Topic
Transactional memory
About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.
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TL;DR: The elastic transaction model and an implementation of it are presented, then its simplicity and performance on various concurrent data structures, namely double-ended queue, hash table, linked list, and skip list are illustrated.
31 citations
Patent•
23 Mar 2006TL;DR: In this article, a software transactional memory system is described, which utilizes decomposed software transaction memory instructions as well as runtime optimizations to achieve efficient performance, such as code movement around procedure calls, addition of operations to provide strong atomicity, removal of unnecessary read-to-update upgrades, and removal of operations for newly-allocated objects.
Abstract: A software transactional memory system is described which utilizes decomposed software transactional memory instructions as well as runtime optimizations to achieve efficient performance. The decomposed instructions allow a compiler with knowledge of the instruction semantics to perform optimizations which would be unavailable on traditional software transactional memory systems. Additionally, high-level software transactional memory optimizations are performed such as code movement around procedure calls, addition of operations to provide strong atomicity, removal of unnecessary read-to-update upgrades, and removal of operations for newly-allocated objects. During execution, multi-use header words for objects are extended to provide for per-object housekeeping, as well as fast snapshots which illustrate changes to objects. Additionally, entries to software transactional memory logs are filtered using an associative table during execution, preventing needless writes to the logs. Finally a garbage collector with knowledge of the software transactional memory system compacts software transactional memory logs during garbage collection.
30 citations
22 Feb 2017
TL;DR: This paper describes an architecture that consists of many lightweight multi-threaded processing engines, a global transactional shared memory, and a work scheduler and argues that despite increased transaction conflicts due to the higher concurrency and single-thread latency, scalable speedup over serial execution can be achieved.
Abstract: Many applications that operate on large graphs can be intuitively parallelized by executing a large number of the graph operations concurrently and as transactions to deal with potential conflicts. However, large numbers of operations occurring concurrently might incur too many conflicts that would negate the potential benefits of the parallelization which has probably made highly multi-threaded transactional machines seem impractical. Given the large size and topology of many modern graphs, however, such machines can provide real performance, energy efficiency, and programability benefits. This paper describes an architecture that consists of many lightweight multi-threaded processing engines, a global transactional shared memory, and a work scheduler. We present challenges of realizing such an architecture, especially the requirement of scalable conflict detection, and propose solutions. We also argue that despite increased transaction conflicts due to the higher concurrency and single-thread latency, scalable speedup over serial execution can be achieved. We implement the proposed architecture as a synthesizable FPGA RTL design and demonstrate improved per-socket performance (2X) and energy efficiency (22X) by comparing to a baseline platform that contains two Intel Haswell processors, each with 12 cores.
30 citations
Book•
01 Jan 2008
TL;DR: This book provides embedded engineers with solid grounding in the skills required to develop software targeting multicore processors, and an in-depth exploration of performance analysis, and a close-up look at the tools of the trade.
Abstract: The multicore revolution has reached the deployment stage in embedded systems ranging from small ultramobile devices to large telecommunication servers The transition from single to multicore processors, motivated by the need to increase performance while conserving power, has placed great responsibility on the shoulders of software engineers In this new embedded multicore era, the toughest task is the development of code to support more sophisticated systems This book provides embedded engineers with solid grounding in the skills required to develop software targeting multicore processors Within the text, the author undertakes an in-depth exploration of performance analysis, and a close-up look at the tools of the trade Both general multicore design principles and processor-specific optimization techniques are revealed Detailed coverage of critical issues for multicore employment within embedded systems is provided, including the Threading Development Cycle, with discussions of analysis, design, development, debugging, and performance tuning of threaded applications Software development techniques engendering optimal mobility and energy efficiency are highlighted through multiple case studies, which provide practical "how-to" advice on implementing the latest multicore processors Finally, future trends are discussed, including terascale, speculative multithreading, transactional memory, interconnects, and the software-specific implications of these looming architectural developments Table of ContentsChapter 1 - Introduction Chapter 2 - Basic System and Processor Architecture Chapter 3 - Multi-core Processors & Embedded Chapter 4 -Moving To Multi-core Intel Architecture Chapter 5 - Scalar Optimization & Usability Chapter 6 - Parallel Optimization Using Threads Chapter 7 - Case Study: Data Decomposition Chapter 8 - Case Study: Functional Decomposition Chapter 9 - Virtualization & Partitioning Chapter 10 - Getting Ready For Low Power Intel Architecture Chapter 11 - Summary, Trends, and Conclusions Appendix I Glossary References * Get up to speed on multicore design! This is the only book to explain software optimization for embedded multicore systems* Helpful tips, tricks and design secrets from an Intel programming expert, with detailed examples using the popular X86 architecture* Covers hot topics including ultramobile devices, low-power designs, Pthreads vs OpenMP, and heterogeneous cores
30 citations
09 Jan 2010
TL;DR: This paper addresses the intrinsic difficulty behind the support for parallel nesting in transactional memory, and proposes a novel solution that is the first practical solution to meet the lowest theoretical upper bound known for the problem.
Abstract: Exploiting the emerging reality of affordable multi-core architectures goes through providing programmers with simple abstractions that would enable them to easily turn their sequential programs into concurrent ones that expose as much parallelism as possible. While transactional memory promises to make concurrent programming easy to a wide programmer community, current implementations either disallow nested transactions to run in parallel or do not scale to arbitrary parallel nesting depths. This is an important obstacle to the central goal of transactional memory, as programmers can only start parallel threads in restricted parts of their code.This paper addresses the intrinsic difficulty behind the support for parallel nesting in transactional memory, and proposes a novel solution that, to the best of our knowledge, is the first practical solution to meet the lowest theoretical upper bound known for the problem.Using a synthetic workload configured to test parallel transactions on a multi-core machine, a practical implementation of our algorithm yields substantial speed-ups (up to 22x with 33 threads) relatively to serial nesting, and shows that the time to start and commit transactions, as well as to detect conflicts, is independent of nesting depth.
30 citations