scispace - formally typeset
Search or ask a question
Topic

Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.


Papers
More filters
Proceedings ArticleDOI
30 Aug 2011
TL;DR: This paper defends that the amount of contention can be reduced if read-only transactions access recent consistent data snapshots, progressing in a wait-free manner, and shows how the required number of versions of a shared object can be calculated for a set of tasks.
Abstract: The recent trends of chip architectures with higher number of heterogeneous cores, and non-uniform memory/non-coherent caches, brings renewed attention to the use of Software Transactional Memory (STM) as a fundamental building block for developing parallel applications. Nevertheless, although STM promises to ease concurrent and parallel software development, it relies on the possibility of aborting conflicting transactions to maintain data consistency, which impacts on the responsiveness and timing guarantees required by embedded real-time systems. In these systems, contention delays must be (efficiently) limited so that the response times of tasks executing transactions are upper-bounded and task sets can be feasibly scheduled. In this paper we assess the use of STM in the development of embedded real-time software, defending that the amount of contention can be reduced if read-only transactions access recent consistent data snapshots, progressing in a wait-free manner. We show how the required number of versions of a shared object can be calculated for a set of tasks. We also outline an algorithm to manage conflicts between update transactions that prevents starvation.

28 citations

Proceedings ArticleDOI
11 Jun 2018
TL;DR: This work aims to clarify the interplay between weak memory and TM by extending existing axiomatic weak memory models with new rules for TM with a key finding that a proposed TM extension to ARMv8 currently being considered within ARM Research is incompatible with lock elision without sacrificing portability or performance.
Abstract: Weak memory models provide a complex, system-centric semantics for concurrent programs, while transactional memory (TM) provides a simpler, programmer-centric semantics. Both have been studied in detail, but their combined semantics is not well understood. This is problematic because such widely-used architectures and languages as x86, Power, and C++ all support TM, and all have weak memory models. Our work aims to clarify the interplay between weak memory and TM by extending existing axiomatic weak memory models (x86, Power, ARMv8, and C++) with new rules for TM. Our formal models are backed by automated tooling that enables (1) the synthesis of tests for validating our models against existing implementations and (2) the model-checking of TM-related transformations, such as lock elision and compiling C++ transactions to hardware. A key finding is that a proposed TM extension to ARMv8 currently being considered within ARM Research is incompatible with lock elision without sacrificing portability or performance.

28 citations

Proceedings ArticleDOI
24 Aug 2009
TL;DR: Experimental results show that RT-STM can improve the performance of transactional memory-based applications on multicore platforms and explore a new heuristic for conflict resolution that reduces the number of deadline violations when scheduling soft real-time transactions.
Abstract: Transactional memory is currently a hot research topic, having attracted the focus of both academic researchers and development groups at companies. Indeed, the concept of transactional memory has recently attracted much interest for multicore systems as it eases programming and avoids the problems of lock-based methods. However, up to now, the scheduling of real-time transactions within software transactional memories has not been studied. To address this issue, we present in this paper a real-time software transactional memory, namely RT-STM. We focus on the scheduling of concurrent soft real-time transactions. In particular, we explore a new heuristic for conflict resolution that reduces the number of deadline violations when scheduling soft real-time transactions. After having discussed the scalability of various classical STMs under a real-time operating system, we present experimental results that show that RT-STM can improve the performance of transactional memory-based applications on multicore platforms.

28 citations

Proceedings Article
01 Jan 2007
TL;DR: The Transactional Memory module of the Glasgow Haskell Compiler (GHC) 6.6 is extended to support a construct that allows the removal of a transactional variable from the readset, called unreadTVar, which can significantly improve execution time and memory usage when traversing transactional linked structures.
Abstract: As new trends in computer architecture lead towards shared-memory chip multiprocessors (CMP), the rules for programming these machines are significantly changing. In the search for alternatives to deadlock-prone lock-based concurrency protocols, Software Transactional Memory (STM) extensions to Haskell have provided an easy-to-use lock-free abstraction mechanism for concurrent programming, using atomically composed blocks operating on transactional variables. However, as in the case for linked structures, the composition of these atomic blocks require extra attention, as the transactional management might act overconservatively by keeping track of more variables than necessary, causing an overall decrease in performance. To remedy this situation, we have extended the Transactional Memory module of the Glasgow Haskell Compiler (GHC) 6.6 to support a construct that allows the removal of a transactional variable from the readset. Although this construct that we term unreadTVar, when not applied carefully, might put the strong atomicity guarantees of STM at risk, the experimentations done with linked lists and binary trees show that it can significantly improve execution time and memory usage when traversing transactional linked structures. 1Barcelona Supercomputing Center, Barcelona/Spain; Email:{nehir.sonmez,cristian.perfumo,srdjan.stipic,adrian.cristal, osman.unsal,mateo.valero}@bsc.es 2Computer Architecture Department – Universitat Politecnica de Catalunya

28 citations

Book ChapterDOI
26 Mar 2011
TL;DR: This paper introduces a revision calculus that concisely captures the programming model and proves that the calculus is confluent and guarantees determinacy, and shows that the consistency guarantees of the calculus are a logical extension of snapshot isolation with support for conflict resolution and nesting.
Abstract: Enabling applications to execute various tasks in parallel is difficult if those tasks exhibit read and write conflicts. We recently developed a programming model based on concurrent revisions that addresses this challenge in a novel way: each forked task gets a conceptual copy of all the shared state, and state changes are integrated only when tasks are joined, at which time write-write conflicts are deterministically resolved. In this paper, we study the precise semantics of this model, in particular its guarantees for determinacy and consistency. First, we introduce a revision calculus that concisely captures the programming model. Despite allowing concurrent execution and locally nondeterministic scheduling, we prove that the calculus is confluent and guarantees determinacy. We show that the consistency guarantees of our calculus are a logical extension of snapshot isolation with support for conflict resolution and nesting. Moreover, we discuss how custom merge functions can provide stronger guarantees for particular data types that are tailored to the needs of the application. Finally, we show we can visualize the nonlinear history of state in our computations using revision diagrams that clarify the synchronization between tasks and allow local reasoning about state updates.

28 citations


Network Information
Related Topics (5)
Compiler
26.3K papers, 578.5K citations
87% related
Cache
59.1K papers, 976.6K citations
86% related
Parallel algorithm
23.6K papers, 452.6K citations
84% related
Model checking
16.9K papers, 451.6K citations
84% related
Programming paradigm
18.7K papers, 467.9K citations
83% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202316
202240
202129
202063
201970
201888