Showing papers on "Transistor published in 1968"

Modeling and simulation of insulated-gate field-effect transistor switching circuits

Abstract: A new equivalent circuit for the insulated-gate field-effect transistor (IGFET) is described. This device model is particularly useful for computer-aided analysis of monolithic integrated IGFET switching circuits. The results of computer simulations using the new equivalent circuit are in close agreement with experimental observations. As an example of a practical application, simulation results are shown for an integrated circuit IGFET memory cell.

Determination of Threshold Failure Levels of Semiconductor Diodes and Transistors Due to Pulse Voltages

Abstract: Theoretical predictions of circuit failure in an Electromagnetic Pulse (EMP) environment require a knowledge of failure levels for each component of the circuit due to surge voltages or currents. For most circuits, the semiconductor devices are the weakest elements with respect to such failure. This paper presents the results of an extensive experimental program to determine pulse power failure levels of semiconductor junctions. Approximately 80 different types of silicon diodes and transistors were studied with variations in junction areas from 10-4to 10-1 cm2 and with widely varying junction geometries. Power levels of up to two kilowatts, with time durations of 0.1 to 20 microseconds, were applied to semiconductor junctions in both forward and reverse polarity modes. A semi-empirical formula, based on experimental data and on a simple thermal failure model is given. From the formula one can make order-of-magnitude estimates of the failure level as a function of pulse length for many silicon diodes or transistors whose junction area is known.

SB-IGFET: An insulated-gate field-effect transistor using Schottky barrier contacts for source and drain

Abstract: Insulated-gate field-effect transistors using Schottky barrier contacts for the source and drain have been studied. At room temperature, the device characteristics are Comparable to conventional IGFET's with similar electrode geometry. At lower temperatures, the current transport is by tunneling of carriers from the metal across the Schottky barrier to the semiconductor inversion layer.

The temperature dependence of ideal gain in double diffused silicon transistors

Abstract: Theoretical treatments predict higher injection efficiency for double diffused silicon transistors than the experimentally observed values. This paper shows that the discrepancy can be partly explained by the difference in the effective energy gaps in the emitter and base regions. Coulomb interaction of the free carriers results in lower energy gap in the heavily doped emitter than in the rest of the transistor. The difference in the energy gaps is experimentally determined from the activation energy difference of the emitter-current and the ideal component of the base Current. It is concluded that too much doping in the emitter lowers the transistor gain, increases the temperature dependence of the gain, and results in a higher excess noise.

High voltage integrated circuit transistor

Abstract: TERING NORMAL COLLECTOR-EMITTER BREAKDOWN, BECAUSE THE FIELD INTENSITY IN THE COLLECTOR-BASE CHARGE LAYER IS LIMITED. AN INTEGRATED CIRCUIT TRANSISTOR INCLUDES A SUBSTRATE AND AN EPITAXIALLY GROWN SEMICONDUCTOR MATERIAL THEREON PROVIDING A THREE-LAYER TRANSISTOR COMPRISING A COLLECTOR LAYER, AN EMITTER LAYER, AND A BASE LAYER THEREBETWEEN. THE COLLECTOR LAYER IS CHARACTERIZED BY VIRTUALLY COMPLETE DEPLETION OF MAJORITY CARRIERS AT A COLLECTOR-EMITTER VOLTAGE LESS THAN THE VOLTAGE AT WHICH COLECTOR-EMITTER BREAKDOWN WOULD OTHERWISE OCCUR. AS A RESULT, THE COLLECTOR-EMITTER VOLTAGE MAY BE INCREASED WITHOUT ENCOUN-

ZnO field-effect transistor

Abstract: Fabrication of experimental insulated-gate field-effect transistors on single crystal ZnO is described. Measured transconductance of 10 µmhos is two orders of magnitude smaller than that predicted for this structure by the Hall mobility of 220 cm2/V ċ s. Threshold voltage indicates relatively large values of surface states and/or insulator charge.

Hybrid integrated lumped-element microwave amplifiers

Abstract: This paper describes the development of microwave lumped-element thin-film amplifiers. The basic design philosophy underlying lumped inductors and capacitors at microwave frequencies is reviewed, showing how Q's of 100 are achieved. A variety of tunable input, output, and interstage integrated lumped-element networks for transistor amplifiers were fabricated. The gain and efficiency of 2-GHz class-C operated transistors mounted in these circuits were comparable with the best performance achieved by the same transistors in less lossy coaxial circuits. The measured losses (1.2 dB) at 2 GHz were very close to those calculated using the design parameters. Single-stage amplifiers at 2 GHz achieved one watt of output power with 4 dB of gain. At somewhat lower power levels more than 6 dB of gain was achieved. The circuits allowed the operation of low-power level class-A amplifiers with over 13 dB of gain. Cascaded operation yielded more than 17 dB of gain with 0.8 watts of CW power. It is concluded that lumped elements can be fabricated by thin-film technology and will play an important role in microwave integrated circuits.

IF Amplifier using C/SUB c/ compensated transistors

Abstract: An integrated bridge network of four transistors is used as a self-neutralized active element in tuned RLC amplifier designs. The bridge network compensates for the transistor collector-base junction capacitance (C/SUB c/), yielding a 95-percent reduction in the common-emitter reverse transmission admittance. IF amplifier stages that achieve the maximum unilateral power gain of a common-emitter transistor while maintaining excellent alignability are realized using the C/SUB c/ compensated transistor structure. Variations of the relative bias current levels of the transistors in the bridge network provides gain control by way of signal cancellation. This technique produces minimal frequency response variations of the amplifier stage being controlled. A noise analysis shows output signal to noise ratio at maximum attenuation can be a performance limitation.

Semiconductor process for joining a transistor chip to a printed circuit

Abstract: A METHOD OF ATTACHING TRANSISTORS TO PRINTED CIRCUITS OR MICROCIRCUITS BY EMPLOYING CONDUCTIVE PILLARS BONDED OR WELDED TO CONTACT AREAS ON EACH. THE PILLARS ARE FIRST ATTACHED TO CONTACT AREAS ON THE TRANSISTOR CHIP.

Transistor-transistor logic with high packing density and optimum performance at high inverse gain

Abstract: The advantages of using thin epitaxial layers for bipolar integrated circuits are discussed in this paper. Using epitaxial layer thicknesses of ~ 1 /spl mu/ and a low-voltage form of transistor-transistor logic, packing densities of 10/SUP 5/ logic gates/in/SUP 2/ have been achieved. The power x delay product of the circuits was 5 pJ. The transistors were formed in 1 /spl mu/ thick epitaxial layers and have inverse common-emitter current gains of 2 to 3. These high inverse gains make practical some new circuit configurations, including a dual-emitter inverter with reduced storage time. The thin epitaxial layer may be p type, rather than the usual n type, and this makes possible a new isolation scheme that allows the fabrication of bipolar integrated circuits using only five photolithographic steps.

The equivalent circuit of a transistor with a lightly doped collector operating in saturation

Abstract: This paper analyses the circuit behaviour of saturated transistors that have the base more heavily doped than the collector. The emphasis is on the small-signal response, although the switching characteristics can also be derived from the results. It is shown that, by making reasonable assumptions, the minority carrier density can be found throughout the collector region, and hence the total stored charge in the collector can be calculated. This leads to a small-signal equivalent circuit for the saturated transistor, the accuracy of which is compared with measurements. Finally the relevance of the results to the problem of making transistors with good forward AGC characteristics is discussed.

Pulse width modulator with pulse width limiting

Abstract: A power control circuit for a battery-operated DC traction motor having an inverter providing a series of reference pulses defining periods therebetween, a pulse width modulator receiving said reference pulses and including a monostable multivibrator for generating a power pulse at sometime after the start of the period, power switch transistor means responsive to said power pulses to connect the motor with the battery source, and a pulse width limiting circuit including a controlled rectifier for prenaturely terminating the power pulse within the period in response to sensing of a predetermined overcurrent condition of the motor or power switching transistor means during said period.

High-efficiency power amplifier

Abstract: Described is a high-efficiency Class B power amplifier which operates at essentially 100 percent efficiency for all output voltages, either direct current or alternating current. This is accomplished by utilizing in the amplifier switching transistors in combination with chokes, the arrangement being such that unwanted voltages appear across the chokes at any instant. The chokes, being energy storing devices, can deliver their stored energy to the load after the transistors are turned off.

Electronically controlled timepiece using low power mos transistor circuitry

Abstract: THERE IS DISCLOSED HEREIN AN ELECTRONICALLY CONTROLLED TIMEPIECE SUITABLE FOR USE AS A WRIST WATCH EMPLOYING AN ELECTRONIC OSCILLATOR OPERATING AT A FREQUENCY SUBSTANTIALLY IN EXCESS OF THE DESIRED TIMEKEEPING RATE, FREQUENCY REDUCTION CIRCUITRY FORMED OF A SERIES OF TRANSISTOR STAGES OPERATIVE IN RESPONSE TO CHANGES IN VOLTAGE RATHER THAN CUR- RENT OR POWER LEVEL CHANGES TO PRODUCE TIMING SIGNAL OF THE REQUIRED FREQUENCY, ACTUATING MEANS RESPONSIVE TO THE TIMING SIGNAL AND A TIME DISPLAY OPERATED BY THE ACTUATING MEANS.

Semiconductor integrated circuit having mis and bipolar transistor elements

Abstract: MIS and bipolar transistor elements are provided within a unitary body of semiconductor material wherein first and second regions of opposite conductivity type to that of the substrate provide source and drain regions between which is positioned an insulated gate electrode for the MIS transistor while in a region that may be the same as one of the source and drain regions or an additional region, elements of the bipolar transistor are provided with utilization of the substrate as a collector region or by having laterally disposed emitter and collector regions in a base region.

Current regulator controlled by voltage across semiconductor junction device

Abstract: A CURRENT REGULATING CIRCUIT OR CURRENT SOURCE INCLUDES A FIRST TRANSISTOR CONNECTED IN SERIES WITH A SEMICONDUCTOR JUNCTION DEVICE FOR DEVELOPING A VOLTAGE PROPORTIONAL TO THE CURRENT FLOWING THROUGH SUCH FIRST TRANSISTOR. A SEONCD TRANSISTOR HAS ITS BASE CONNECTED TO THE SEMICONDUCTOR JUNCTION DEVICE WHEREBY CURRENT IN THE SECOND TRANSISTOR IS MODIFIED IN RESPONSE TO THE VOLTAGE ACROSS THE JUNCTION DEVICE. IN TURN, THE COLLECTOR OF THE SECOND TRANSISTOR IS CONNECTED SO THAT IT CONTROLS THE FIRST TRANSISTOR IN A SENSE FOR OPPOSING CHANGE IN THE OUTPUT CURRENT OF THE FIRST TRANSISTOR. THE SEMICONDUCTOR JUNCTION DEVICE PREFERABLY COMPRISES THE BASE-EMITTER JUNCTION OF A THIRD TRANSISTOR, AND ALL THREE TRANSISTORS ARE DESIRABLY FABRICATED UPON A COMMON SEMICONDUCTOR INTEGRATED CIRCUIT STRUCTURE.

Schottky-barrier field-effect transistor

Abstract: A Schottky-barrier field-effect transistor is disclosed with a semiconductor channel of relatively low conductivity between the source and drain electrodes which may be electrically influenced by a Schottky-barrier gate electrode located on the semiconductor channel. The transistor is characterized by a zone or region of higher conductivity which extends from the vicinity of the source electrode to near the gate electrode. Further, source and drain regions are conveniently provided for the transistor of semiconductor of the same conductivity type as the channel semiconductor at the Schottky-barrier electrode. Advantageously, the drain region may be made of semiconductor of high conductivity and the same conductivity type as the source region. The high conductivity region may be achieved through either diffusion or epitaxial growth technique.

Semiconductor circuit devices using insulated gate-type field effect elements having protective diodes

Abstract: Insulated gate-type field effect transistors used in capacitive memory circuits and having protective diodes for protecting the insulating films below the gate electrodes from electrical breakdown, in which parasitic transistor action which might be caused by minority carriers injected into semiconductor substrates by noise signals applied to the protective diodes are eliminated by means for suppressing the injection of minority carriers or by means for preventing injected minority carriers from reaching the drain regions of the field effect transistors.

Surface-diffused transistor with isolated field plate

Abstract: A surface-diffused transistor exhibiting high stability and low collector capacitance includes a metallic field plate buried within an insulating film which covers the active major wafer surface thereof and passivates a surface-adjacent collector junction. Metal field plate is fixed to a negative potential and prevents inversion of a surface-adjacent region of the P-type semiconductor, thereby preventing surface leakage and increased capacitance.

The Schottky-barrier-collector transistor

Abstract: In saturated switching conventional n-p-n or p-n-p junction bipolar transistors the turn-off speed is limited by storage-time. The conventional way to reduce storage time is to control minority-lifetime by gold-doping. But gold-doping also decreases β, which is proportional to the minority lifetime, hence cannot eliminate the problem. The storage-time can be practically eliminated by replacing the conventional p-n collector junction by a Schottky-barrier, with the metallic side forming the collector region. This eliminates the injection of minority-carriers from the collector into the base region, as well as minority charge storage in the collector region. Theoretically the storage-time is thereby approximately β times less than that of the best possible gold-doped transistor with similar geometry and β.

Automatic gain control rf-if amplifier

Abstract: Disclosed is a differential amplifier circuit featuring electronic gain control, and this circuit may be constructed in monolithic integrated form. In one embodiment of the invention, first and second pairs of differentially coupled transistors are connected respectively to first and second differentially coupled input transistors, and the input transistors are connectable to a source of differential input signals. Differential output signals are derived at the outputs of transistors in each of the pairs of transistors, and by applying an automatic gain control (AGC) signal at a node which is common to the transistor pairs, electronic gain control is obtained without a differential signal arising therefrom. In another embodiment of the invention, an output differential amplifier stage is directly coupled to transistors in the first and second pairs of transistors so that any common mode signal present there is rejected in said output stage.

Brushless d.c. motor

Abstract: 1,240,880. Brushless motors. AKAI ELECTRIC CO. Ltd. 6 Aug., 1968 [8 Aug., 1967], No. 37404/68. Heading H2A. Star-connected phase windings L1, L2, L3 forming the stator of a permanent magnet rotor motor are energized from a D.C. supply through transistors Tr2, Tr4, Tr6 which are connected in a ring oscillator circuit 10, supplied through voltage and current control circuits 12, 11, and are rendered conducting by the voltage induced in successive windings. Each stage of the oscillator comprises two directly coupled transistors Tr3, Tr4 having the collector of Tr4 connected to phase winding L2. The input to the stage is coupled to the output of the previous stage through capacitor C1 and integrating circuit R4, C4 and similarly for the other stages. In operation the voltage across resistor R10 will alter with supply fluctuations and this voltage will be transmitted to base of transistor TR7 through VR and will set a voltage at one end of Zener diode ZD. Voltages at the ends of the phase windings will be rectified by diodes D1, D2, D3 and are applied to the other end of ZD and can thereby produce a current flow in resistor R10 thus causing the conductive state of TR8 to change. This charge in voltage will also occur when rotor speed changes and thus the circuits 11 and 12 act to maintain a constant rotor speed. The speed of the motor is varied by altering VR and switch SW2 is used to by-pass the current control circuit 11 so that a higher speed can be obtained.

Phototransistor operation in the charge storage mode

Abstract: Phototransistor performance is considered for the charge storage mode, in which the phototransistor is briefly pulsed and then permitted to remain with both junctions reverse-biased while in the presence of illumination. The charge delivered with the next pulse is proportional to the integral of light received since the last pulse. A lumped model of the transistor, amended here to account for photogeneration, is presented which employs the relative excess densities of minority carriers as the terminal variables. By using the relative excess densities as variables, both the drift and diffusion components of current transported through a nonuniformly doped base region may be represented by a single element. In addition, all of the elements in the model are measured in electrical units, which allows simple use of the model without bringing in the detailed physics unless desired. Simple experimental measurements are outlined by which parameter values are determined, and the results for a particular device are presented. Using the model, a complete analysis of phototransistor operation in the charge storage mode is presented. The equations derived in the analysis are solved on a computer using the measured values of transistor parameters. The peak output voltage is predicted as a function of the light-generated current, along with the time response of the base-emitter and output voltages. The precise correspondence of the computed and measured results verifies the accuracy of both the model and the analysis.

Wafer-chip assembly for large-scale integration

Abstract: A technique has been developed for achieving a very high density interconnection of active silicon devices to permit the fabrication of large electronic subsystems in essentially monolithic form. The technique has been used to assemble a MOS 2000-bit shift register containing 12 000 MOS transistors on a 300 by 600 mils silicon substrate. The register utilizes ten 200-bit shift-register chips, each containing 1200 transistors. Four-phase MOS logic techniques are used to obtain very low power (0.1 mW/bit) and/or high frequency (10 MHZ) operation. In the technique used to assemble the 2000-bit shift register, silicon large-scale array chips are face-down bonded in adjoining positions on a larger silicon wafer section which may contain additional layers of interconnections and/or active devices as required to form a complete system subassembly. Since the same photoengraving technology is used in the substrate as on the chips, very high packing densities can be achieved, with minimum chip area required for interconnections. This approach also minimizes the parasitic capacitance associated with more conventional techniques for encapsulating and interconnecting large-scale arrays. In the case of MOS circuits, large area-buffer devices are not needed due to the small capacitance in the wafer-chip interconnections. Various techniques have been evolved for processing the chips and substrates produce contact regions which permit the required high fabrication yields. The bonding conditions and metallurgical systems used to date in fabricating large shift-register assemblies will be described and compared with other approaches.

Transistor switch with minimized transition power absorption

Abstract: A transistor switch, an inductor and the load are serially connected so that during turn-on transition of the transistor, the inductor holds back current flow until the transistor is saturated. A capacitor paralleled around the transistor charges during turnoff transition so that current through the transistor during transition is minimized to minimize power absorption therein.

Field effect transistors for integrated circuits and methods of manufacture

Abstract: P-channel field-effect transistors are described which include a silicon substrate with an N-type epitaxial layer on one face thereof and an N-type subepitaxial diffused region which extends in one direction into a P-type region in the face of the substrate and in the opposite direction into the epitaxial layer to form a junction with a P-type diffused channel region extending partially into the epitaxial layer. These P-channel transistors may constitute a portion of an integrated circuit including a complementary N-channel field effect transistor and/or vertical and surface bipolar NPN and PNP transistors and resistors. Processes are disclosed for forming such transistors wherein a P-type diffusion in an epitaxial layer and an N-type diffused subepitaxial region are further diffused to form a junction therebetween.