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Showing papers on "Transistor published in 1970"


Journal ArticleDOI
R.C. Joy1, E.S. Schlig1
TL;DR: In this paper, a mathematical model of the three-dimensional transient heat flow problem is presented which takes into account the physical structure of the device and the actual region of power dissipation.
Abstract: Recent predictions that thermal effects will limit future transistor speed improvement motivated an interest in predicting and measuring these effects. A mathematical model of the three-dimensional transient heat flow problem is presented which takes into account the physical structure of the device and the actual region of power dissipation. At any point within the device, the model predicts the time-dependent temperature response to a change in power dissipation. A new method of measuring the local time-dependent thermal behavior of small bipolar transistors is described and used to verify the model. It was found that the thermal spreading resistance becomes important in silicon transistors when the emitter stripe dimensions approach 1 µ. Furthermore, the thermal response is much slower than the electrical response. Also, it was confirmed that adjacent devices in integrated circuits are essentially thermally isolated as far as thermal spreading resistance is concerned.

162 citations


Journal ArticleDOI
Dante M. Tasca1
TL;DR: In this paper, the permanent damage levels associated with a number of different devices and failure mechanisms associated with each were determined both for positive and negative polarity pulses at different conditions of quiescent bias and pulse width.
Abstract: Semiconductor devices operating under both biased and unbiased conditions are vulnerable to permanent damage from relatively moderate levels of pulsed electrical energy, particularly of submicrosecond pulse duration. An experimental study was performed to determine the permanent damage levels associated with a number of different devices and to identify the failure mechanisms associated with each. The device types investigated included general purpose and high speed computer diodes, a medium power diode, medium frequency and UHF transistor amplifiers, and a dielectrically isolated diode gate expander. The permanent damage levels associated with these devices were determined both for positive and negative polarity pulses at different conditions of quiescent bias and pulse width. The pulse duration times included the range of 30 to 300 nanoseconds, and in some instances, up to 1 microsecond. Failure models for both thermal second breakdown induced damage to the semiconductor junction and thermal damage to the device interconnecting leads and metallization patterns were also developed.

160 citations


Journal ArticleDOI
P. Wolf1
TL;DR: In this paper, the microwave properties of the Schottky-barrier field effect transistor (MESFET) with a gate-length of one micrometer are investigated.
Abstract: The microwave properties of silicon Schottky-barrier field-effect transistor(MESFET'S) with a gate-length of one micrometer are investigated. The scattering parameters of the transistors have been measured from 0.1 GHz up to 12 GHz. From the measured data an equivalent circuit is established which consist of an intrinsic transistor and extrinsic elements. Some of the elements of the intrinsic transistor, notably the transconductance, are strongly influenced by the saturation of the drift velocity. Best performance of the intrinsic transistor is obtained with highly doped and thin channels. The measured power-gain is in good agreement with theoretical values deduced from the equivalent circuit. The best device has a maximum frequency of oscillation fmax of 12 GHz. The investigation reveals that the extrinsic elements, especially the resistance of the gate-metallization and the gate-pad parasitics, degrade the power-gain considerably. Without them a value of fmax close to 20 GHz is predicted.

153 citations


Journal ArticleDOI
TL;DR: In this paper, the authors describe the technology and characteristics of insulated-gate field effect transistor integrated circuits using deposited polycrystalline silicon as the gate electrode, and a comparison between silicon gate technology and standard technology is carried out, using the 3705, an eight-channel multiplexer switch with decoding logic.
Abstract: This paper describes the technology and characteristics of insulated-gate field-effect transistor integrated circuits using deposited polycrystalline silicon as the gate electrode. After a brief outline of the characteristics of the silicon gate technology, some of the basic properties of the silicon-silicon dioxide-silicon system, the processing steps for the fabrication of silicon-gate devices, and the electrical characteristics of the devices obtained will be reviewed. A comparison between silicon gate technology and standard technology will be carried out, using the 3705, an eight-channel multiplexer switch with decoding logic. Design considerations for silicon gate technology and some design examples will be given.

116 citations


Journal ArticleDOI
D. P. Kennedy1, R. R. O'Brien1
TL;DR: In this paper, a two-dimensional analysis of the mechanisms of operation for a junction field effect transistor is presented, focusing on the process of electric current saturation in both wide gate and narrow gate structures.
Abstract: A two-dimensional analysis is presented of the mechanisms of operation for a junction field-effect transistor. Particular emphasis is placed upon the process of electric current saturation in both wide gate and narrow gate structures. It is shown that velocity saturated carrier transport in a source-drain channel produces heretofore unreported mechanisms of device operation. Comparisons made between the conclusions derived from this two-dimensional analysis and the conventional one-dimensional theory of JFET operation are presented in graphic form.

110 citations


Journal ArticleDOI
D. Frohman-Bentchkowsky1
01 Aug 1970
TL;DR: In this article, the authors present a unified approach to the characterization of both stable and variable turn-on voltage MNOS transistors, based on an extensive investigation of charge transport and storage in MNOS structures.
Abstract: Recent advances in silicon nitride deposition techniques have led to the emergence of the metal-nitride-oxide-silicon (MNOS) integrated circuit technology as an alternative and supplement to the existing MOS technology. Applications of MNOS field-effect transistors have been proposed for both logic circuits (as an alternative to MOS transistors) and nonvolatile memory arrays This paper reviews the characteristics and applications of MNOS transistors. It presents a unified approach to the characterization of both stable and variable turn-on voltage MNOS transistors. The analysis is based on an extensive investigation of charge transport and storage in MNOS structures. The different modes of transistor operation are described and analyzed in terms of the physical parameters of the two-layer dielectric structure. Understanding of the physical mechanisms underlying transistor operation is applied to the optimization of transistor structure and performance for different digital integrated circuit applications. The feasibility of these applications is demonstrated by fabrication of a nonvolatile semiconductor storage array and a nonvolatile flip-flop.

87 citations


Patent
Barrie Gilbert1
13 Apr 1970
TL;DR: In this article, a wideband differential amplifier comprises a pair of differentially connected control devices, for example transistors, coupled with semiconductor junction input devices coupled for receiving complementary input currents, whereby a linear rather than a nonlinear amplifier current output is produced.
Abstract: A wideband differential amplifier comprises a pair of differentially connected control devices, for example transistors, having a pair of semiconductor junction input devices coupled thereto for receiving complementary input currents. The input devices exhibit logarithmic characteristics substantially compensating for nonlinear properties of the pair of differentially connected control devices, whereby a linear rather than a nonlinear amplifier current output is produced. Multipliers, cascaded amplifiers, and other useful circuit configurations are provided.

82 citations


Journal ArticleDOI
B.V. Gokhale1
TL;DR: In this article, the authors describe a technique of obtaining numerical solutions of the basic carrier transport equations for a semiconductor and the results of some calculations pertaining to a silicon n-p-n transistor.
Abstract: This paper describes a technique of obtaining numerical solutions of the basic carrier transport equations for a semiconductor and the results of some calculations pertaining to a silicon n-p-n transistor. The calculations include dc characteristics in direct and inverse operation, saturation parameters, and small-signal ac common emitter h -parameters. Both Boltzmann and Fermi statistics have been used, and the dependence of carrier mobilities on electric field has been taken into account.

70 citations


Journal ArticleDOI
TL;DR: In this article, the inverted common collector transistor resonator filters were analyzed in terms of the input immittance parameters, and a design procedure for the resulting circuitry was suggested, and the stability of the resultant circuitry was discussed.
Abstract: In this paper "inverted common collector" transistor resonator filters will be analyzed. Simple formulas will be presented for the input immittance parameters, in terms of the bridged-T equivalent network and in terms of the common-emitter Y parameters. A design procedure is suggested, and a design example given. Stability of the resultant circuitry is discussed.

65 citations


Patent
Yuichi Haneta1
02 Jun 1970
TL;DR: A field effect transistor is a gate assembly comprising a sandwich of a layer of silicon oxide with excess silicon between two insulating films of appropriate thickness for the entrapment of charge carriers in the silicon-rich silicon oxide layer.
Abstract: A field effect transistor is provided with a gate assembly comprising a sandwich of a layer of silicon oxide with excess silicon between two insulating films of appropriate thickness for the entrapment of charge carriers in the silicon-rich silicon oxide layer. Such entrapment provides the transistor with information storage capabilities in which information can be stored for a long time and readily erased or modified.

50 citations


Journal ArticleDOI
TL;DR: In this paper, an analytical approach to the design of power transistors with an empirically derived method of predicting failure under conditions of thermal fatigue is presented. But the authors do not consider the impact of thermal cycling of the transistor on the performance of the transistors.
Abstract: In silicon power transistor applications, thermal cycling of the transistor may activate a failure mechanism called thermal fatigue. This phenomenon is caused by the mechanical stresses set up by the differential in the thermal expansions of the various materials used in the assembly and heat sink of the transistor. Thermal fatigue often results in cracking of the silicon pellet or failure at the silicon mounting interface. This paper discusses the two types of interfaces encountered in power-transistor chip mounting. In type I (hard-solder) systems, the stress-strain relationship is treated in the elastic region. In type II (soft-solder) systems, the stress-strain relationship is plastic in that at least one component exhibits material flow. For the type I systems, a method is suggested for calculation of the forces acting at each interface. For type II systems, an empirical approach to predicting the number of cycles to failure is given. Accelerated testing techniques for thermal-fatigue evaluation are suggested, and a method of predicting performance for various mounting systems is given. This method uses an equation of the form N = A_{0}e^{(\gamma0/H)} . This paper combines an analytical approach to the design of power transistors with an empirically derived method of predicting failure under conditions of thermal fatigue.

Journal ArticleDOI
K.E. Drangeid1, R. Sommerhalder1, W. Walter1
TL;DR: In this paper, it was shown that gallium arsenide is a well suited material for high-frequency field effect transistors and that the frequency limit for power amplification is considerably higher than for other known transistors.
Abstract: The letter shows that gallium arsenide is a well suited material for high-frequency field-effect transistors. From preliminary measurements on realised transistors, it is shown that the frequency limit for power amplification is considerably higher than for other known transistors. The processes involved are briefly described.

Journal ArticleDOI
01 Jan 1970
TL;DR: A computer program for both analog and digital circuits that formulates and solves nonlinear equations for d.c. node voltages and transistor operating points is described and can be effectively simulated.
Abstract: A computer program for both analog and digital circuits that formulates and solves nonlinear equations for d.c. node voltages and transistor operating points is described. Temperature variations and dependence can be effectively simulated.

Patent
28 Dec 1970
TL;DR: In this article, the solenoid coil is serially connected to a first transistor circuit operating as an on-off switch and to a second transistor circuit connected parallel to the first transistor and operating to variably control the voltage applied to the soleneoid.
Abstract: A circuit for initially applying an unusually large drive voltage to a solenoid coil and for subsequently reducing the applied voltage during the travel of the solenoid plunger. The solenoid coil is serially connected to a first transistor circuit operating as an on-off switch and to a second transistor circuit connected parallel to the first transistor circuit and operating to variably control the voltage applied to the solenoid. A capacitor-charge timing circuit controls the variable transistor and thereby gradually reduces the voltage applied to the solenoid.

Journal ArticleDOI
TL;DR: In this paper, the authors calculated the noise resistance of the field effect transistor taking into account high-field effects such as mobility saturation and hot carrier temperature upon the thermal noise, and compared it with measurements of the noise of a junction gate FET and a MOS tetrode with short active channels.
Abstract: The noise resistance of the field-effect transistor has been calculated taking into account high-field effects such as mobility saturation and hot carrier temperature upon the thermal noise. The result of the calculations can be represented by a practical formula. The calculated results have been compared with measurements of the noise of a junction gate FET and a MOS tetrode with short active channels. The agreement is reasonable. At room temperature the effect is moderate, but at low temperatures it is considerable.

Patent
18 Sep 1970
TL;DR: In this article, a diode having low breakdown is established by forming P+type regions or N+ type regions in electrical communication with the resistor so that the diode breakdown is effectively dominated by the impurity concentration characteristics of the P+ type or N + type regions.
Abstract: In a CMOS integrated circuit of the type which includes a diffused P type region in which the N type transistors are formed, a resistor-region is provided by diffusion at the same time as that P type region. A diode having low breakdown is established by forming P+ type regions or N+ type regions in electrical communication with the resistor so that the diode breakdown is effectively dominated by the impurity concentration characteristics of the P+ type or N+ type regions.

Journal ArticleDOI
TL;DR: In this paper, a general model for the transient behaviour of m.i.s. memory transistors is presented and applied to a practical memory transistor which has an insulator layer consisting of 500-1000 A silicon nitride on 15-25 A silicon dioxide.
Abstract: A general model for the transient behaviour of m.i.s. memory transistors is presented. The model is applied to a practical memory transistor which has an insulator layer consisting of 500–1000 A silicon nitride on 15–25 A silicon dioxide. The properties of this device are calculated and are shown to agree with experimental data.

Patent
Balthasar H Pinckaers1
27 Aug 1970
TL;DR: In this article, an alternating current contactor or relay which can be used for control of equipment such as refrigeration compressors is disclosed with a minimum off-time control including a resistor-capacitor timing circuit which charges initially from a power source through a transistor, and this is held in a charged condition while the current continues to flow through the transistor to energize a solid-state switch which energizes the contactor.
Abstract: An alternating current contactor or relay which can be used for control of equipment such as refrigeration compressors is disclosed with a minimum off-time control. The minimum off-time control includes a resistor-capacitor timing circuit which charges initially from a power source through a transistor, and this is held in a charged condition while the current continues to flow through the transistor to energize a solid-state switch which energizes the contactor. In the event that a momentary interruption of power occurs, or in the event that power is removed, the capacitor starts to slowly discharge activating a second transistor circuit that shorts out the first transistor so that the output switch cannot be reenergized for some minimum period of time.

Journal ArticleDOI
TL;DR: In this paper, the gate voltage hysteresis attributed to trapping of charge carriers on oxide near the silicon oxide interface, and the traps follow a time constant dispersion of the form dN = (N 0/τ) dτ, where dN is the density of traps with time constants between τ and τ + dτ and N0 is a normalization constant.
Abstract: Measurements have been made of the hysteresis in the drain current (or equivalent gate voltage) of a number of commercial MOS transistors. The hysteresis was obtained after applying a negative voltage on the gate electrode. The hysteresis is attributed to trapping of charge carriers on oxide near the silicon oxide interface. A gate voltage hysteresis of the order of 0.01 to 0.2 V has been obtained depending on the transistor and kind of measurement. The traps studied follow a time constant dispersion of the form dN = (N0/τ) dτ, where dN is the density of traps with time constants between τ and τ + dτ and N0 is a normalization constant. It is shown that this time-constant dispersion is compatible with a simple tunneling model for the charge trapping and also with the low-frequency noise spectrum obtained from MOS transistors.

Journal ArticleDOI
TL;DR: In this article, the maximum frequency of oscillation for GaAs-Ge heterojunction transistors utilizing either doped or high-resistivity space-charge-limited emitters was calculated.
Abstract: Assuming a state-of-the-art microwave planar geometry, the maximum frequency of oscillation has been calculated for GaAs-Ge heterojunction transistors utilizing either doped or high-resistivity space-charge-limited emitters. This is compared with a Ge homojunction transistor of the same geometry. A detailed equivalent circuit is used which accounts for the parasitics of the chip. It is shown that if chip parasitics are neglected, GaA-Ge devices should outperform Ge devices by about 4 to 1 in power gain. In the geometry assumed, however both heterojunction and homojunction transistors are limited by wafer parasitics, particularly base contact resistance. The calculated figures of merit of the two types of devices are therefore quite similar.

Journal ArticleDOI
TL;DR: In this article, various devices have been fabricated using silicon films grown epitaxially on low aluminum-rich spinel substrates, including MOS capacitors, MOS transistors, and vertical junction diodes.
Abstract: Various devices have been fabricated using silicon films grown epitaxially on low aluminum-rich spinel substrates. The insulating substrate provides complete isolation of the semiconductor devices and eliminates the parasitic capacitances of the back-biased p−n junctions. The low aluminum-rich spinel offers the advantages of better thermal stability and easier surface preparation for silicon epitaxy over both the conventional high aluminum-rich (MgO:3Al2O3) and the stoichiometric (MgO:Al2O3) materials. MOS capacitors, MOS transistors, and vertical junction diodes were constructed and studied using films with mobilities equal to or near the bulk values. Information on MOS capacitance vs. bias behavior, transistor characteristics, diode junction properties, and minority carrier lifetime was obtained. The silicon-spinel composites were also characterized by physical methods, and the nature of the defect structures was examined.

Patent
13 Feb 1970
TL;DR: Orientation-dependent etching is employed in the fabrication of a monolithic semiconductor circuit network to provide electrical isolation and increased packing density, while minimizing collector series resistance and output capacitance.
Abstract: Orientation-dependent etching is employed in the fabrication of a monolithic semiconductor circuit network to provide electrical isolation and increased packing density, while minimizing collector series resistance and output capacitance. Collector contact to a transistor component is made by the direct metallization of a buried low-resistivity substrate region exposed by the preferential etching operation.

Patent
Graf S A1
04 Nov 1970
TL;DR: In this article, a temperature compensated reference voltage source is provided which is suitable for fabrication using integrated circuit techniques and a constant current source is coupled via first and second current paths to a reference terminal.
Abstract: A temperature compensated reference voltage source is provided which is suitable for fabrication using integrated circuit techniques A constant current source is coupled via first and second current paths to a reference terminal Each of the first and second current paths includes one or more diodes A current repeater circuit, which includes a further diode and a transistor having proportionally related conduction characteristics, is coupled between the two current paths and the reference terminal to provide substantially constant currents in each of the first and second paths The currents are selected so that a difference voltage, produced across the emitter-collector electrodes of the transistor of the repeater circuit, is substantially constant as a function of temperature

Patent
James Peter Till1
16 Mar 1970
TL;DR: In this article, a combined overload and overvoltage protective circuit for solid state devices was proposed, which utilizes two transistors in a NOR logic gate configuration that is held normally off by a common emitter bias supplied through a feedback current developed from voltage supplied to a load.
Abstract: A combined overload and overvoltage protective circuit for solid state devices which utilizes two transistors in a NOR logic gate configuration that is held normally off by a common emitter bias supplied through a feedback current developed from voltage supplied to a load. Either transistor is switched on to shunt supply current away from solid state devices of the circuit during an overload or input overvoltage condition. In case of overload, excessive load current causes the development of an increased drop across the base-emitter circuit of one transistor countering the hold off bias developed from the feedback current. An input overvoltage causes a Zener diode to conduct and to develop an increased drop across base-emitter of other transistor countering the same hold off bias developed from the feedback current.

Patent
22 Sep 1970
TL;DR: In this article, a semiconductor device includes a common substrate, on the one side of which there are provided an insulated gate field effect transistor and bipolar transistor for protecting the former transistor from the failure.
Abstract: A semiconductor device includes a common substrate, on the one side of which there are provided an insulated gate field effect transistor and bipolar transistor for protecting the former transistor from the failure. The gate of the former is electrically connected to the emitter of the latter to have the same potential.

Patent
Thomas M Frederiksen1
16 Nov 1970
TL;DR: In this article, an improved constant current source, which may provide very small current without requiring the construction of a large resistor, is described. But this source requires a bias source comprising a second transistor that is biased to low current conduction, the bias resistor for the biased transistor being advantageously small.
Abstract: An improved constant current source, which may provide very small current without requiring the construction of a large resistor, is disclosed. This constant current source includes a transistor having a bias source comprising a second transistor that is biased to low current conduction, the biasing resistor for the biased transistor being advantageously small.

Patent
05 Nov 1970
TL;DR: In this paper, a relay-operated switch is connected between the battery and the load devices, such as headlights, and a reset switch is provided to reconnect the remaining battery voltage across the relay winding.
Abstract: A control circuit is connected into the electrical system of a vehicle such as an automobile having a starting motor, a battery, and various current-consuming load devices, such as headlights. A relay-operated switch is connected between the battery and the load devices. A potentiometer is connected across the battery, and the relay winding and a transistor are connected across the potentiometer with the potentiometer slider connected to the base of the transistor and the collector connected to the relay winding. The resistance values are chosen such that when the battery is substantially charged, the voltage across the baseemitter junction of the transistor is sufficient to keep the transistor conducting, thus causing the relay to be energized and the switch to be closed, connecting the load devices to the battery. Should the battery be run down, as through leaving the headlights on, the battery voltage will drop, and at some desired proportion of full charge the voltage across the base-emitter junction will become too low to keep the transistor conducting, and the relay will drop out, opening the switch and disconnecting the load devices. A reset switch is provided to reconnect the remaining battery voltage across the relay winding.

Patent
06 Apr 1970
TL;DR: In this paper, a non-dispressive power loss suppression circuit for a transistor controlled DC power converter of the type having a pair of positive and negative input terminals for connection to a source of DC voltage, a power converter inductor having primary and secondary windings, one end of the primary windings being connected to the positive input terminal, a transistor having a base connected to a transistor drive circuit for control of the transistor with turn-on and turnoff pulses, a collector conducted to the other end of a power converter primary winding, and an emitter connected to
Abstract: A nondissipative power loss suppression circuit for a transistor controlled DC power converter of the type having a pair of positive and negative input terminals for connection to a source of DC voltage, a power converter inductor having primary and secondary windings, one end of the primary windings being connected to the positive input terminal, a transistor having a base connected to a transistor drive circuit for control of the transistor with turn-on and turnoff pulses, a collector conducted to the other end of the power converter inductor primary winding, and an emitter connected to the negative input terminal, and an output diode in series arrangement for providing a DC voltage output across the arrangement. The power loss suppression circuit consists of an energy absorbing circuit connected to the terminals and the power converter inductor for absorbing input voltage power during a turn-on pulse while said output diode recovers and for transferring excess absorbed power to the source when the diode recovers. Also provided is an energy storage circuit connected to the positive terminal and collector for storing power in the power converter inductor and the energy absorbing circuit during a turnoff pulse. An energy transfer circuit connected to the negative terminal and the energy storage circuit provides for the transfer of energy stored by the energy storage circuit to the source during a succeeding turn-on pulse.

Patent
22 Apr 1970
TL;DR: In this paper, the sum of threshold voltages of two transistors of different conductivity type is employed as a reference level in voltage sensing and other circuits, where a first transistor connected as a diode and its current source are connected in series between a pair of terminals to which a voltage to be sensed is applied.
Abstract: The sum of the threshold voltages of two transistors of different conductivity type is employed as a reference level in voltage sensing and other circuits A first transistor connected as a diode and its current source are connected in series between a pair of terminals to which a voltage to be sensed is applied A second transistor of different conductivity type than the first transistor is connected at its control electrode to the connection of the diode to its current source The conduction path of the second transistor in series with its load is connected at at least one end to one of the pair of terminals

Patent
01 Oct 1970
TL;DR: In this paper, the authors present a control system for an electromagnet having a movable core, wherein a power winding is provided for moving the core to active position and a holding winding requiring less power maintains the core in active position.
Abstract: Control system for an electromagnet having a movable core, wherein a power winding is provided for moving the core to active position and a holding winding requiring less power maintains the core in active position. A transistor controls the power supply circuit and, when made conductive, energizes a transistor in series with each winding, thus energizing both windings. After a time delay provided by a resistor-condenser circuit, another transistor is energized which causes the transistor in the power winding to become non-conductive, thus de-energizing the power winding. De-energizing the control transistor causes the transistor in the maintenance winding to become non-conductive so that the maintenance winding is de-energized and its energy is dissipated through a Zener diode and a resistor, both in series therewith.