Showing papers on "Transistor published in 1975"

Class E-A new class of high-efficiency tuned single-ended switching power amplifiers

Abstract: The new class of amplifiers described is based on a load network synthesized to have a transient response which maximizes power efficiency even if the active device switching times are substantial fractions of the a.c. cycle. The new class of amplifiers, named `Class E,' is defined and is illustrated by a detailed description and a set of design equations for one simple member of the class. For that circuit the authors measured 96 percent transistor efficiency at 3.9 MHz at 26-W output from a pair of Motorola 2N3735 TO-5 transistors. Advantages of Class E are unusually high efficiency, a priori designability, large reduction in second-breakdown stress, low sensitivity to active-device characteristics, and potential for high-efficiency operation at higher frequencies than previously published Class-D circuits.

Signal and Noise Properties of Gallium Arsenide Microwave Field-Effect-Transistors

Abstract: Publisher Summary This chapter examines the signal and noise properties of gallium arsenide (GaAs) microwave field-effect transistors (FET) High frequency gallium arsenide field-effect transistors (GaAs FETs) have demonstrated remarkably low noise figures and high power gains at microwave frequencies A practical microwave GaAs FET is usually fabricated by deposition or diffusion of source, gate, and drain contacts on the surface of an appropriately doped thin epitaxial n-type layer This layer, in turn, is grown on a semi-insulating wafer by either a vapor or liquid epitaxial technique The apparent minor role played by the negative resistance region in practical short-gate FETs suggests that radiofrequency instabilities due to this region, if they exist, occur at frequencies far above the normal frequency regime of microwave FETs The small-signal equivalent circuit of the FET, valid up to moderately high frequencies is elaborated It is found that noise in a microwave GaAs FET is produced both by sources intrinsic to the device and by thermal sources associated with the parasitic resistances

A hydrogen-sensitive Pd-gate MOS transistor

Abstract: An n‐channel MOS transistor with palladium gate was fabricated. The threshold voltage of this transistor was found to depend on the partial pressure of hydrogen in the ambient atmosphere. At a device temperature of 150 °C, 10 ppm hydrogen in air is easily detected, and in nitrogen or argon the sensitivity is considerably larger. A model, based on hydrogen adsorption on the palladium–silicon dioxide interface, is proposed. This model explains the device behavior and is also able to predict the absolute sensitivity for hydrogen in argon.

Field-effect transistor versus analog transistor (static induction transistor)

Abstract: The reason why the usual FET shows the saturated characteristics has been shown that with increasing drain voltage, the effect of the negative feedback action, increases through a marked increase of the Series channel resistance in the neighborhood of the pinch-off voltage, under which condition the apparent transfercon-ductance G_{m'}= G_{m}/(1 + r_{s}.G_{m}) becomes G_{m'} \simeq r_{s}^{-1} . It is also pointed out that a transistor in analogy to the vacuum type proposed by Watanabe and Nishizawa in 1950, exhibits the nonsaturated build-up character only When the internal negative feedback action is as little as G_{m'} \simeq G_{m} . In this case, when the channel has not yet pinched off, the characteristics are ohmic and then the transistor can operate as a good variable resistor; on the other hand, when the channel has already pinched, the transistor shows the build-up characteristics similar to those of a vacuum tube triode as a result of the static induction from the drain. The transistor similar to that of the vacuum tube triode type is named "Static Induction Transistor," because its output character is based on the static induction as well as input characteristics. The SIT has the exponential characteristics in contrast with the "Analog Transistor" which is expected by Shockley to follow the space-charge conduction law. The SIT has already been ascertained to have low noise, low distortion, and high-power capability, and its fabrication has been already realized in the form of a high-power transistor (2 kW, 8 MHz), a high-frequency transistor (a few watts, UHF), and a high-speed thyristor. Microwave transistors and very high-speed integrated circuits are being constructed, as well as variable resistors.

Potassium ion-sensitive field effect transistor

Abstract: The construction and theory of operation of a potassiumsensitive field effect transistor Is described, and Its performance is characterized both as a solid-state field-effect device and as an electrochemical sensor. The performance of this device is comparable with the correspondlng PVC-type ion selective electrodes. The transistor operates satisfactorliy in the presence of proteins and it has been used for determination of potassium ion concentration in blood serum. A new type of electrochemical sensor, an ion-sensitive field-effect transistor (ISFET), was introduced when Bergveld removed the metal gate from a metal oxide semiconductor field-effect transistor (MOSFET) and exposed the silicon oxide gate insulator to a measured solution (I). A similar approach was followed later by Matsuo and Wise (Z), and this new subject area has been recently reviewed by Zemel (3). In the broader sense of chemically sensitive field-effect transistors, one sensitive to molecular hydrogen has also been reported (4). The ISFET is a result of the integration of two technologies: ion-selective electrodes and solid state microelectronics. This development opens several new possibilities, such as miniaturization, development of multiprobes, all solidstate design and in situ signal processing. Because of its small size, it presents a difficult encapsulation and packaging problem which is, however, amply offset by the elimination of electrical pick-up noise by in situ impedance conversion and on site signal amplification. Bergveld did not modify the ion-sensitive layer in any way although he considered introducing impurities in order to render the device ion selective. In this paper, we introduce a class of devices having a chemically-sensitive layer placed over the gate region, and we report our results with valinomycin/plasticizer/poly(vinylchloride) membrane

Device physics of integrated injection logic

Abstract: After a brief review of relevant device parameters, characterizing the inversely operating multicollector n-p-n transistor and the lateral p-n-p transistor which make up an I^{2}L basic cell, some electronic circuit properties of this gate are discussed quantitively. Analytic expressions are derived for the transfer characteristics, the noise margin and the propagation delay time per gate in relation to the cell geometry, fan-out, doping profiles, and recombination properties. These expressions are compared with experimental and numerical circuit simulation results.

A 6 × 6-in 20-lpi electroluminescent display panel

Abstract: Over the last two years, we have been working on a solution of the solid-state display addressing problem which consists of building the addressing circuits (and eventually, also scanning or decoding circuits) directly on the panel, and fully integrated with the particular display medium. The technique utilized for this approach is that of a vacuum-deposited thin-film transistor matrix. In this paper, we report on the design, construction, and performance of a 12 000 element EL panel, suitable for alphanumeric, vectorgraphic, and monochrome TV image presentation. The basic circuit, repeated at every picture element, consists of an X-Y-addressed logic transistor, a power transistor, and a storage capacitor. The entire circuit was fabricated through multiple evaporations in a multisource system using one pumpdown cycle. The finished thin-film circuit is covered with a sprayed EL-phosphor. An evaporated Au/PbO layer forms the continuous top electrode. The entire display panel is finally sealed with a glass cover plate. Reproducible fabrication of good-quality displays was achieved, with >99 percent of the elements operational. Excellent alphanumeric displays with very few defects were demonstrated. Contrast ratios >50:1 (ON:OFF under dark ambient) were obtained. Power consumption under typical alphanumeric display conditions was below 1 W, with a peak brightness of 40 fL.

Process for fabricating non-volatile field effect semiconductor memory structure utilizing implanted ions to induce trapping states

Abstract: Disclosed is a non-volatile field effect information storage device which can be electrically written and erased. It consists of an insulated gate field effect transistor having a single gate dielectric material formed in two stages. The gate dielectric is made up of two adjacent layers of silicon dioxide, one of which is relatively thin and adjacent to the semiconductor substrate, while the other is relatively thick and implanted with ions at controlled depths and dosages near the interface with the first silicon dioxide layer. With the application of an appropriate control voltage on the gate structure, charges from the adjacent transistor channel region tunnel through the relatively thin layer of silicon dioxide and become stored in the trapping sites introduced by the implanted ions located in the second layer of silicon dioxide and very near the interface between the two silicon dioxide layers. While there, the charges control the conductivity of the channel, and thus the logic state of the transistor.

Deep-channel MOS transistor

Abstract: A new type of ion-implanted MOS transistor is described. The transistor functions, for example, as an integrating nondestructively readable photosensor and its technology is fully compatible with the advanced MOS integrated circuits.

Theory of the carrier‐density fluctuations in an IGFET near threshold

Abstract: A three‐dimensional perturbation‐theory treatment of the carrier‐density fluctuations in the insulated‐gate field‐effect transistor (IGFET) above threshold and their effect upon the source‐drain current is presented. The fluctuations are considered to be generated by interface charge nonuniformities. It is shown that such fluctuations reduce the source‐drain current over that for a uniform device with the same average carrier density. It is found that the fluctuations increase with decreasing carrier density, that they are larger in a shallow channel than in a deep channel, and that the increase in fluctuations with decreasing carrier density is quite abrupt. The critical carrier density below which carrier‐density fluctuations are important is found to be ?1011 carriers/cm2 at 300 °K and ?1012 carriers/cm2 at 0 °K for ordinary‐device charge densities. The difference in the threshold for the onset of fluctuations at the two temperatures is attributable to the smaller amplitude of fluctuations at high temp...

Bipolar transistor modeling of avalanche generation for computer circuit simulation

Abstract: An avalanche generation model is developed and incorporated into computer circuit analysis programs SLIC and NICAP. A modified form of Miller's empirical expression for generation is found to agree well with measured data for Western Electric and commercial n-p-n transistors. Measurement techniques and parameter determination for the three model coefficients are discussed. Equation constraints appropriate for computer implementation are presented.

Method for making transistors

Abstract: Submicron plasma trimming of a patterened resist material is combined with ion implantation techniques to achieve submicron control of lateral doping profiles. This makes possible the high-yield fabrication of, for example, bipolar microwave transitors of the self-aligned-emitter type. The basic technique can also be supplied to the fabrication of high performance insulted-gate field-effect transistors, junction-gate field-effect transistors and Schottky-barrier field-effect transistors.

Subnanosecond-pulse generator with variable pulsewidth using avalanche transistors

Abstract: The letter describes a pulse generator with epitaxial silicon planar transistors working in the avalanche-breakdown mode. The risetime is 150 ps and the fall time 200 ps. The pulse-width can be varied continuously between 0.3 and 120 ns, without changing the maximum amplitude of about 15 V. Simple rules for the exact design of the circuitry are given.

An experimental and theoretical analysis of double-diffused MOS transistors

Abstract: An experimental and theoretical study of double-diffused MOS transistors (DMOST's) has been made. A simple, analytic two-transistor model gives insight into DMOS device physics as well as predicting DMOST characteristics. Both the model and experimental results show that three distinct regions of operation exist: short-channel control, long-channel control, and carrier velocity saturation control. Quantitative criteria are established for judging the region of operation as a function of device parameters and terminal voltages. A DMOST may be optimized to have the same d.c. characteristics as its short-channel component transistor over most of its operating range. A two-transistor model suitable for Computer-Aided Circuit Design (CAD) is also presented.

Mounting assemblies for a plurality of transistor integrated circuit chips

Abstract: A mounting assembly for a power transistor integrated circuit chip having a pair of electrodes on one surface thereof comprising base and emitter connections and a third electrode on the opposite surface thereof comprising the collector connection, is fabricated by the method including the steps of providing an electrically conductive strip having a central cavity extending the length thereof, the depth of the cavity being substantially equal to the height of the chip and the strip also including arms extending outwardly at opposite sides of the cavity; tinning the strip with solder; placing transistor chips in the cavity adjacent each other with the collector electrodes thereof being in contacting engagement with the strip; heating the strip with the chips therein to reflow the solder for connecting the chips thereto at the collector electrode; and severing the strip transverse the length thereof between chips to provide individual power transistor chip mounting assemblies each having a pair of outwardly extending support feet formed from the severed arms of the strip. The mounting assembly can be mounted to printed circuit conductors which are in-line by soldering the support feet to predetermined ones of the conductors and the base and emitter electrodes to others of the conductors.

CMOS Schmitt trigger

Abstract: The input of the Schmitt trigger is applied in parallel to the gates of a plurality of stacked MOS transistors. The stacked transistors are connected with their respective source and drain electrodes in series with a source of potential and with the drain electrode of a p channel transistor being connected to the adjacent drain electrode of an n channel transistor to define an output node on which the output hysteresis signal is derived. Upper and lower trip point reference potentials are established on the respective source electrodes of said output node defining p and n channel transistors. At least one of the trip point reference potentials is gated to the respective source electrode as a function of the state of the output, i.e., whether the output is high or low. The input signal is compared in the stack with the established trip point reference potentials to derive the upper and lower trip points dependent upon the sign of the change in the potential of the input signal to produce hysteresis in the transfer function of the device. The output hysteresis signal is inverted and a portion of the inverted output signal is fed back via a second inverter to the output node for stabilizing the output signal.

Method and structure for controllng carrier lifetime in semiconductor devices

Abstract: The device structure is a bi-polar transistor having a region of inert atoms located in the collector adjacent to the base-collector junction. Another embodiment of the invention is a complementary insulated gate field effect transistor (IGFET) structure having N and P channel IGFETs with regions of implanted ions beneath the source and drain of one or both transistors, and/or annular regions projecting inwardly from the surface that surround or separate the different types of IGFETs.

Method for manufacturing a semiconductor field effort transistor

Abstract: A method of manufacturing a metal, insulator, semiconductor type field effect transistor (MISFET) is disclosed by which a device is obtained having greatly improved reliability and containing multi-layered wiring. Only three photo-mask processes are used and the requirement for precision mask aligning is eliminated.

Clock generator and delay stage

Abstract: A clock generator for an MOSFET integrated circuit having a plurality of cascaded delay stages is disclosed. Each delay stage includes a bootstrap inverter having first and second transistors connected in series between the drain supply voltage and a source supply voltage, thus forming a first node between the transistors. The first node is capacitively coupled to a bootstrap node which is connected to the gate of the first transistor. The bootstrap node is also coupled through the channel of a third transistor to an input. The gate of the third transistor forms a third node. Circuit means are provided for precharging the third node and then isolating the third node while an input signal is applied through the third transistor to the bootstrap node so that the third node is also bootstrapped up to permit rapid charging of the bootstrap node to the full voltage of the input signal. The second transistor is held on by a precharge signal so that the first node is held low until the bootstrap node has been charged to the input voltage. Then both the third node and the gate of the second transistor are discharged to turn the second and third transistors off, thus permitting the bootstrap node to go rapidly above the drain supply voltage. The bootstrap node may be used directly as output, or can drive the gate of an output transistor so as to produce a very rapidly rising output which quickly reaches the full drain supply voltage. Circuit means is also provided to discharge the third node to disable the output before an input signal occurs. Since the third node is automatically discharged after receiving an input, the input may subsequently be changed without changing the output. Circuit means is also provided to selectively discharge the bootstrap node to isolate the output after it has achieved maximum voltage, so that the output can be capacitively boosted above the drain supply voltage. A circuit is also provided to reset the output to zero volts in conjunction with isolation of the output. A clock generator employing the various functions of a plurality of cascaded delay stages is also disclosed to demonstrate the capabilities of producing a series of clock pulses which go to V DD in timed sequence in response to input signal, of producing a voltage substantially above V DD , and of producing a pulse of predetermined duration.

Two-dimensional computer simulation for switching a bipolar transistor out of saturation

Abstract: A two-dimensional numerical analysis for the turnoff of a bipolar transistor from high injection level (V BE = 900 mV) is carried out. V BC is being kept constant at 1 V. Distributions of potential, electron, and hole density are interpreted and lead to a subdivision of the total transient time into four time regions, each governed by a single phenomenon. These phenomena are 1) fast discharge of the sidewall transistor, 2) the "lateral wave" which has the dominating influence in the total switching time, 3) the vertical discharge, and 4) the emitter discharge. The transient behavior is essentially ruled by two-dimensional lateral effects. Hence one-dimensional models are not adequate for switching a transistor out of saturation.

Modelling weak avalanche multiplication currents in IGFETS and SOS transistors for CAD

Abstract: A model is developed for the substrate current of an IGET operating in saturation. This current results from the impact ionization of the channel current carriers in the high field region adjacent to the drain. Due to the exponential dependency of the impact ionization process on the electric field, an accurate description of the field near the drain is essential. An expression for the field, accounting for the two-dimensional nature of the drain space charge region, is used. The result is a closed form expression for the substrate current. By using an appropriate p-n junction model for the source diffusion, the floating substrate potential in SOS devices is evaluated.

Electronic ballast for gaseous discharge lamps

Abstract: An electronic circuit for starting and operating gaseous discharge lamps. A DC input is connected to a time-ratio control (TRC) circuit which includes a regulating transistor, a sensing resistor and a coasting inductor connected in series. A flyback diode is connected to the inductor for providing a discharge path for the inductor. The TRC circuit serves to ballast the gaseous discharge lamp. An inverter is connected to the TRC circuit for driving the lamp with square waves. A starting circuit is provided and is connected to one of the lamp electrodes for starting the lamp. A transient protection circuit is provided for the inverter to shunt transients back to the input. A TRC drive and control circuit is connected to the TRC regulating transistor and sensing resistor for controlling the regulating transistor. Power for the circuits which control the regulating transistor, the inverter and the starting circuit is provided by a feedback power supply which is connected in a circuit relationship with the lamp so that it supplies power substantially only while there is operating voltage for the lamp.

Transistor protection circuit

Abstract: The disclosed protection circuit which is suitable for providing protection of transistors included in integrated circuits such as regulators and power amplifiers, includes thermal shutdown, safe area and current control circuits. The current control portion includes a sense transistor connected substantially in parallel with the transistor to be protected. In monolithic integrated circuit applications, the sense transistor has an emitter area that is a predetermined ratio of the emitter area of the protected transistor. A "sense resistor" is connected to the sense transistor and develops a control signal which is proportional to the instantaneous current being conducted by the protected transistor. A threshold circuit is coupled between the sense resistor and the drive circuit for the protected transistor and responds to the magnitude of the control signal crossing a predetermined threshold to remove or reduce the drive to the protected transistor.

Semiconductor floating gate storage device with lateral electrode system

Abstract: A semiconductor storage device having a field-effect transistor with a floating insulating gate electrode on which information-containing charge can be stored by tunneling charge carriers between the semiconductor body and the gate electrode. According to the invention the recording and erasing voltage is applied between two juxtaposed surface zones of the same conductivity type present outside the channel region and the source and drain zones, one of the surface zones, which is preferably also the source or drain zone, being separated from the floating gate electrode by an insulating layer having a thickness of less than 0.01 micron through which charge carriers can tunnel. Recording and erasing can be carried out at low voltages and with a voltage source of the same polarity relative to a reference potential.

Microwave Interference Effect in Bipolar Transistors

Abstract: This work discusses the active circuit behavior of typical bipolar transistors as they are injected with low level microwave energy. The observed response is found to be due to square law rectification of the energy at the transistor's emitter-base junction. A rectification efficiency measurement'is described which gives a quantitative measure of a transistors sensitivity to microwave interference in terms of an equivalent rectified base current interference signal per unit of absorbed microwave power. Measurements show that a typical n-p-n Si planar transistor (FT = 450 MHz) has a rectification factor of approximately 0.05 mA/mW for 2 GHz microwave energy. Typically, this factor decreases at about 6 dB/octave as the interference carrier frequency is increased. A model for the rectification effect is propQsed which suggests that it is due to ac crowding and the decrease in transistor a at the edges of the emitter, in addition to the basic nonlinearity of the emitter-base junction volt-ampere characteristic.

Dual injector, floating gate MOS electrically alterable, non-volatile semiconductor memory device

Abstract: A dual injector, floating-gate MOS non-volatile semiconductor memory device (DIFMOS) has been fabricated, using process specifications and design rules of the same general character previously developed for single-level metal gate CMOS devices. An electron injector junction (p+/n) is avalanched to "write" a charge on the floating gate, and a hole injector junction (n+/p-) is avalanched to "erase" the charge. An MOS sensing transistor, whose gate is an extension of the floating gate, "reads" the presence or absence of charge on the floating gate. In a preferred embodiment, the hole injection means includes an MOS "bootstrap" capacitor for coupling a voltage bias to the floating gate.

Optimum gain-bandwidth limitations of transistor amplifiers as reactively constrained active two-port networks

Abstract: The design of broad-band high-frequency transistor amplifiers is a difficult and challenging outstanding problem in active network theory of great practical importance. New and explicit optimum gain-bandwidth limitations of high-frequency transistor amplifiers for arbitrary prescribed transistor gain rolloff characteristics are presented. The transistor is modeled as a reactively constrained active two-port network. The limitations derived and presented are applicable to the design of broad-band small-signal as well as high-power transistor amplifiers. Realization of a class of practical broad-band matching networks are also presented. The explicit gain-bandwidth limitations and the new realization results presented form the basis for a new broadbanding theory for high-frequency transistor amplifiers and represent a significant advancement in the design theory of active networks.

Peripheral circuits for one-transistor cell MOS RAM's

Abstract: The use of a single transistor and storage capacitor allows MOS dynamic memories to be built with cell areas of less than two square mils. The logic signals then available are unusually small and balanced sensing is commonly used. Such sense amplifiers and other on-chip circuits peripheral to the memory array are increasingly important in determining the total area and cost, the performance and testing difficulties. This paper describes some of the key peripheral circuits used in a practical 4K random-access memory (RAM) design paying particular attention to these factors. A `margin test' facility is designed into the form of sense amplifier used and allows measurement of cell storage levels and sense amplifier offset to ensure that adequate signal margins exist in the memory.

Integrated, programmable logic arrangement

Abstract: An integrated, programmable logic arrangement includes an AND matrix and an OR matrix which have individual gates. In the AND matrix each input is connected to a control line and via an inverter to another control line for production of a complementary input signal. A selector line and a base line are provided for each gate both in the AND matrix and in the OR matrix and the selector line is connectible to the supply potential. In the AND matrix, in programmed fashion, a switching transistor is provided at the intersection points between a control line and a selector line, or is not so provided, and a switching transistor so arranged at an intersection is connected by its gate terminal to an associated control line, Also, the switching transistor is connected, on the one hand, to an associated selector line of a gate and, on the other hand, to a base line which is connectible to another potential. The difference between the supply potential and the other potential corresponds to the supply voltage. In the OR matrix, in a correspondingly programmed fashion, a switching transistor is provided at an intersection point of a control line and a selector line or is not so provided. A switching transistor so provided is connected by its gate terminal to the associated control line and is connectible, on the one hand, to the selector line of a gate which may be connected to the supply potential and, on the other hand, to a base line which is connectible to ground. In the AND matrix a selector line of a gate is, in each case, connected by way of a pulsed load transistor to the supply potential and the base line of the gate is connectible by way of a pulsed cut-off transistor to the further potential. In the OR matrix, in corresponding fashion, a selector line of a gate is, in each case, connectible via a pulsed load transistor to the supply potential and the base line of the gate is connectible via a pulse cut-off transistor to the further potential. A pulsed flip-flop is arranged, in each case, between an output of the AND matrix and an input of the OR matrix and a pulsed flip-flop is provided, in each case, at an output of an OR matrix.

High frequency power source for fluorescent lamps and the like

Abstract: A power source for operating gas discharge lamps and other loads at high frequency, typically utilizing a 115 volt ac source rectified to provide a 150 volt dc input and providing a 20,000 hertz output. An inverter with a transistor current control for protection against transistor damage under open circuit, starting and no-load conditions, with low power consumption under no-load and with dimming capability. An inverter with a detector circuit connected across the feedback winding or an additional control winding for developing a control signal varying as a function of the feedback winding output, and a zener diode or other device for connecting the control signal to the base of the transistor in current controlling relation when the control signal exceeds a predetermined value.