Showing papers on "Transistor published in 1981"

Programmable cell for use in programmable electronic arrays

Abstract: An improved programmable cell for use in programmable electronic arrays such as PROM devices, logic arrays, gate arrays and die interconnect arrays. The cells have a highly non-conductive state settable and non-resettable into a highly conductive state. The cells have a resistance of 10,000 ohms or more in the non-conductive state which are settable into the conductive state by a threshold voltage of 10 volts or less, a current of 25 milliamps or less, for 100 microseconds or less. The cells in the conductive state have a resistance of 100 ohms or less. The cells have a maximum permittable processing temperature of 400° centigrade or more and a storage temperature of 175° centigrade or more. The cells are formed from doped silicon alloys including at least hydrogen and/or fluorine and contain from about 0.1 to 5 percent dopant. The cells can be plasma deposited from silane or silicon tetrafluoride and hydrogen with 20 to 150,000 ppm of dopant. Each cell in an array is a thin film deposited cell and includes an isolating device which can be a bipolar or MOS device or can be a thin film diode or transistor. The associated addressing circuitry also can be conventional bipolar or MOS devices or thin film deposited devices. The cells have a cell area of less than one square mil to provide a high cell packing density.

Application of amorphous silicon field effect transistors in addressable liquid crystal display panels

Abstract: It is shown that thin-film field effect transistors (FETs) made from amorphous (a-) silicon deposited by the glow-discharge technique have considerable potential as switching elements in addressable liquid crystal display panels. The fabrication of the elements and their characteristics with steady and pulsed applied potentials are discussed in some detail. Two important points are stressed: (i) a-Si device arrays can be produced by well-established photolithographic techniques, and (ii) satisfactory operation at applied voltages below 15VV is possible. Small experimental 7×5 transistor panels have been investigated and it is shown that with the present design up to 250-way multiplexing could be achieved. The reproducibility of FET characteristics is good and in tests so far no change has been observed after more than 109 switching operations.

Full-charge indicator for battery chargers

Abstract: A full-charge indicator for battery chargers, includes a transistor which is in a conductive state as long as charging current to the battery is not less than a level which indicates that the battery did not reach full charge. When the battery reaches full charge, a voltage drop in a resistor in the charging current path is not sufficient to maintain the transistor in a conducting state, and therefore it is switched off. When this occurs an LED is turned on, to indicate a full charge state of the battery. A photocoupler together with a photocoupler transistor are included. When the transistor is off, the photocoupler activates the photocoupler transistor to shunt out a resistor, thereby reducing the charging current to the battery to a float charging current and prevent the battery from being overcharged and damaged.

Self-aligned bipolar transistors for high-performance and low-power-delay VLSI

Abstract: An n-p-n bipolar transistor structure with the emitter region self-aligned to the polysilicon base contact is described. The self-alignment results in an emitter-to-base contact separation less than 0.4 µm and a collector-to-emitter area ratio about 3:1 for a two-sided base contact. This ratio can be less than 2:1 for a base contacted only on one side. The vertical doping profile can be optimized independently for high-performance and/or high-density and low-power-delay circuit applications. The technology, using recessed oxide isolation, was evaluated using 13-stage nonthreshold logic (NTL) and 11-stage merged-transition logic (MTL) ring-oscillator circuits designed with 2.5 µm design rules. For transistors with 200-nm emitter junction depth the common-emitter current gain for polysilicon emitter contact is typically 2-4 times that for Pd 2 Si emitter contact. There is no observable circuit performance degradation attributable to the polysilicon emitter contact. Typical observed per-stage delays were 190 ps at 1.3 mW and 120 ps at 2.3 mW for the NTL ( FI = FO = 1 ) circuits and 1.3 ns at 0.15 mA for the MTL ( FO = 4 ) circuits.

Active matrix assembly for a liquid crystal display device including an insulated-gate-transistor

Abstract: An active matrix assembly for a liquid crystal display device utilizing an MIS (metal-insulator-semiconductor) transistor array is provided. The active matrix assembly includes a transparent substrate, a first thin layer of silicon disposed thereon, an insulating film on the first silicon layer and a second thin layer of silicon disposed on the insulating film. The layers are selectively etched for forming a gate and the silicon layers are doped for forming a MOS transistor for a display element of the device. The two silicon layers and insulating material intersect to form capacitors with the upper electrode of the storage capacitor being the driving electrode for the liquid crystal. An active matrix assembly constructed and arranged in accordance with the invention permits 90 percent or more of incident light coming from above to pass therethrough. Use of such a transparent substrate in an active matrix liquid crystal display device permits utilization of a transparent liquid crystal drive, such as the field effect type liquid crystal for providing a maximum degree of contrast. Operation of the device with peripheral drive circuits for the gate lines and data lines including non-inverting rationless shift registers formed in the same manner as the active matrix permits a substantial reduction in power consumption due to reduced parasitic capacitance.

High Electron Mobility Transistor Logic

Abstract: A high electron mobility transistor (HEMT) logic is described. Ring oscillators with enhancement-mode switching and depletion-mode load HEMTs with a 1.7 µm-gate length have been fabricated to assess logic performance capability. Switching delays down to 56.5 ps at room temperature and down to 17.1 ps at liquid nitrogen temperature have been obtained. The switching delay of 17.1 ps is the lowest of all the semiconductor logic technologies reported thus far.

Semiconductor integrated circuit device with memory MISFETS and thin and thick gate insulator MISFETS

Abstract: A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.

Integrated circuit protection device

Abstract: Disclosed is a protection circuit which may be used, for example, in a television receiver to protect circuitry formed within an integrated circuit from damage due to excessively high voltage transients. The protection circuit comprises a PNPN structure forming a silicon controlled rectifier (SCR) and metal-oxide-semiconductor (MOS) transistor integral to the SCR structure. The SCR and the MOS transistors are arranged to form a two terminal protection circuit which is rendered conductive when the potential difference across the two terminals is greater than a predetermined threshold. One terminal of the protection circuit is connected to an input or output signal terminal of the protected circuit, and the other terminal is connected to a reference terminal to which a reference potential such as ground potential is applied. Transient voltages appearing at the integrated circuit terminal greater than the predetermined threshold voltage causes the protection circuit to conduct current, thereby dissipating the energy of the high voltage transient and protecting the integrated circuit from damage. In one embodiment, the gate electrode of the MOS transistor is connected to the reference terminal, and in another to the signal terminal. The latter connection provides a much larger predetermined threshold than the former, and typically considerably in excess of the supply voltage.

Ttl to cmos input buffer

Abstract: A TTL to CMOS input buffer accomplishes buffering a TTL signal to a CMOS signal without static current flow when the TTL is a logic "1" by isolating the input from an input P channel transistor and using feedback from an input N channel transistor to turn off the P channel transistor. A second P channel transistor is used to couple a positive power supply voltage to the input P channel transistor in response to an output from the N channel transistor.

Overcurrent and overtemperature protective circuit for power transistor system

Abstract: A power transistor switch is protected against thermal destruction that might be caused by accidental short circuiting of the load being switched by a protective circuit having a base-drive-removing transistor in shunt to the base-emitter junction of the power transistor; an RC circuit including a capacitor in series with a resistor connected across the power transistor with the capacitor coupled across the base-emitter junction of the base-drive-removing transistor; a forward-biased shunting transistor connected across the capacitor; a shunt-removing transistor connected across the base-emitter junction of the shunting transistor; and a turn-on transistor triggerable to the conductive state by a turn-on signal for applying base drive to the power transistor and for forward biasing the shunt removing transistor to thereby turn off the shunting transistor and permit the capacitor to charge. Excessive current flow through the power switch causing it to desaturate results in charging the capacitor and consequent turning on the base-drive-removing transistor to thereby remove base current from the power transistor and turn it off.

Inverter for interfacing advanced energy sources to a utility grid

Abstract: A transistor is operated in the PWM mode such that a hlaf sine wave of current is delivered first to one-half of a distribution transformer and then the other as determined by steering thyristors operated at the fundamental sinusoidal frequency Power to the transistor is supplied by a dc source such as a solar array and the power is converted such that a sinusoidal current is injected into a utility at near unity power factor

Methods and apparatus for microdielectrometry

Abstract: An impedance measuring apparatus having a measuring transistor with its gate electrode adapted to form a two electrode, interdigitated capacitor with the material to be measured forming the dielectric, a second reference transistor connected in differential configuration to the measuring transistor so that their drain currents are constrained to be equal, a time-varying voltage generator connected to one electrode of the interdigitated capacitor and a gain-phase meter connected to the gate of the reference transistor.

Solid state image pickup

Abstract: A Detection Matrix having elementary modules disposed in lines and in columns. Each module has a photoconductance, a thin-film MOS transistor and a storage capacitor. The gate of the transistor is connected to a line electrode. The source of the transistor is connected to a video amplifier, and the drain of the transistor is connected to one terminal of the photocapacitance and of the capacitor. The other terminal of the photoconductance of the capacitor are both connected to the line electrode following or preceding the line electrode connected to the gate of the transistor.

Battery charging circuit

Abstract: A battery charging circuit having an electromagnetic transformer with primary and secondary coils, a rectifier connected between the secondary coil and the battery, a first transistor connected in series with the primary coil and a resistor to form a circuit in parallel with a power source, the base of the first transistor being connected to the secondary coil, and a second transistor electrically connected to the base of the first transistor The first transistor has a high switching frequency, and the battery is charged with a constant reverse current during its blocking phase, regardless of the power source voltage The first transistor is protected from reverse kick-back voltage pulses induced during its blocking phase by the provision of a diode and Zener diode connected in series across the primary coil and a capacitor interposed between the secondary coil and the base of the first transistor

High voltage MOS transistor

Abstract: A metal oxide semiconductor device is featured by the provision of a covering element for covering a channel region of the semiconductor device there being interposed therebetween an insulating layer. The covering element is connected to at least one electrode selected from the drain electrode, the source electrode and the gate electrode. Therefore, the electrical level of the covering element is fixed.

Electronic ballast for gaseous discharge lamps

Abstract: An electronic ballast for energizing one or more gaseous-discharge lamps and for regulating the power consumed thereby, the ballast including a power supply for providing a source of DC power between a pair of outputs, a pair of transistors connected as switches in series between the power-supply outputs, the transistors for selectively coupling to the juncture thereof positive and negative potentials, a voltage-conditioning and current-limiting network for energizing the lamp from the potential developed between the transistor juncture and a power-supply common, and a pulse generator for developing pulses for driving each of the transistors in turn whereby a potential is developed at the transistor juncture which alternates as positive-going and negative-going pulses each separated by a dead time, the pulse generator for monitoring the power consumption level of the lamp and responsive thereto operative to vary the frequency and/or the width of the transistor driving pulses whereby the lamp consumption is regulated. Also included is a third harmonic trap for coupling the power supply to the AC power line to improve the power factor.

Measurement of GaAs field‐effect transistor electronic impulse response by picosecond optical electronics

Abstract: Direct time‐resolved measurements of the linear and nonlinear electronic impulse response of a high‐speed gallium arsenide metal semiconductor field‐effect transistor have been made by using picosecond optical pulses to drive high‐speed photoconducting electronic pulse generators and sampling gates. High resolution, jitter‐free measurements with excellent signal‐to‐noise showed the field‐effect transistor to have a fast full width at half‐maximum response of approximately 25 ps, and a slower fall time of 75 ps.

Semiconductor integrated circuit with a response time compensated with respect to temperature

Abstract: A current-controlling MOS transistor is connected between a power source and an MOS circuit. A control voltage which has a level related to temperature is applied to the gate electrode of the control MOS transistor in order to compensate for current reduction at high temperatures due to the lowering of the mobility of minority carriers. The response time of the MOS circuit is made less dependent on temperature as a result of the current compensation.

Effects of drift region parameters on the static properties of power LDMOST

Abstract: The effects of the drift region geometry and the physical parameters on the thin layer (resurfed) lateral DMOS transistor operation have been studied for both the static on-state and the off-state. The variations of breakdown voltage with drift region parameters were investigated using numerical modeling and compared to the experimental results. The operation of the LDMOST in the on-channel condition was modeled semi-empirically. The analytical and experimental results show that the operation of the device depends strongly on the geometry and the physical parameters of the drift region, particularly at high gate voltages and low drain voltages. Design guidelines for the lateral DMOS transistor for switching applications are discussed.

Self-refreshing memory cell

Abstract: A self-refreshing non-volatile memory cell having two cross-coupled transistors includes a first floating gate formed between the gate and the channel of said first transistor, said first floating gate overlying by means of a tunnel oxide a portion of the drain of said second transistor and a second floating gate formed between the gate and channel of said second transistor, a portion of said second floating gate overlying by tunnel oxide a portion of the drain of the first transistor. Disturbances in the supply voltage and the gate voltage of the device normally enhance rather than degrade the state of data stored in the cell, thereby providing an extremely long storage time for the cell. The cell is capable of operating simultaneously in a volatile and a non-volatile state.

Semiconductor memory circuit

Abstract: A semiconductor memory circuit (10) has a plurality of word lines (12, 14), column lines (16, 18) and bit lines (20, 22). A memory cell transistor (30) has the gate terminal connected to the word line (12) and the drain and source terminals connected between the bit line (20) and the column line (16). A reference transistor (106) is connected to the word line (12) to provide a reference signal for input to a sense amplifier (136). A data line (54) is connected to the bit line (20) to provide the data state from the data storage transistor (30) to the sense amplifier (136). The data bit line (20) and reference bit line (104) are clamped at different pull down voltages. The memory circuit (10) includes a reference circuit that has reference transistor (106) which operates statically to provide a reference signal for the sense amplifier (136). When the word lines are being sequentially accessed the reference signal produced by the reference circuit rises to a higher average voltage and enhances the operating speed of the memory.

Active load pulse generating circuit

Abstract: The conduction paths of a first, normally on, transistor and a second, normally off, transistor are connected in parallel between an output line and a circuit point at a first value, of potential. When any one of a plurality of normally non-conducting input signal responsive means coupled to the output line, is enabled, it causes the potential on the output line to be driven to a second value of potential. Means are provided responsive to the potential on the output line for applying a turn-off signal to the first transistor followed by a delayed turn-on signal to the second transistor when the potential on the output line is driven towards the second value of potential and for applying a turn-on signal to the first transistor followed by a delayed turn-off signal to the second transistor when the potential on the output line is being restored to the first value of potential.

Semiconductor integrated circuit device with low power consumption in a standby mode using an on-chip substrate bias generator

Abstract: A mode switching transistor which is controlled by a chip enable signal is connected between a power supply terminal and a MOS inverter including transistors. The transistor functions as a weak depletion or depletion type MOS transistor to provide sufficient current with a first back gate bias given in an active mode and functions as a perfect enhancement type transistor to completely cut off current with a second back gate bias given in a standby mode.

Charge pumping in SOS—MOS transistors

Abstract: The variation of the floating-substrate potential of SOS-MOS transistors is studied by applying frequent pulses to the gate. The minority carriers are injected into the floating substrate by charge pumping and they recombine there. The injected charges are stored because of the reverse-biased junctions at the source and drain. The threshold-voltage change by the substrate bias is also investigated. If the silicon film is fully depleted under the gate, the threshold-voltage change does not occur. This condition is used to stabilize the high-speed operations of the SOS-MOS integrated circuits. A new memory cell consisting of only one transistor without a storage capacitor is realized utilizing the change of the floating-substrate potential by the charge pumping and the avalanche multiplication. The sensitivity of the memory cell is affected by the channel length of an SOS-MOS transistor. The memory storage time is obtained as 300 µs.

Semiconductor memory circuit with depletion data transfer transistor

Abstract: A read only memory (ROM) circuit (10) includes a memory storage transistor (16) which is fabricated to have one of a plurality of threshold voltages corresponding to predetermined data states. The source and drain terminals of the memory transistor (16) are connected between a column node (18) and a bit line (20). A lightly depleted data transfer transistor (30) is connected between the bit line (20) and a data line (14). The column node (18), bit line (20) and data line (14) are precharged. A memory address is decoded to drive a selected word line (12) and a selected column decode line (32) to a high voltage state. A transistor (34) discharges the column node (18). Depending upon the state of the memory storage transistor (16) the bit line (20) is discharged or maintained precharged. The state of bit line (20) is transmitted through the data transfer transistor (30) to the data line (14). The data transfer transistor ( 30) can be fabricated as a relatively small device due to the large turn on voltage applied thereto because the transistor (30) is a depletion device. The smaller size of a plurality of the transistors (30) results in a substantial saving in space and reduces capacitive loading on the data line (14) thereby speeding up the discharge rate of the data line (14).

Inrush current limiter

Abstract: An inrush current limiter includes at least a two-terminal circuit in series with a power load having a high gain high current Darlington transistor, a driver transistor for the high gain high current Darlington transistor, a current sensing resistor, a base-drive resistor, and a diode bridge interfaced for providing a peak-current-limiting function by proportional adjustment of the voltage to the power load as a function of current.

Electric switch operation monitoring circuitry

Abstract: The Figure shows switching circuitry comprising switches 16, 18, 26, 28 which are operated in timed relationship to supply DC current in opposite directions in alternate cycles to an inductive load 10. In operation the switch 16 is opened momentarily before switch 18 in alternate cycles and the switch 26 is opened momentarily before switch 28 in the intervening cycles. The correct operation of the switches is monitored by the remaining circuitry. When switch 16 opens correctly, the potential of node 20 falls to one diode drop below earth and this is the normal potential of test input terminal 70. When 70 is pulsed, diode 56 is reverse biased and the potential of node 51 remains low. Transistor 60 remains non-conducting. Conversely if switch 16 has not completely opened, diode 52 is reversed biased and when 70 is pulsed, potential of node 51 rises and transistor 60 conducts. This is signalled by the potential change of output line 66. Operation of switch 26 is checked in the same way.