Showing papers on "Transistor published in 1983"

Numerical analysis of heterostructure semiconductor devices

Abstract: A numerical method for analyzing heterostructure semiconductor devices is described. The macroscopic semiconductor equations for materials with position-dependent dielectric constant, bandgap, and densities-of-states are first cast into a form identical to that commonly used to model heavily doped semiconductors. Fermi-Dirac statistics are also included within this simple, Boltzmann-like formulation. Because of the similarity in formulation to that employed for heavily doped semiconductors, well-developed numerical techniques can be directly applied to heterostructure simulation. A simple one-dimensional, finite difference solution is presented. The accuracy of the numerical method is assessed by comparing numerical results with special-case, analytical solutions. Finally, we apply numerical simulation to two heterostructure devices: the heterostructure bipolar transistor (HBT) and the modulation doped field-effect transistor. The influence of a conduction band spike on the current-voltage characteristics of the HBT emitter-base junction is studied, and the variation with gate bias of the two-dimensional electron gas in a field-effect device is also investigated.

Monolithic semiconductor switching device

Abstract: An electrical circuit device made in integrated monolithic form has low level operating characteristics of a MOS device and high level operating characteristics of a Triac. The structure includes two double diffused MOS transistors which have merged drain regions. At higher voltage and current levels a lateral Triac structure is triggered by the MOS devices. Alternatively, separate terminal contacts can be made to the P and N regions comprising the MOS transistor source and channel regions with the Triac triggered conventionally by an externally applied control voltage.

Combinational logic structure using pass transistors

Abstract: PASS transistors are used to reduce the layout complexity of logic circuits by using PASS transistors connected to pass a first and second input function to an output node in response to selected CONTROL signals, thereby to generate a selected output function on the output node. The PASS transistor comprises a transistor capable of passing an input function in response to a CONTROL signal applied to the transistor thereby to generate an output function related to the input function. In general, the input function comprises less than all of a set of input variables and the CONTROL function comprises one or more of the remainder of the set of input variables.

Simulation tools for digital lsi design

Abstract: This thesis proposes a timing simulator (RSIM) based on a uniquely simple transistor model. RSIM allows a designer to determine both the functional and approximate timing characteristics of a MOS network with more accuracy than gate-level simulation, and using larger circuits than are accommodated by circuit analysis programs. In RSIM, transistors are modeled as resistors; the logic states of a transistor''s terminal nodes determine its effective resistance. Using this model, a MOS network is simulated as a network of resistors where each node''s value is determined by the resistance of its connections to various inputs. Transition times are determined from the RC time constant calculated for the node by examining the surrounding network; (R from the transistors, C from the interconnect and gate capacitance). The network''s behavior as inputs are given values is calculated by an efficient event-driven algorithm. Two changes to the underlying model are also investigated: (1) further simplifying the transistor model of an on/off switch (which can be thought of as a degenerate resistor). Several approaches to switch-level simulation are developed, one particularly well-suited for implementation using parallel hardware; (2) modeling the behavior of a network of switches by a system of logic equations. Various compilation strategies are evaluated for producing code that implements the system of equations.

Avalanche fuse element as programmable memory

Abstract: A programmable device is provided by a thin-oxide avalanche fuse element (40) which is programmed at a voltage below the oxide (44) breakdown level. This device may be used to fix the addresses of faulty rows or columns in a memory having redundant or substitute cells, or as a programmable memory of the PROM type. Upon break- down, the thin oxide (44) is perforated by small holes which fill with silicon to create short circuit. In one embodiment, the source or emitter (41) of the transistor device may be separated from the drain (42) and gate (43) by thick field oxide (20).

Multi-bit-per-cell read only memory circuit

Abstract: A data memory circuit is provided including a plurality of depletion type MOS transistors connected in series, each of which stores data including two bits in the form of a threshold voltage. One end of the memory circuit is kept at a power source level and the second terminal thereof is kept at a ground potential level. 0 V is applied to the gate electrode of one selected MOS transistor while the power source voltage is applied to the gate electrodes of the remaining MOS transistors. As a result, a voltage equal to an absolute value of the threshold voltage of the selected MOS transistor is produced at the second terminal. A converter converts the voltage produced at the second terminal into corresponding binary coded data.

Compact DC model of GaAs FETs for large-signal computer calculation

Abstract: A modified, simple and fairly accurate explicit expression of DC current-voltage characteristics of GaAs FETs is presented. A departure from the square-law behavior in saturation of the short channel transistor is included by introducing drain-source voltage bias dependent pinch-off potential. The model proposed here needs four parameters extracted by the global curve-fitting technique of a measured family of drain current-voltage characteristics. A comparison with other DC compact models of MESFETs valid over the entire range of drain-source voltages shows good compromise between simplicity and accuracy of the model proposed. The model can be easily implemented in programs of computer-aided analysis and design of circuits with GaAs FETs.

Effects of the collector current fall time on the class E tuned power amplifier

Abstract: Presents the equations governing the operation of the amplifier when the collector current fall time during the on-to-off transition of the transistor is an appreciable fraction of the signal period. A current-source model of the transistor with a linearly decreasing collector current during the fall time is used. The following basic amplifier parameters are determined: the waveforms of the collector current, the collector-to-emitter voltage, the instantaneous power dissipated in the transistor, the optimum values of the load-network components, the output power, the power-output capability, and the collector efficiency. The decrease of the collector efficiency is e.g. 10 percent at 60/spl deg/ fall time. Experimental results are also given. The author shows the behavior of the class E amplifier at higher operating frequencies and provides more accurate circuit design procedure.

Method of making high density VMOS electrically-programmable ROM

Abstract: A method of making an electrically-programmable memory array in which the memory elements are capacitor devices formed in anisotropically etched V-grooves, providing enhanced dielectric breakdown at the apex of the groove. After breakdown, a memory element exhibits a low resistance to a grounded substrate. The method includes forming access transistors in series with the memory elements, and polycrystalline silicon, deposited to form control gates of the access transistors, also forms address lines. Oxide is formed in the V-groove thinner than the gate oxide thickness formed for the access transistor, providing a lower programming voltage. These factors provide a very small, high speed device.

High-Frequency Doubler Operation of GaAs Field-Effect Transistors

Abstract: A comprehensive study of single-gate GaAs FET frequency doublers is presented. Special emphasis is placed on exploring high-frequency limitations, while yielding explanations for previously observed lower frequency phenomena as well. Extensive Iarge-signal simulations demonstrate the underlying relationships between circuit performance characteristics and principal design parameter. Verifying experiments include straight frequency doubler and a self-oscillating doubler, both with output signal frequencies in Ku-band. The self-oscillating doubler appears especially attractive, yielding an overall dc-to-RF efficiency of 10 percent. The type of transistor employed in the numerical and experimental examples possesses a gate length of 0.5 µm and a gate width of 250 µm.

Fully isolated lateral bipolar—MOS transistors fabricated in zone-melting-recrystallized Si films on SiO 2

Abstract: A four-terminal device that can be operated either as a lateral n-p-n bipolar transistor or as a conventional n-channel MOSFET has been fabricated in silicon-on-insulator films prepared by graphite-strip-heater zone-melting recrystallization. Common-emitter current gain close to 20 and emitter-base breakdown voltage in excess of 10 V have been obtained for bipolar operation. As a MOSFET, the device exhibits well-behaved enhancement-mode characteristics with a field-effect mobility of ∼ 600 cm2/V.s and drain breakdown voltage exceeding 15 V.

Three-dimensional CMOS IC's Fabricated by using beam recrystallization

Abstract: A three-dimensional (3-D) CMOS integrated circuit with a structure, in which one type of transistor is fabricated directly above a transistor of the opposite type with separate gates and an insulator in between, has successfully been fabricated by using laser beam recrystallization. Seven-stage ring oscillators fabricated in the 3-D structure have a propagation delay of 8.2 ns. In the present experiment, a double-layer of silicon-nitride and phospho-silicate-glass (PSG) film has been used as an intermediate insulating layer between the top and the bottom devices. This CMOS structure and the process technology we have developed here can be the basis for realizing a multilayered 3-D device composed of vertically stacked transistors with separate gates and an insulating layer in between.

Transistors : fundamentals for the integrated-circuit engineer

Abstract: A practical, comprehensive introduction to transistor devices in electronics as they are currently used in integrated circuits. Includes high-level conditions as encountered in BJT operations. Unique to the book is a user's guide to the subject matter and a cross-referenced index. Includes tables at the end of each chapter summarizing important equations for quick references.

Method for manufacturing semiconductor Bi-CMOS device

Abstract: A method for forming a Bi-CMOS structure, wherein a vertical npn transistor and CMOS transistors are formed on a single semiconductor substrate, is disclosed. After forming a p-type epitaxial silicon layer on a p-type silicon substrate with a plurality of n+ -type buried layers therein, n-type wells are formed to extend to the n+ -type buried layers. Selective oxidation is performed to form field oxide films so as to define an n-type element region for the npn transistor, an n-type element region for the p-channel MOS transistor, and a p-type element region for the n-channel MOS transistor. An oxide film as a gate oxide film for the CMOS is formed on the surfaces of all the element regions. After forming a p-type active base region of the npn transistor by ion-implantation of boron, an emitter electrode comprising an arsenic-doped polysilicon layer is formed in contact with the p-type active base region. Gate electrodes of the CMOS are formed and have a low resistance due to doping with phosphorus and/or arsenic. Using the emitter electrode as a diffusion source, an n-type emitter region is formed. Boron is then ion-implanted to simultaneously form a p+ -type external base region and p+ -type source and drain regions of the p-channel MOS transistor. Phosphorus is ion-implanted to form an n+ -type collector contact region and n+ -type source and drain regions of the n-channel MOS transistor.

Semiconductor memory device having stacked capacitor- type memory cells

Abstract: In a semiconductor memory device having stacked capacitor-type memory cells, the capacitor of each memory cell comprises an electrode, an insulating layer, and a counter electrode. The electrode is connected electrically to a source or drain region of a transfer transistor and extends over a part of a word line adjacent to another word line serving a gate electrode of the transfer transistor, at which part no memory cell is formed.

Gate circuit of combined field-effect and bipolar transistors

Abstract: A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

Test system for VLSI digital circuit and method of testing

Abstract: The conductive state of a transistor in a semiconductor integrated circuit is determined by irradiating the transistor with a radiation beam and measuring changes in load current, thereby indicating whether the transistor was conducting or non-conducting prior to irradiation. A correlated double sampling method is employed in measuring changes in load current. A load resistor in series with the device under test is capacitively coupled to a differential amplification means including a plurality of differential amplifiers with buffers connected between successive amplifiers. A system clock is stopped at a predetermined time period prior to irradiating the transistor. A bypass switch shunts the load resistor until the clock is stopped.

Thin-film transistor circuit

Abstract: A thin-film transistor circuit used to drive a liquid crystal display (LCD) device is disclosed, which circuit includes a plurality of circuit components (C ij ) which are as arranged in the form of a matrix as to be connected with data lines (Y j , Y j+1 ) for supplying an image signal and with address lines (X i , X i+1 ) for supplying a gate pulse signal, whereby the circuit components control the picture element display in the unit picture element region of the LCD device. Each circuit component has a capacitor (26) connected to the unit picture element region (22) for temporarily storing the image signal, and a TFT transfer gate (20) having a gate electrode connected to one (X i ) of the address lines, a source electrode connected to one (Y j ) of the data lines, and a drain electrode connected to the capacitor (26). The transfer gate (20) performs the switching operation in response to the gate pulse signal, thereby transferring the image signal to the capacitor (26). A compensating pulse signal which is synchronized with the gate pulse signal and has a polarity opposite to that of the gate pulse signal is applied to the capacitor (26), thereby preventing a decrease in the image signal voltage across this capacitor (26) due to the parasitic capacitance component existing in the thin-film transistor (20).

Process for manufacturing MOS integrated circuit with improved method of forming refractory metal silicide areas

Abstract: A CMOS integrated circuit made up of complementary insulated gate field effect transistors incorporates isolation trenches formed by a combination of thermal growth of silicon dioxide and chemical vapor deposition of polycrystalline silicon to prevent air gaps. Matching of the thermal coefficient of expansion of the trench with that of the substrate minimizes pn junction leakage currents as well as positive feedback latch-up operation. To reduce the ohmic contact resistance and interconnect resistance of the transistor elements, refractory metal silicide areas of low sheet resistance are contacted with the source, drain and gate elements. The process of manufacture also employs vertical walls of silicon nitride to prevent the formation of "birds' beak" portions of increased thickness in the silicon dioxide layer of each transistor, which could degrade the high frequency performance of the device.

Tunable active filter

Abstract: A tunable high-pass or low-pass filter employs a balanced amplifier (Fig. 3, 30) having electronically controlled resistance elements (39, 40) in either two input (31, 32) or two feedback (35, 36) paths (or both). A reactive element (41, 42) is placed in each of the other pair of paths. Especially low distortion results from this arrangement, allowing convenient integrated circuit implementation with a nonlinear device (e.g., MOS transistor) as a voltage-controllable element. Multiple stages can be cascaded and controlled from a reference clock (Fig. 1) or other precision source for high accuracy (Fig. 3).

Process for forming complementary integrated circuit devices

Abstract: A process for forming chanstops in complementary transistor integrated circuit devices which involves only a single extra masking step yet permits close control of the doping in the chanstops. The process is advantageously used starting with a twin-tub structure for forming CMOS integrated circuit devices.

A thin film MOS transistor and an active matrix liquid crystal display device

Abstract: A thin film MOS transistor includes a silicon layer (202) whose thickness, at least in the channel region is less than 2500 ANGSTROM . The silicon layer may be a polycrystalline silicon layer and its thickness in the channel region may be less than its thickness in the source and drain regions. Such thin film MOS transistors may be used in active matrix liquid crystal display devices having a plurality of picture elements arranged in a matrix, each picture element having a thin film MOS transistor as a switching element.

Semiconductor integrated circuit device and a method for manufacturing the same

Abstract: An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

Simple NMOS voltage reference circuit

Abstract: A simple, compact voltage reference circuit for an NMOS integrated circuit comprises a series connected depletion transistor with its gate at ground and an enhancement transistor with its gate connected to an output node between the two transistors.

Liquid crystal display panel

Abstract: PURPOSE:To enable the illumination of a liq. crystal display panel having a switching transistor array from the rear side and to enhance the display performance, by laminating insulating films in the vicinity of the transistor of the panel. CONSTITUTION:A liq. crystal display panel is composed of a panel substrate 1, a transistor 2, light shielding films 3, 4 made of metal or metallic silicide, insulating films 5, 6 formed by the plasma deposition of gaseous hydrocarbon and having a higher refractive index, insulating films 7-10 of silicon oxide having a lower refractive index, and a transparent electrode 11. Light incident on the substrate 1 at a large angle is captured in the films 5, 6 by total reflection, and it does not reach the transistor 2. Accordingly, the panel can be illuminated from the rear side, and the display performance is enhanced.

Thin film transistors

Abstract: The thin film transistor comprises a plurality of individual thin film transistors on a common insulating substrate with the plurality of individual thin film transistors being connected together in series. The gate electrode of each individual transistor of the plurality of thin film transistors is connected to form one common gate electrode for the overall transistor. Leakage current in the OFF condition is substantially reduced. Identical performance is achieved from the transistor with interchangeability in designating source and drain terminals, when a symmetry is provided such that the i-th transistor in a series of N is physically identical to the (N-i+1)-th transistor in the overall transistor.

Field-effect transistor sensitive to dipolar molecules

Abstract: A field-effect transistor with metal gate suspended above the gate insulator has been fabricated. Fluid samples can freely penetrate into the gap formed between the metal and the insulator. If the molecules carry an electrical dipole, they will alter the surface potential on these two materials giving rise to a change in the drain current of the transistor. Our preliminary results confirm this mechanism for dipolar molecules such as methanol and methylene chloride.

A CMOS magnetic field sensor

Abstract: The authors present a novel, fully integrated magnetic field sensor made in the standard, polysilicon-gate CMOS technology. The circuit shows a sensitivity of 1.2 V/T with 10 V supply voltage and 100 /spl mu/A current consumption. The circuit consists of a pair of split-drain MOS transistors in a CMOS-differential amplifier-like configuration.

Fast-switching insulated gate transistors

Abstract: Insulated gate transistors (IGT's) with high-speed gate turn-off capability have been developed by using electron irradiation to reduce the minority-carrier lifetime in the drift region. Gate turnoff times as low as 200 ns have been achieved. These devices have been found to offer a unique advantage in the ability to tradeoff conduction and switching losses which allows optimization of device characteristics for each application.