Showing papers on "Transistor published in 1984"

A reliable approach to charge-pumping measurements in MOS transistors

Abstract: A new and accurate approach to charge-pumping measurements for the determination of the Si-SiO 2 interface state density directly on MOS transistors is presented. By a careful analysis of the different processes of emission of electrons towards the conduction band and of holes towards the valence band, depending on the charge state of the interface, all the previously ill-understood phenomena can be explained and the deviations from the simple charge-pumping theory can be accounted for. The presence of a geometric component in some transistor configurations is illustrated and the influence of trapping time constants is discussed. Furthermore, based on this insight, a new technique is developed for the determination of the energy distribution of interface states in small-area transistors, without requiring the knowledge of the surface potential dependence on gate voltage.

Chemical derivatization of an array of three gold microelectrodes with polypyrrole: Fabrication of a molecule-based transistor

Abstract: : This document reports the fabrication of a chemically derivatized microelectrode array that can function as a transistor when immersed in an electrolyte solution. The key finding is that a small signal (charge) needed to turn on the device can be amplified. The device to be described MIMICS the fundamental characteristics of solid state transistor, since the resistance between to contacts can be varied by a signal to be amplified. The chemical transistor is the set of three (drain, gate, and source) Au microelectroces covered by polypyrrole.

Chemical derivatization of an array of three gold microelectrodes with polypyrrole: Fabrication of a molecule-based transistor

Abstract: : This document reports the fabrication of a chemically derivatized microelectrode array that can function as a transistor when immersed in an electrolyte solution. The key finding is that a small signal (charge) needed to turn on the device can be amplified. The device to be described MIMICS the fundamental characteristics of solid state transistor, since the resistance between to contacts can be varied by a signal to be amplified. The chemical transistor is the set of three (drain, gate, and source) Au microelectroces covered by polypyrrole.

Correlating the Radiation Response of MOS Capacitors and Transistors

Abstract: A new technique is presented for separating the threshold-voltage shift of an MOS transistor into shifts due to interface states and trapped-oxide charge. Using this technique, the radiation responses of MOS capacitors and transistors fabricated on the same wafer are compared. A good correlation is observed between p-substrate capacitors and n-channel transistors irradiated at 10 V, as well as between n-substrate capacitors and p-channel transistors irradiated at 0 V. These correlations were verified for samples having large variations in the amount of radiation-induced trapped holes and interface states. An excellent correlation is also observed between n-channel capacitors and n-substrate transistors irradiated under positive bias. The use of capacitors separately fabricated on control wafers for potential use in process development or monitoring is clearly demonstrated.

A Switch-Level Model and Simulator for MOS Digital Systems

Abstract: The switch-level model describes the logical behavior of digital systems implemented in metal oxide semiconductor (MOS) technology. In this model a network consists of a set of nodes connected by transistor "switches" with each node having a state 0, 1, or X (for invalid or uninitialized), and each transistor having a state "open," "closed," or "indeterminate." Many characteristics of MOS circuits can be modeled accurately, including: ratioed, complementary, and precharged logic; dynamic and static storage; (bidirectional) pass transistors; buses; charge sharing; and sneak paths. In this paper we present a formal development of the switch-level model starting from a description of circuit behavior in terms of switch graphs. Then we describe an algorithm for a logic simulator based on the switch-level model which computes the new state of the network by solving a set of equations in a simple, discrete algebra. This algorithm has been implemented in the simulator MOSSIM II and operates at speeds approaching those of conventional logic gate simulators. By developing a formal theory of MOS logic circuits, we have achieved a greater degree of generality and accuracy than is found in other logic simulators for MOS.

A ratio-independent algorithmic analog-to-digital conversion technique

Abstract: An algorithmic analog-to-digital conversion technique is described which is capable of achieving high-resolution conversion without the use of matched capacitors in an MOS technology. The exact integral multiplication of the signal required by the conversion is realized through an algorithmic circuit method which involves charge summing with an MOS integrator and exchange of capacitors. A first-order cancellation of the charge injection effect from MOS transistor switches is attained with a combination of differential circuit implementation and an optimum timing scheme. An experimental prototype has been fabricated with a standard 5-/spl mu/m n-well CMOS process. It achieves 12-bit resolution at a sampling rate of 8 kHz. The analog chip area measures 2400 mils/SUP 2/.

Master slice IC device

Abstract: A master slice IC device comprising at least two kind of basic cells; that is, a first kind of basic cells each having one or more n-type MIS transistors and one or more p-type MIS transistors to form a CMIS logic circuit, and a second kind of basic cells each comprising an npn-type bipolar transistor and a pnp-type bipolar transistor to form a bipolar buffer circuit having a large drive ability. The second kind of basic cells are used, for example, only when the fan-out number is large and/or the length of the connection lines is long, thereby realizing a high degree of freedom in circuit design and a high operating speed without increasing the power consumption.

Modulation-doped GaAs/AlGaAs heterojunction field-effect transistors (MODFET's), ultrahigh-speed device for supercomputers

Abstract: In the past few years, a new transistor has appeared on the scene, made of GaAs and AlGaAs, which now holds the record as the fastest logic switching device, switching at speeds of close to ten trillionths of a second (10 ps). The device evolved from the work on GaAs-AlGaAs superlattices (thin alternating layers of differing materials sharing the same crystalline lattice) pioneered by L. Esaki and R. Tsu at IBM in the late 1960's. They realized that high mobilities in GaAs could be achieved if electrons were transferred from the doped and wider band-gap AlGaAs to an adjacent undoped GaAs layer, a process now called modulation doping. R. Dingle, H. L. Stormer, A. C. Gossard, and W. Wiegmann of AT&T Bell Labs, working independently, were the first to demonstrate high mobilities obtained by modulation doping in 1978, in a GaAs-AlGaAs superlattice. Realizing that such a structure could form the basis for a high-performance field-effect transistor (Bell Labs Patent 4163237, filed on April 24, 1978), researchers at various labs in the United States (Bell Labs, University of illinois, and Rockwell), Japan (Fujitsu), and France (Thomson CSF) began working on this device. In 1980, the first such device with a reasonable microwave performance was fabricated by the University of Illinois and Rockwell, which they called a modulation-doped FET or MODFET. The same year Fujitsu reported the results obtained in a device with a 400-µm gate which they called the "high electron mobility transistor" or HEMT, in the open literature. Thomson CSF published shortly thereafter calling their realization a "two-dimensional electron gas FET" or TEGFET, and Bell Labs followed, using the name "selectively doped heterojunction transistor" or SDHT. These names are all descriptive of various aspects of the device operation as we will discuss in the text. For the sake of internal consistency will call it MODFET, hereafter. In this paper we review the principals of MODFET operation, factors affecting its performance, optimization of the device, and comparison with other high-performance compound and elemental semiconductor devices. Finally, the remaining problems and future challenges are pointed out.

Diffused planar InP bipolar transistor with a cadmium oxide film emitter

Abstract: A novel bipolar InP transistor is demonstrated which comprises a Zn-diffused base and a transparent conductor widegap emitter made of sputtered cadmium oxide. Preliminary current gain was about 10. Owing to its less demanding planar technology the device is assessed to be promising for monolithic integration.

Ultrasonic liquid atomizer with an improved soft start circuit

Abstract: In an ultrasonic liquid atomizer, an oscillator has a transistor and a resonant circuit a part of which is formed by a piezoelectric vibrator mounted in an energy transfer relationship with liquid in a chamber. The transistor and the resonant circuit receive a full-wave rectified supply voltage to generate ultrasonic energy in the vibrator in the presence of a bias voltage. A soft start circuit has a time constant circuit responsive to the bias voltage and a transistor responsive to an output of the time constant circuit which provides switching action in phase with the full-wave rectified supply voltage so that ultrasonic energy is generated in the form of a series of bursts having durations gradually increasing as a function of time during an initial brief interval from application of the bias voltage to the oscillator. A bias stabilizer has a second time constant circuit responsive to the bias voltage and a transistor connected to the output of the second time constant circuit to establish a low impedance path across the base and emitter of the transistor of soft start circuit after termination of the initial brief interval.

A new flash E 2 PROM cell using triple polysilicon technology

Abstract: A new Flash Electrically Erasable-PROM cell with single transistor per bit as same as conventional UV-EPROM(1) (2) and suitable for 256K bit F-E2PROM with rather conservative 2.0µm design rule is described. The cell is programmed by a channel hot carrier injection mechanism similar to EPROM. The contents of all memory cells are simultaneously erased by using field emission of electrons from a floating gate to an erase gate in a flash. The F-E2PROM cell with single transistor per bit consists of three layers of polysilicon with select transistor. (3) (4) (5) Programming is 10msec per bit as same as UV-EPROM. Good erasing characteristics is obtained with 550A of oxide thickness between floating gate and erase gate.

Thin film field effect transistor

Abstract: There is disclosed a film field effect transistor which can be operated at fast switching rates for use, for example, in video display applications. The transistor includes a body of silicon semiconductor material having a structure more ordered than amorphous material and less ordered than single crystalline material. The source and drain of the transistor comprise rectifying contacts formed on the body of silicon semiconductor material. Also disclosed are a method of making the transistor and an electronically addressable array system utilizing the transistor to advantage.

Transistor effect in monolithic Si/CoSi2/Si epitaxial structures

Abstract: Epitaxial Si 〈111〉/CoSi2/Si structures have been grown by molecular beam epitaxy. The transistor effect, via ballistic electron transport in the CoSi2 200 A-thick base, has been observed. The ballistic mean free path in CoSi2 obtained (λB 105 A) from the current gain is consistent within 20% with the predicted value (λBth 80 A).

A GaAs gate heterojunction FET

Abstract: A new semiconductor-insulator-semiconductor field-effect transistor has been fabricated. The device consists of a heavily doped n-type GaAs gate with undoped (Al,Ga)As as the gate insulator, on an undoped GaAs layer. This structure gives the device a natural threshold voltage near zero, well suited for low-voltage logic. The threshold voltage is, to first order, independent of Al mole fraction and thickness of the (Al,Ga)As layer. The layers were grown by MBE and devices fabricated using a self-aligned technique involving ion-implantation and rapid thermal annealing. A transconductance of 240 mS/mm and a field-effect mobility of about 100 000 cm2/V-s were achieved at 77 K.

Charge injection transistor based on real-space hot-electron transfer

Abstract: We describe a new transistor based on hot-electron transfer between two conducting layers separated by a potential barrier. The mechanism of its operation consists of controlling charge injection over the barrier by modulating the electron temperature in one of the layers. This physical principle is different from those employed in all previous three-terminal amplifying devices-which are based either on the modulation of a potential barrier (vacuum triode, bipolar transistor, various analog transistors) or on the modulation of charge in a resistive channel (field effect transistors). In contrast to this, the present device can be compared to a hypothetical vacuum diode whose cathode has an effective electron temperature which is controlled without inertia by an input electrode ("cathode heater"). The device has been implemented in an AlGaAs/GaAs heterojunction structure. One of the conducting layers is realized as an FET channel, the other as a heavily doped GaAs substrate. The layers are separated by an Al x Ga 1 - x As graded barrier. Application of a source-to-drain field leads to a heating of channel electrons and charge injection into the substrate. The substrate thus serves as an anode and the FET channel represents a hot-electron cathode, whose effective temperature is controlled by the source-to-drain field. Operation of the charge injection transistor is studied at 300, 77, and 4.2 K. At 77 K the existence of power gain is demonstrated experimentally with the measured value of the mutual conductance g m reaching 280 mS/mm (at 300 K, g m ≈ 88 mS/mm). The fundamental limit on the device speed of operation is analyzed and shown to be determined by the time of flight of electrons across a high-field region of spatial extent ∼ 10-5cm. Practical ways of approaching this limit are discussed. The process of hot-electron injection from the channel is studied experimentally at 77 and 4.2 K with the purpose of measuring the electron temperature in the channel at different bias conditions. For not too high substrate bias the electron temperature in the channel is found to be proportional to the square of the heating voltage.

GaAs/(Ga,Al)As heterojunction bipolar transistors with buried oxygen-implanted isolation layers

Abstract: A simple self-aligned technique using oxygen implants to reduce the extrinsic base-collector capacitance in GaAs/(Ga,Al)As heterojunction bipolar transistors (HBT's) is described. This technique has been used to achieve nonthreshold logic ring-oscillators with propagation delays down to 30 ps per gate, the lowest reported to date for any bipolar transistor circuit.

Thin-film transistor

Abstract: In a thin-film transistor having a source zone (10), a drain zone (11) and a channel zone (9), and also a source electrode (15), a drain electrode (16) and a gate electrode (13), the source electrode (15) or the drain electrode (16) has been extended so as to cover the channel zone (9) and thereby prevent the entry of light into the channel zone (9) and the generation of a light-induced current associated therewith.

Metal‐semiconductor field‐effect transistors fabricated in GaAs layers grown directly on Si substrates by molecular beam epitaxy

Abstract: Device‐quality GaAs layers have been grown directly on Si(100) substrates by molecular beam epitaxy. Metal‐semiconductor field‐effect transistors have been fabricated in these layers with transconductance as high as 85 mS/mm and leakage current as low as 1 μA at Vgs =−3 V for gate dimensions of 2.0 μm×200 μm.

Current sensing circuit

Abstract: A current sensing circuit is disclosed wherein a small portion of a load current is sampled through a sensing resistor and a substantially larger portion of the load current is allowed to bypass the sensing resistor. A first high current vertical MOS transistor is coupled between the load and the ground terminal. A second vertical MOS transistor is coupled in series between the load and ground terminal. The transistors are constructed in a vertical MOS cellular construction whereby the first transistor comprises on the order of three-thousand cells and the second transistor comprises a single cell. A signal is taken across the sensing resistor and may be provided as feedback to a control means driving the first and second transistors for performing a current limiting or constant current function.

Inversion-mode insulated-gate gallium arsenide field-effect transistors

Abstract: Inversion-mode insulated field-effect transistor structures are provided wherein a lightly-doped GaAs drift or drain region is combined with a gate-controlled channel structure comprising a film or layer of a semiconductor layer other than GaAs and within which inversion regions may more readily be formed. Suitable semiconductor materials for the gate-controlled channel structure are InP and Ga x In 1-x As. Presently preferred is a Ga x In 1-x As graded layer wherein x ranges from 1.0 to about 0.47.

Integrated circuit high voltage protection

Abstract: Protection of the thin gate oxide of MOS field effect transistors from irreversible puncture due to undesired high voltages and currents, generated by electrostatic discharge through handling or otherwise, is provided by a two stage circuit that operates to shunt thousands or tens of volts around the protected transistors. A first stage, employing a thick field effect transistor, protects against the very high voltage. A second stage, employing a thin field effect transistor, protects against lower but still excessive voltage. The protection circuit is formed as part of an integrated circuit chip by surrounding the lead bonding pad to which the protected transistors are connected.

A parametric short-channel MOS transistor model for subthreshold and strong inversion current

Abstract: A parametric model with short-channel capabilities is presented for MOS transistors. It covers the subthreshold and strong inversion regions with a continuous transition between these regions. The effects included in the model are mobility reduction, carrier velocity saturation, body effect, source-drain resistance, drain-induced barrier lowering, and channel length modulation. The model simulates accurately the current characteristics as well as the transconductance and output conductance characteristics which are important for analog circuit simulation.

The hemt: A superfast transistor: An experimental GaAs-AlGoAs device switches in picoseconds and generates little heat. This is just what supercomputers need

Abstract: A description is given of an experimental GaAs-AlGaAs device that switches in picoseconds and generates little heat. Known as MODFET or HEMT, the device is compared to other less conventional devices, and an outline is presented of its operation.

Comparison of high voltage devices for power integrated circuits

Abstract: A variety of lateral high voltage devices has been investigated for applications in power ICs, including RESURFed LDMOS transistors, merged bipolar-MOS transistors (LBMOS) and insulated gate rectifiers (LIGR). The devices are described and compared on the basis of current handling capability and switching speed. It is shown that for low load currents, the LDMOS exhibits superior performance, while for high load currents, the LIGR is advantageous, and the LBMOS shows only marginal improvement over the LDMOS at current gain of 5. In terms of switching, the LBMOS switches in 1-3 µsec, the LIGR in 3-10 µsec, and the LDMOS in tens of nsec. depending on the bias condition. The role of the substrate in lateral devices is also discussed.

Sinusoidal line current rectification with a 100kHZ B-SIT step-up converter

Abstract: A step-up converter circuit for the sinusoidal line current rectification at a unity power factor is described. A Bipolar-Static-Induction-Transitor (B-SIT) with extremely fast switching times is utilized. The gate drive and the snubber circuits are presented. A new way to achieve current hysteresis control without noise problems for switching frequencies up to 100 kHz is developed. Measured overall efficiency and the transistor losses are presented. At 1 kw dc output, the total transistor switching and conduction losses are 9 watts at about 100 kHz switching frequency. The overall rectification efficiency is in a 97–98.5% range. Justification for the use of step-up converters is given. Component selection and the stability in the feedback loop is analyzed. The converter is especially advantageous for single phase in — three phase out, variable frequency ac motor drives in lower horsepower applications.

Process for producing CMOS structures with Schottky bipolar transistors

Abstract: A process is disclosed for making CMOS transistors in combination with self-aligned fully oxide isolated Schottky clamped bipolar transistors.

A simple method for separation of the internal and external (peripheral) currents of bipolar transistors

Abstract: A simple method is described which enables the direct base and collector current of a bipolar transistor each to be separated into an internal and external (peripheral) part. Such a separation is, e.g. a necessary precondition for evaluating the reduction of current gain with decreasing emitter size and, furthermore, for estimating the effective internal base resistance as well as the emitter-current crowding due to the voltage drop across this resistance. The method described is based on very careful measurements of test transistors with different emitter geometries. The approach was experimentally verified with double-implanted high-speed transistors (transit frequency f T ⋍ 7 GHz ). For example, an emitter stripe width of about 2 μm leads to the following results: About 32% of the base current but only 9% of the collector current flow outside the emitter area defined by the implantation mask, resulting in a reduction of the common-emitter current gain to about 75% of its internal value.

CMOS schmitt triggers

Abstract: Two variants of CMOS Schmitt triggers, consisting of only four enhancement-type MOS transistors, are proposed in the paper. One consists of three NMOS transistors and one PMOS transistor, while the other consists of one NMOS and three PMOS transistors. A Schmitt trigger with three pairs of CMOS transistors is also described. The hysteresis voltage depends on supply voltage and transistor geometry.

Photosensitive device for the infrared range

Abstract: A photosensitive device for the infrared range wherein each detector is connected to a first and a second MOS transistor. The second MOS transistors are addressed, column by column, by a first shift register. The first MOS transistors are connected, line by line, to a charge storage capacity and to a third charge reading MOS transistor addressed by a second shift register. The whole of the device is placed in a cryostat which only has a single output.