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Showing papers on "Transistor published in 1985"


Journal ArticleDOI
TL;DR: Devices available in digital oriented CMOS processes are reviewed, with emphasis on the various modes of operation of a standard transistor and their respective merits, and on additional specifications required to apply devices in analog circuits.
Abstract: Devices available in digital oriented CMOS processes are reviewed, with emphasis on the various modes of operation of a standard transistor and their respective merits, and on additional specifications required to apply devices in analog circuits. Some basic compatible analog circuit techniques and their related tradeoffs are then surveyed by means of typical examples. The noisy environment due to cohabitation on the chip with digital circuits is briefly evoked.

319 citations


Journal ArticleDOI
TL;DR: In this article, a negative conductance device consisting of a heterojunction bipolar transistor with a quantum well and a symmetric double barrier or a superlattice in the base region is proposed.
Abstract: We propose a new negative conductance device consisting of a heterojunction bipolar transistor with a quantum well and a symmetric double barrier or a superlattice in the base region. The key difference compared to previously studied structures is that resonant tunneling is achieved by high‐energy minority carrier injection into the quantum state rather than by application of an electric field. Thus this novel geometry maintains the crucial, structural symmetry of the double barrier, allowing unity transmission at all resonance peaks and higher peak‐to‐valley ratios and currents compared to conventional resonant tunneling structures. Both tunneling and ballistic injection in the base are considered. These new functional devices have significant potential for a variety of signal processing and multiple‐valued logic applications and for the study of the physics of transport in superlattices.

314 citations


Journal ArticleDOI
TL;DR: In this article, a hot electron transistor (RHET) is demonstrated in which electrons are injected from emitter to base by resonant-tunneling through a quantum well, and are near-ballistically transferred to a collector.
Abstract: -A new functional, resonant-tunneling hot electron transistor (RHET) is demonstrated in which electrons are injected from emitter to base by resonant-tunneling through a quantum well, and are near-ballistically transferred to a collector. The main feature of this device is a peaked collector-current characteristic with respect to the base-emitter voltage. This enables us to build a frequency multiplier or an Exclusive-NOR gate using only one transistor.

276 citations


Journal ArticleDOI
TL;DR: In this paper, the Moll and Ross integral relations for the current flow through the base region of a bipolar transistor and for the base transit time were generalized to the case of a heterostructure bipolar transistor with a nonuniform energy gap.
Abstract: The two integral relations by Moll and Ross for the current flow through the base region of a bipolar transistor, and for the base transit time, are generalized to the case of a heterostructure bipolar transistor with a nonuniform energy gap in the base region.

247 citations


Journal ArticleDOI
TL;DR: The delay modeler executes 10 000 times as fast as SPICE, yet produces delay estimates that are typically within 10 percent of SPICE for digital circuits.
Abstract: Crystal is a timing verification program for digital nMOS and CMOS circuits. Using the circuit extracted from a mask set, the program determines the length of each clock phase and pinpoints the longest paths. Crystal can process circuits with about 40 000 transistors in about 20-30 min of VAX-11/780 CPU time. The program uses a switch-level approach in which the circuit is decomposed into chains of switches called stages. A depth-first search, with pruning, is used to trace out stages and locate the critical paths. Bidirectional pass transistor arrays are handled by having the designer tag such structures with flow control information, which is used by Crystal to avoid endless searches. Delays are computed on a stage-by-stage basis, using a simple resistor-switch model based on rise-time ratios (a measure of how fully turned-on the transistors in the stage are). The delay modeler executes 10 000 times as fast as SPICE, yet produces delay estimates that are typically within 10 percent of SPICE for digital circuits.

246 citations


Journal ArticleDOI
A. Yukawa1
TL;DR: In this article, a novel high-speed low-power CMOS balanced comparator circuit is proposed and implemented in an 8M fully parallel analog-to-digital (A/D) converter IC.
Abstract: A novel high-speed low-power CMOS balanced comparator circuit is proposed and implemented in an 8M fully parallel analog-to-digital (A/D) converter IC. A 20-MHz sampling rate with 350-mW power dissipation from a single 5-V power supply has been realized. Integral linearity of /spl plusmn/ 1/2 LSB to 8-bit conversion has been achieved through intensive transistor dimension optimization applied to the comparator circuit, instead of employing an offset canceling technique.

192 citations


Patent
25 Apr 1985
TL;DR: In this article, a film field effect transistor is proposed to operate at fast switching rates for use in video display applications, where the transistor includes a body of silicon semiconductor material having a structure more ordered than amorphous material and less ordered than single crystalline material.
Abstract: There is disclosed a film field effect transistor which can be operated at fast switching rates for use, for example, in video display applications. The transistor includes a body of silicon semiconductor material having a structure more ordered than amorphous material and less ordered than single crystalline material. The source and drain of the transistor comprise rectifying contacts formed on the body of silicon semiconductor material. Also disclosed are a method of making the transistor and an electronically addressable array system utilizing the transistor to advantage.

192 citations


Journal ArticleDOI
TL;DR: In this paper, the transistor action in a Si/CoSi2/Si structure is reported, where the thin silicide layer is a single-crystal metal, essentially continuous and locally exhibiting atomically perfect interfaces with Si.
Abstract: We report transistor action in a Si/CoSi2/Si structure. The thin silicide layer (<100 A), which acts as the base, is a single‐crystal metal, essentially continuous and locally exhibiting atomically perfect interfaces with Si. The transistor action is manifested by a common base current gain α as high as 0.6 and a voltage gain greater than 10.

159 citations


Journal ArticleDOI
TL;DR: In this paper, the effects of ionizing radiation on discrete MOS n- and p-channel transistors are correlated with performance degradation of CMOS integrated circuits, and the individual components of radiation induced charge, oxide-trapped charge and interface-state charge, are separated using a subthreshold current technique.
Abstract: The effects of ionizing radiation on discrete MOS n- and p-channel transistors are correlated with performance degradation of CMOS integrated circuits. The individual components of radiation induced charge, oxide-trapped charge and interface-state charge, are separated using a subthreshold current technique. Processing splits and post-irradiation biased anneals are used to vary the ratio of oxide-trapped charge to interface-state charge. It is shown that the effective channel mobility depends to first order on the interface-state charge density. Static power supply current is correlated with the n-channel leakage at zero gate voltage while output drive currents are a function of both threshold voltage and channel mobility. Changes in propagation delay of signals through integrated circuits can be understood when both mobility and threshold voltage are considered as a function of the bias dependent charge buildup. A new transistor switching time figure of merit, t/C, which measures the drain to source drive over a full logic level voltage swing at the drain node, is introduced. This index is then shown to correlate with propagation delay in an IC. Finally, performance changes in an IC are modeled using only the measured buildup of oxide-trapped and interface-state charges from transistors as a function of radiation.

150 citations


Patent
26 Apr 1985
TL;DR: In this article, integrated circuit compatible thin film field effect transistors which can be fabricated at low temperatures and operated at fast switching rates for use, for example, in video rate applications are disclosed.
Abstract: There is disclosed integrated circuit compatible thin film field effect transistors which can be fabricated at low temperatures and operated at fast switching rates for use, for example, in video rate applications. The transistors include a silicon-germanium alloy body having a structure more ordered than amorphous material and less ordered than single crystalline material. The source and drain of the transistors are rectifying contacts formed on or in the body. Also disclosed are a method of making the transistors and an electronically addressable array system utilizing the transistors to advantage.

129 citations


Proceedings ArticleDOI
01 Dec 1985
TL;DR: In this article, a 1T DRAM cell with both the transistor and the capacitor fabricated on the sidewalls of a deep trench is described, and its fabrication and characterization is discussed.
Abstract: A 1T DRAM cell with both the transistor and the capacitor fabricated on the sidewalls of a deep trench is described. Trench Transistor Cell (TTC) fabrication and characterization are discussed.

Journal ArticleDOI
TL;DR: A new family of ternary logic circuits that uses both depletion and enhancement types of complementary metal-oxide semiconductor (CMOS) transistors is presented.
Abstract: A new family of ternary logic circuits that uses both depletion and enhancement types of complementary metal-oxide semiconductor (CMOS) transistors is presented. These circuits use two power supplies, each below the transistor's threshold voltages, and do not include resistors. Circuit designs of basic ternary operators (inverters, NAND, NOR) are described. These basic ternary operators can be used as building blocks in the VLSI implementation of three-valued digital systems. An example of the design of a ternary full adder using this family of logic circuits is also presented.

Journal ArticleDOI
TL;DR: In this paper, two formal design techniques are presented to realize pass logic networks in NMOS and CMOS technologies, which can be effective tool for the design of networks up to five or six variables.
Abstract: Two formal design techniques are presented to realize pass logic networks in NMOS and CMOS technologies. The first technique uses a modified Karnaugh map minimization procedure, which can be effective tool for the design of networks up to five or six variables. For networks involving more than six variables, an algorithmic procedure is developed by modifying the conventional Quine-McCluskey approach. The savings in silicon area depends on the transistor count as well as the interconnect structure. Maximum topograph regularity for an array of pass transistors can be achieved in the intersection of the set of control variables with the set of pass variables in a null set. This allows the pass variables and the control variables to flow at right angles to each other. This requirement may increase the transistor count in the design, hence there is a tradeoff between topological regularity and transistor count. Cells drawn in CMOS and NMOS are compared.

Patent
07 Jun 1985
TL;DR: An integrated circuit for a miniaturized solid-state chemical sensor as mentioned in this paper includes a chemical-selective membrane which provides an electric signal in response to contact with a particular chemical or group of chemicals in a fluid.
Abstract: An integrated circuit for a miniaturized solid-state chemical sensor. The integrated circuit includes a chemical-selective membrane which provides an electric signal in response to contact with a particular chemical or group of chemicals in a fluid. The chemical-selective membrane is attached to the integrated circuit by a membrane definition layer. An electrically conductive layer beneath the membrane definition layer provides electrical contact between the chemical-selective membrane and one of the input transistors of the voltage-follower amplifier. The chemical-selective membrane is formed separately from the gate of the input transistors and is designed as a integrated input to the amplifier. The output of the chemical sensor is a low impedance electric signal represented as a voltage which corresponds to the chemical activity present at the chemical-selective membrane/fluid interface. In one embodiment, multiple chemical sensors are fabricated on a single integrated circuit wherein each chemical-selective sensor forms an integrated input to a separate amplifier. Included on the integrated circuit of that embodiment is circuitry to allow for multiplexing of the outputs of the amplifiers to one or both of two output pads provided on the integrated circuit.

Patent
18 Sep 1985
TL;DR: In this article, a dRAM cell and array of cells, together with a method of fabrication, was described, where the cell includes one field effect transistor and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate.
Abstract: A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate. The transistor source and drain are insulated from the substrate, and the transistor may be adjacent the trench or on the upper portion of the trench sidewalls. Signal charge is stored on the capacitor plate insulated from the substrate.

Patent
Lu Nicky Chau-Chun1
21 Oct 1985
TL;DR: In this paper, a three-dimensional DRAM device with a single-crystal access transistor stacked on top of a trench capacitor and a fabrication method therefor where crystallization seeds are provided by the singlecrystal semiconductor area surrounding the cell and/or from the vertical sidewalls of the trench and wherein the access transistor is isolated by insulator.
Abstract: Dynamic random access memory (DRAM) devices are taught wherein individual cells, including an access transistor and a storage capacitor are formed on a single-crystal semiconductor chip, and more particularly a three-dimensional dynamic random access memory (DRAM) device structure is described having a single-crystal access transistor stacked on top of a trench capacitor and a fabrication method therefor wherein crystallization seeds are provided by the single-crystal semiconductor area surrounding the cell and/or from the vertical sidewalls of the trench and wherein the access transistor is isolated by insulator. In the structure, a trench is located in a p+ type substrate containing heavily doped N+ polysilicon. A composite film of SiO 2 /Si 3 N 4 /SiO 2 is provided for the capacitor storage insulator. A thin layer of SiO 2 is disposed over the polysilicon. A lightly doped p-type epi silicon layer is located over the substrate and SiO 2 layer. The access transistor for the memory cell is located on top of the trench capacitor. An N+ doped material connects the source region of the transistor to the polysilicon inside the trench. A medium doped p-region on top of the trench surface may be provided in case there is any significant amount of leakage current along the trench surface.

Journal ArticleDOI
TL;DR: In this paper, a systematic method is given for generating negative-resistance circuits made of 2 transistors and linear positive resistors only, which can be integrated as a two-terminal device in monolithic form.
Abstract: A systematic method is given for generating negative-resistance circuits made of 2 transistors and linear positive resistors only. The 2 transistors may be bioolar ( n-p-n or p-n-p ), JFET ( n -channel or p-channel), MOSFET ( n -channel or p -channel), or their combinations. Since the circuits do not require an internal power supply, they are passive and can be integrated as a two-terminal device in monolithic form. Two algorithms are given for generating a negative-resistance device which exhibits either a type- N \upsilon - i characteristic similar to that of a tunnel diode, or a type- S \upsilon -i characteristic similar to that of a four-layered p-n-p-n diode. Hundreds of new and potentially useful negative resistance devices have been discovered. A selected catalog of many such prototype negative-resistance devices is included for future applications.

Patent
14 Nov 1985
TL;DR: In this article, a reference potential generator circuit on a data detection circuit is used to produce a voltage in accordance with a memory element with respect to the reference potential through a current/voltage converting element.
Abstract: PURPOSE:To make the allowance with respect to noises larger and to speed up actions by providing a reference potential generator circuit on a data detection circuit and producing a voltage in accordance with a memory element with respect to the reference potential through a current/voltage converting element. CONSTITUTION:After an output terminal 11 of a row line 12 is made to a grounding potential by transistors 13 and 19 for switching on and off sequentially, it is made into a high potential. Then a row selection transistor 2 is turned on, while a transistor 3 of an ROM memory element is also turned on in accordance with the storage content when a threshold is small. A current flows through a resistance 7 of a current/voltage converting element from a reference potential generator circuit 18 of a detection circuit, and a lower storage contents with respect to the reference potential is detected as a voltage irrespective of a power supply voltage, etc. On the other hand, when the threshold of the storage contents is larger, the transistor 3 is turned off, and the storage contents are detected as a high voltage with respect to the reference potential on the basis of a current for flowing in the circuit 18. As a result, even if a resistance value of the resistance 1 is set larger, a action speed will not drop, and a high speed action can be possible with a larger allowance degree against noises caused by the fluctuation of the power source.

Patent
08 Feb 1985
TL;DR: In this paper, a charge pump for providing programming voltages to the word lines of a semiconductor memory array is presented, which prevents DC current from flowing from the source of the programming voltage to ground through unselected word lines, and thereby permits the design of semiconductor programmable memory arrays having on-chip programming voltage generation.
Abstract: A charge pump for providing programming voltages to the word lines of a semiconductor memory array is disclosed. The charge pump, configured as a combination of enhancement and native MOS transistors, prevents DC current from flowing from the source of the programming voltage to ground through unselected word lines, and thereby permits the design of semiconductor programmable memory arrays having on-chip programming voltage generation, allowing for design of semiconductor programmable memory arrays which operate from a single voltage power supply.

Patent
21 Jun 1985
TL;DR: In this paper, a bipolar switching device of field-drive type includes a bipolar component having a pnp transistor portion (8) and a npn transistor portion(9), being connected to cause a positive feedback, and an n-channel MOS transistor (11) connected across an emitter and a collector electrode (n2) of said nPN transistor portion.
Abstract: A semiconductor switching device of field-drive type includes a bipolar component having a pnp transistor portion (8) and a npn transistor portion (9), said pnp transistor portion (8) and said npn transistor portion (9) being connected to cause a positive feedback, and a n-channel MOS transistor (11) connected across an emitter electrode (n3) and a collector electrode (n2) of said npn transistor portion (9), wherein a p-channel MOS transistor (10) is connected across an emitter electrode (p1) and a connector electrode (p2) of the pnp transistor portion (8), and a control terminal of said n-channel MOS transistor (11) is electrically connected with a control terminal of said p-channel MOS transistor (10). Said device is operable to control the main drive section even in the floating state and to drive the main drive section by a small control current.

Journal ArticleDOI
TL;DR: In this article, the authors proposed a new solid-state field-effect bipolar device for bipolar inversion channel field effect transistor (BICFET), which is bipolar in nature and relies upon the field effect inducement of an inversion layer, that corresponds to the conventional neutral base of a bipolar transistor.
Abstract: A new solid-state field-effect bipolar device designated the BICFET for bipolar inversion channel field-effect transistor is proposed. The device, which is bipolar in nature and relies upon the field-effect inducement of an inversion layer, that corresponds to the conventional neutral base of a bipolar transistor, features potentially very high current gain (105), very high current operation (106A/cm2) and thus high transconductance (4 × 107S/cm2) and low input capacitance. The BICFET has three terminals: a metallic emitter which makes ohmic contact to a semi-insulator (wide bandgap semiconductor); a source terminal which contacts an inversion layer formed at the interface between the semi-insulator and the semiconductor depletion region; and a collector which is the semiconductor bulk. An important feature of this bipolar device is the absence of the base layer and all of its associated problems. The principle of operation is based on controlling the flow of majority carriers through the semi-insulating region to the collector by the biasing action of charge in the inversion channel. A significant advantage of the BICFET structure is that it is not subject to the scaling limitations due to punchthrough as in the MOS or junction bipolar transistor. The problem of threshold control in the MOS transistor is avoided, so the requirement of very shallow junctions may be relaxed.

Proceedings ArticleDOI
S. Mukherjee, T. Chang, R. Pang, M. Knecht, D. Hu 
01 Jan 1985
TL;DR: In this article, the authors describe an electrically programmable and erasable nonvolatile memory cell employing a single floating gate transistor and its implementation in a 512K CMOS EEPROM memory chip.
Abstract: This paper describes an electrically programmable and erasable nonvolatile memory cell employing a single floating gate transistor (1), and its implementation in a 512K CMOS EEPROM memory chip. The single transistor EEPROM cell is based on an innovative device concept, and utilizes proven process techniques. The cell is programmed to a high Vt state by channel hot electron injection like an EPROM cell, and erased to a low Vt state by Fowler Nordheim tunneling from the floating gate to source diffusion. With the proper choice of gate dielectric and cell layout the cell is programmed to high threshold with less than 5 volts on the drain and less than 15 volts on the control gate. Erasing is achieved with less than 15 volts on the source diffusion. A 25 square micron cell has been implemented in a 512K EEPROM memory chip with a die size of 4.3 mm. by 7 mm.

Journal ArticleDOI
TL;DR: In this paper, an analysis of a resonant converter which contains a capacitive-input output filter, rather than the more conventional inductor-input input filter, is presented along with design curves along with experimental data.
Abstract: Resonant dc-dc converters offer several advantages over the more conventional PWM converters. Some of these advantages include: 1) low switching losses and low transistor stresses; 2) medium speed diodes are sufficient (transistor parasitic, inverse-parallel diodes can be used, even for frequencies in the hundreds of kilohertz); and 3) ability to step the input voltage up or down. This paper presents an analysis of a resonant converter which contains a capacitive-input output filter, rather than the more conventional inductor-input output filter. The switching waveforms are derived and design curves presented along with experimental data. The results are compared to the inductor-input filter case obtained from an earlier paper.

Book Chapter
01 Jan 1985
TL;DR: In this paper, the elements of an electronic receptor with many orders of magnitude dynamic range are described, and the key to very sensitive receptors is to use the current gain of this very clean bipolar transistor before subjecting the signal to any noise from subsequent amplification stages.
Abstract: The photoreceptors in biological systems give meaningful outputs over about six orders of magnitude of illumination intensity. If we are to build an electronic vision system that is truly useful, it must have a similar dynamic range. The elements of an electronic receptor with many orders of magnitude dynamic range are described below. Experimental devices were fabricated in p-well cMOS bulk technology through the MOSIS foundry; npn phototransistors with collector connected to substrate are a byproduct of this process. The n-type bulk forms the collector, the p-well is the base, and the n+ diffusion the emitter. In a typical process, a large transistor of this sort has a current gain β of more than a thousand. Smaller transistors have lower current gains, but are still respectable. The key to very sensitive receptors is to use the current gain of this very clean bipolar transistor before subjecting the signal to any noise from subsequent amplification stages.

Journal ArticleDOI
TL;DR: In this paper, the relative positions of the base and collector are interchanged from conventional emitter-base-collector sequence to obtain negligible base currents and large current transfer ratios.
Abstract: Two novel three‐terminal devices based on tunneling in quantum well and quantum barrier heterostructures are proposed and analyzed theoretically. In both devices, the relative positions of the base and collector are interchanged from conventional emitter‐base‐collector sequence. This provides a means for obtaining negligible base currents and large current transfer ratios. In both cases, a base voltage controls the emitter‐collector tunneling current by shifting the resonances in a quantum well. Calculations indicate that significant variations in the emitter‐collector current‐voltage characteristics can be obtained for reasonable base‐emitter voltages. We call the two devices a Stark effect transistor and a negative resistance Stark effect transistor, respectively.

Journal ArticleDOI
TL;DR: In this paper, the authors derived analytical formulas for the current and stored charge in a vertical bipolar transistor and showed how current and charge depend on minority carrier concentrations, which in turn are functions of junction voltages.
Abstract: New, compact analytical formulas for the current and stored charge in a vertical bipolar transistor are derived. The derivation is not based on the charge control concept, but shows how current and charge depend on minority carrier concentrations, which in turn are functions of junction voltages. In this way the influence of the built-in field, the bias-dependent transit times, and the Early effect are incorporated quite naturally. The new set of equations is the framework of a complete transistor model for computer-aided circuit design purposes.

Patent
15 Jul 1985
TL;DR: In this paper, a PNP transistor is formed in a monocrystalline semiconductor body having a buried N+ region within the body and a P type collector region is located around the side periphery of the emitter region.
Abstract: The lateral transistor is described which has both its base width and the emitter region of the transistor minimized. This minimization of the elements of the lateral transistor gives high performance. The lateral transistor which may be typically PNP transistor is formed in a monocrystalline semiconductor body having a buried N+ region within the body. A P type emitter region is located in the body. An N type base region is located around the side periphery of the emitter region. A P type collector region is located in the body surrounding the periphery of the base region. A first P+ polycrystalline silicon layer acting as an emitter contact for the emitter region is in physical and electrical contact with the emitter region and acts as its electrical contact. A second P+ polycrystalline silicon layer is located on the surface of the body to make physical and electrical contact with the collector region. A vertical insulator layer on the edge of the second polycrystalline silicon layer isolates the two polycrystalline silicon layers from one another. The N base region at its surface is located underneath the width of the vertical insulator layer. An N+ reach-through region extending from the surface of the body to the buried N+ region acts as an electrical contact through the N+ region layer to the base region. The width of the vertical insulator has a width which is equal to the desired base width of the lateral PNP transistor plus lateral diffusions of the collector and emitter junctions of the lateral PNP. The preferred structure is to have the emitter formed around the periphery of a channel or groove which has at its base an insulating layer such as silicon dioxide. The parasitic transistor is almost totally eliminated by this buried oxide isolation.

Journal ArticleDOI
TL;DR: This paper proposes a new logical model for nMOS and CMOS circuits in the form of a multivalued algebra defined on a set of node states that allows for strong interactions between all three terminals of a transistor.
Abstract: This paper proposes a new logical model for nMOS and CMOS circuits. Existing gate-level and switch-level models are limited in their ability to simulate MOS circuit behavior accurately when modeling physical failures. The model proposed in this paper is in the form of a multivalued algebra defined on a set of node states. The state of a node is represented as a pair where "a" specifies the condition of a node and "b" specifies the logic level: There are five conditions and five logic levels. The assignment of node states is done dynamically during the process of logic simulation. The rules of the algebra are used to derive state tables that model the behavior of transistors. Our general model of a transistor allows for strong interactions between all three terminals of a transistor. This enables us to model the effects of physical failures such as a short between the gate and drain of a transistor. A simulation algorithm based on the algebra is discussed, and techniques for simulating physical failures in MOS circuits using the algebra are indicated.

Patent
27 Sep 1985
TL;DR: In this article, an integrated circuit structure includes both low-voltage n-channel and p-channel MOS transistors (LV-NMOS), and highvoltage hV-n-channel transistors and HV-PMOS transistor (HV-NMS transistors).
Abstract: An integrated circuit structure includes both low-voltage n-channel and p-channel MOS transistors (LV-NMOS transistors and LV-PMOS transistors) and high-voltage n-channel and p-channel MOS transistors (HV-NMOS transistors and HV-PMOS transistors). There are formed at the same time first p - regions for the compartments of the LV-NMOS transistors, second p - regions in which only the sources and channels of the HV-NMOS transistors are incorporated, and third p - regions in which only the drains of the HV-PMOS transistors are incorporated.

Patent
22 Mar 1985
TL;DR: In this article, a semiconductor memory device provided with a plurality of memory cells each comprised of an insulated gate field effect transistor having first and second semiconductor regions of a first conductivity type formed separately from one another in a substrate of a second conductivities type, two bits can be stored in each transistor.
Abstract: In a semiconductor memory device provided with a plurality of memory cells each comprised of an insulated gate field effect transistor having first and second semiconductor regions of a first conductivity type formed separately from one another in a substrate of a second conductivity type, two bits can be stored in each transistor The threshold voltages of the portions adjacent to the first region and/or the second region are raised by writing data Since data can be written in at either the first or second regions, two bits can be effectively stored in each insulated gate field effect transistor The first bit is read out under the state in which the first region serves as the drain and the second region, as the source, and the second bit is read out under the state in which the first region serves as the source and the second region, as the drain