Showing papers on "Transistor published in 1987"

Operation and modeling of the MOS transistor

Abstract: 1. SEMICONDUCTORS, JUNCTIONS AND MOFSET OVERVIEW 2. THE TWO-TERMINAL MOS STRUCTURE 3. THE THREE-TERMINAL MOS STRUCTURE 4. THE FOUR-TERMINAL MOS STRUCTURE 5. MOS TRANSISTORS WITH ION-IMPLANTED CHANNELS 6. SMALL-DIMENSION EFFECTS 7. THE MOS TRANSISTOR IN DYNAMIC OPERATION - LARGE-SIGNAL MODELING 8. SMALL-SIGNAL MODELING FOR LOW AND MEDIUM FREQUENCIES 9. HIGH-FREQUENCY SMALL-SIGNAL MODELS 10.MOFSET MODELING FOR CIRCUIT SIMULATION

Modern power devices

Abstract: Carrier Transport Physics Breakdown Voltage Power Junction Field-Effect Transistors Power Field-Controlled Diodes Power Metal-Oxide-Semiconductor Field Effect Transistors Power MOS-Bipolar Devices New Rectifier Concepts Synopsis References Index

Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance

Abstract: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion. This original method of transistor operation offers excellent device performance, in particular great increases in subthreshold slope, transconductance, and drain current. A simulation program and experiments on SIMOX structures are used to study the new device.

Dramatic enhancement in the gain of a GaAs/AlGaAs heterostructure bipolar transistor by surface chemical passivation

Abstract: With a simple chemical treatment we have passivated nonradiative recombination centers at the periphery of a GaAs/AlGaAs heterostructure bipolar transistor, resulting in a 60‐fold increase in the current gain of the device at low collector currents. This large enhancement in gain was achieved by spin coating thin films of Na2S9H2O onto the devices after their fabrication. We briefly discuss the passivation mechanism and the implications for other III‐V optoelectronic devices.

BSIM: Berkeley short-channel IGFET model for MOS transistors

Abstract: The Berkeley short-channel IGFET model (BSIM), an accurate and computationally efficient MOS transistor model, and its associated characterization facility for advanced integrated-circuit design are described. Both the strong-inversion and weak-inversion components of the drain current expression are included. In order to speed up the circuit-simulation execution time, the dependence of the drain current on the substrate bias has been modeled with a numerical approximation. This approximation also simplifies the transistor terminal-charge expressions. The charge model was derived from its drain-current counterpart to preserve consistency of device physics. Charge conservation is guaranteed in this model.

A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation

Abstract: The examined class of circuits includes voltage multipliers, current multipliers, linear V-I convertors, linear I-V convertors, current squaring circuits, and current divider circuits. Typical for these circuits is an independent control of the sum as well as the difference between two gate-source voltages. As direct use is made of the basic device characteristics, only a small number of transistors is required in the presented circuits.

A versatile CMOS linear transconductor/square-law function

Abstract: A simple CMOS circuit technique for realizing both linear transconductance and a precision square-law function is described. The circuit provides two separate outputs in the linear as well as square-law modes. The linear outputs both have a range of 100% or more of the total quiescent current value. The theory of operation is presented and effects of transistor nonidealities on the performance are investigated. Design optimization techniques are developed. Experimental results measured on nonoptimized prototypes are: distortion of 0.2% for input signals up to 2.4 V/SUB p-p/ in the case of linear transfer function and 1.3% in the case of the square-law transfer function, with a DC to -3-dB bandwidth of up to 20 MHz. Improved performance is expected when the optimization techniques developed are applied. The circuit is versatile in application: diverse applications are demonstrated in the fields of linear amplifiers, continuous-time filters, and nonlinear function implementation.

A true single-transistor oxide-nitride-oxide EEPROM device

Abstract: A novel single-transistor EEPROM device using single-polysilicon technology is described. This memory is programmed by channel hot-electron injection and the charges are stored in the oxide-nitride-oxide (ONO) gate dielectric. Erasing is accomplished in milliseconds by applying a positive voltage to the drain plus an optional negative voltage to the gate causing electron tunneling and/or hot-hole injection due to the deep-depletion-mode drain breakdown. Since the injection and storage of electrons and holes are confined to a short region near the drain, the part of the channel near the source maintains the original positive threshold voltage even after repeated erase operation. Therefore a select transistor, separate or integral, is not needed. Because oxide layers with a thickness larger than 60 A are used, this device has much better data retention characteristics than conventional MNOS memory cells. This device has been successfully tested for WRITE/ERASE endurance to 10000 cycles.

Dynamic sense amplifier for CMOS static RAM

Abstract: A sense amplifier for use in a CMOS static random access memory. The core of the sense amplifier comprises seven transistors: two sensing transistors with their sources coupled to a common pull down node, a pull down transistor for drawing current from the pull down node during sensing operations, and a four transistor latch coupled to the drains of the two sensing transistors. The four transistor latch comprises two cross coupled CMOS inverters. When the pull down transistor is activated, the four transistor latch automatically amplifies the voltage differential on the gates of the two sensing transistors, typically latching in less than two nanoseconds. Since the latch is made up of CMOS inverters, no d.c. current is drawn by the sense amplifier after the input data has been sensed and latched. As a result, relatively powerful transistors can be used in the sense amplifier. The use of powerful transistors to produce differential output signals significantly reduces the amount of circuitry needed in the output driver of the memory device incorporating this sense amplifier. Furthermore, this sense amplifier significantly improves the access time of a memory device by enabling sensing with very small input signals from a memory cell, and by reducing the delay between sensing and providing an external data output signal.

High-temperature point-contact transistors and Schottky diodes formed on synthetic boron-doped diamond

Abstract: Point-contact transistors and Schottky diodes have been formed on synthetic boron-doped diamond. This is the first report of diamond transistors that have power gain. Further, the transistors exhibited power gain at 510°C and the Schottky diodes were operational at 700°C.

An SOI voltage-controlled bipolar-MOS device

Abstract: This paper describes a new operation mode of the SOI MOSFET. Connecting the floating substrate to the gate in a short-channel SOI MOSFET allows lateral bipolar current to be added to the MOS channel current and thereby enhances the current drive capability of the device. Part of the bipolar current emitted by the source terminal merges into the channel before reaching the drain, which renders the base width substantially shorter than the gate length. This novel operating mode of a short-channel SOI transistor is particularly attractive for high-speed operation, since the device is capable of both reduced voltage swing operation and high current drive, n-p-n and p-n-p devices, as well as complementary inverters have been successfully fabricated.

A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic

Abstract: Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique that has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. A detailed comparison of DCVS logic and conventional logic is carried out by simulation, using SPICE, of the performance of full adders designed using the different circuit techniques. The parameters compared are: input gate capacitance, number of transistors required, propagation delay time, and average power dissipation. In the static case, DCVS appears to be superior to full CMOS in regards to input capacitance and device count but inferior in regards to power dissipation. The speeds of the two technologies are similar. In the dynamic case, DCVS can be faster than more conventional CMOS dynamic logic, but only at the expense of increased device count and power dissipation.

Metal--Metal Matrix (M /sup 3/) for High-Speed MOS VLSI Layout

Abstract: This paper proposes a new layout method for high-speed VLSI circuits in single-poly and double-metal MOS technology. With emphasis on the speed performance, our Metal-Metal Matrix (M /sup 3/) layout method employs maximal use of metal interconnections while restricting delay-consuming polysilicon or polycide features only to form MOS transistor gates or to connect the same type of transistor gates with common input signals. M /sup 3/ layout is also amenable to submicron technology trends and existing CAD tools for single-poly and single-metal chip assembly and routing. Our layout studies indicate that M /sup 3/ is particularly appealing to high-speed dynamic CMOS circuits in view of packing density and speed performance. This new structure has not been experimented with VLSI chip fabrication yet and awaits empirical verification.

A new three-terminal tunnel device

Abstract: A Zener effect has been identified in the trench transistor cell (TTC) which is used in Texas Instruments' 4-Mbit DRAM. This paper discusses a closed-form analytical model for the tunneling current in the TTC. The effect is also verified in a novel planar MOS structure.

Photoelectric converting apparatus

Abstract: A photoelectric converting apparatus of the present invention includes a photoelectric converting element, a resetting transistor in which a source is connected to the photoelectric converting element and a drain is connected to a resetting power source, a readout transistor in which a gate is connected to the photoelectric converting element and a drain is connected to a readout power source, a signal line connected to a source of the readout transistor, a selecting transistor connected between the readout power source or the signal line and the readout transistor, and a constant current source connected to the signal line.

Submicrometer-channel CMOS for low-temperature operation

Abstract: A 0.5-µm-channel CMOS design optimized for liquid-nitrogen temperature operation is described. Thin gate oxide (12.5 nm) and dual polysilicon work functions (n+-poly gate for n-channel and p+-poly for p-channel transistors) are used. The power supply voltage is chosen to be 2.5 V based on performance, hot-carrier effects, and power dissipation considerations. The doping profiles of the channel and the background (substrate or well) are chosen to optimize the mobility, substrate sensitivity, and junction capacitance with minimum process complexity. The reduced supply voltage enables the use of silicided shallow arsenic and boron junctions, without any intentional junction grading, to control short-channel effects and to reduce the parasitic series resistance at 77 K. The same self-aligned silicide over the polysilicon gate electrode reduces the sheet resistance (as low as 1 Ω/sq at 77 K) and provides the strapping between the gates of the complementary transistors. The design has been demonstrated by a simple n-well/p-substrate CMOS process with very good device characteristics and ring-oscillator performance at 77 K.

Vertical type MOS transistor and method of formation thereof

Abstract: A vertical MOS transistor having its channel length determined by the thickness of an insulating layer provided over a semiconductor substrate, rather than by the depth of a trench in which the transistor is formed. As a result, the characteristics of the transistor as relatively unaffected by doping and heat-treatment steps which are performed during formation. Also, the transistor may be formed so as to occupy very little surface area, making it suitable for application in high-density DRAMs. 0O048455372

AlGaAs/GaAs heterojunction bipolar transistors fabricated using a self-aligned dual-lift-off process

Abstract: This paper describes a self-aligned heterojunction-bipolar-transistor (HBT) process based on a simple dual-lift-off method. Transistors with emitter width down to 1.2 µm and base doping up to 1 × 1020/cm3have been fabricated. Extrapolated current gain cutoff frequency f t of 55 GHz and maximum frequency of oscillation f_{\max} of 105 GHz have been obtained. Current-mode-logic (CML) ring oscillators with propagation delays as low as 14.2 ps have been demonstrated. These are record performance results for bipolar transistors. The dual-lift-off process is promising for both millimeter-wave devices and large-scale integrated circuit fabrication.

Introduction To Semiconductor Device Modelling

Abstract: This book deals mainly with physical device models which are developed from the carrier transport physics and device geometry considerations. The text concentrates on silicon and gallium arsenide devices and includes models of silicon bipolar junction transistors, junction field effect transistors (JFETs), MESFETs, silicon and GaAs MESFETs, transferred electron devices, pn junction diodes and Schottky varactor diodes. The modelling techniques of more recent devices such as the heterojunction bipolar transistors (HBT) and the high electron mobility transistors are discussed. This book contains details of models for both equilibrium and non-equilibrium transport conditions. The modelling Technique of Small-scale devices is discussed and techniques applicable to submicron-dimensioned devices are included. A section on modern quantum transport analysis techniques is included. Details of essential numerical schemes are given and a variety of device models are used to illustrate the application of these techniques in various fields.

Dc-to-Dc converters using multi-resonant switches

Abstract: A generalized multi-resonant switch that combines current-mode and voltage-mode resonant switches. Application of the multi-resonant switch in zero-voltage switched multi-resonant converters results in reduction of the voltage stress to the switching transistor, increase of the load range and reduction of the switching frequency bandwidth. Each embodiment of the multi-resonant converter includes a multi-resonant switch having an active switch, a passive switch and reactive components for causing the active and passive switches to operate in a multi-resonant manner.

Room‐temperature operation of hot‐electron transistors

Abstract: We demonstrate the first room‐temperature operation of a double heterojunction unipolar hot‐electron transistor. Our test structure has a current gain greater than 10 and a measured current drive capability in excess of 1200 A cm−2. The device uses an indirect, wide‐band‐gap AlSb0.92As0.08 emitter and the transistor base is a 100‐A‐wide InAs layer.

Semiconductor memory device

Abstract: PURPOSE:To eliminate the unstable state of a potential due to alpha particles by forming a load with nonlinear impedance in a memory cell which are a couple of inverters equipped with loads and driver transistors (TR) and composed of an FF. CONSTITUTION:Diodes D1 and D2 are connected in parallel to load resistances R1 and R2 and then the V-I characteristic that the load impedance based upon the diode D1 or resistance R2 and diode D2 indicates is nonlinear. Therefore, the potential at a point (a), i.e. voltage applied to the resistance R2 drops be cause of an electron generated by alpha particles to prevent storage from being inverted owing to the bistability of the FF. Namely, the junction dielectric strength of the diode D2 is broken down the moment the voltage drop occurs, and a current path is opened between V1 and (a) to supply a voltage, thereby maintaining the potential at the point (a). Consequently, the unstableness of the potential due to alpha particles which occurs possibly to the storage node of the memory cell is eliminated.

A new charge pumping method of measuring Si‐SiO2 interface states

Abstract: A new method of measuring the density of band‐gap interface states at the Si‐SiO2 interface has been developed. This method is based on a charge pumping phenomenon and can be performed on a metal‐oxide‐semiconductor transistor structure without the need for Shockley–Hall–Read statistics. Although the method requires knowledge of the gate voltage‐surface potential relationship, the measured density of states is not as sensitive to either errors or fluctuations in this relationship as other more common techniques. Other advantages of this new method are that it can measure the density of interface states over most of the band gap, it is relatively simple to implement, and has a resolution comparable to either the conductance or deep level transient capacitance techniques. Applying the new method to a transistor with a channel length of 50 μm and a width of 25 μm, the density of interface states has been measured to within 80 meV of the conduction band.

Double implanted LDD transistor self-aligned with gate

Abstract: An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer. A lightly doped junction is aligned with the central alignment members and a heavily doped junction is aligned with the outboard alignment members.

A flash-erase EEPROM cell with an asymmetric source and drain structure

Abstract: A flash-erase EEPROM cell which consists of a single floating gate transistor is described. The cell is based on self-aligned double polysilicon stacked gate structure without a select transistor. It is programmed and erased by hot electrons at the drain edge similar to a UV-EPROM, and by Fowler-Nordheim tunneling of electrons from the floating gate to the source, respectively. An asymmetry in source and drain regions is introduced to enable fast program/erase operation. In addition, an n+concentration in the source region is optimized to achieve reproducible erasure, which is indispensable to avoid over-erasing problem. The optimized cell enables an erasing time of less than one millisecond with 12. 5 V on the source, and a scatter of erased Vth is almost negligible. Endurance and data retention characteristics is also adequate for implementation in memory chips. The small cell area of 9.3µm2is accomplished in a 0.8µm technology.

Transport and related properties of (Ga, Al)As/GaAs double heterostructure bipolar junction transistors

Abstract: This paper presents a study of the transport and related properties of GaAs double heterostructure bipolar junction transistors with GaAlAs emitters and collectors utilizing both graded and abrupt junctions. By studying the temperature dependence of current-voltage characteristics, the recombination mechanisms in the transition regions associated with the base-emitter, the base-collector junction, and the quasi-neutral base region have been quantitatively separated. The junction corresponding to growth of GaAs on GaAlAs is found to have higher nonradiative recombination. For abrupt junctions, it also shows a lower barrier for electron injection than does the GaAlAs/GaAs junction. At mid-1018cm-3base doping, the junctions show ideal emission/ diffusion transport at high currents, recombination-dominated transport in a medium current range, and transport with a characteristic energy greater than twice the thermal energy at very low currents. Due to excess recombination current in the devices, the offset voltage is shown to be sensitive to the ratio of emitter and collector junction areas. At low temperatures, transport across the injecting interface of abrupt devices is dominated by tunneling and in the quasi-neutral base by diffusion. The devices exhibit gain at temperatures as low as 4.2 K. The current gain below 77 K appears to be limited by radiative recombination lifetime, and at higher temperatures by nonradiative recombination and injection efficiency. Transistors with current gains of 300 to 500 have been achieved at small emitter dimensions of 1.6 µm × 4.0 µm and at current densities exceeding 105A . cm-2. At current densities of 100 A . cm-2, some of the transistors exhibited gains approaching 100. These devices had an offset voltage of less than 100 mV. Self-aligned devices have also been fabricated and show current gains of 20 to 50 at similar dimensions. In the inverted configuration, gains of up to 50 were observed for non-self-aligned transistors. The dependence of device Characteristics upon the structure indicates that surface effects are minimal. The negative resistance exhibited by these devices at high currents is shown to be due to temperature effects resuiting from the 10-µs or lower thermal time constants.

High voltage MOS transistors

Abstract: An insulated-gate, field-effect transistor and a double-sided, junction-gate field-effect transistor are connected in series on the same chip to form a high-voltage MOS transistor. An extended drain region is formed on top of a substrate of opposite conductivity-type material. A top layer of material having a conductivity-type opposite that of the extended drain and similar to that of the substrate is provided by ion-implantation through the same mask window as the extended drain region. This top layer covers only an intermediate portion of the extended drain which has ends contacting a silicon dioxide layer thereabove. The top layer is either connected to the substrate or left floating. Current flow through the extended drain region can be controlled by the substrate and the top layer, which act as gates providing field-effects for pinching off the extended drain region therebetween. A complementary pair of such high-voltage MOS transistors having opposite conductivity-type are provided on the same chip.

Power DMOS transistor with high speed body diode

Abstract: This inventive DMOS transistor provides faster turn-on switching than prior art lateral and vertical DMOS transistors in dV/dt situations and prevents catastrophic failures from high dV/dt's. The preferred embodiment of this improved device combines a Schottky diode with a vertical DMOS transistor, within the semiconductor structure itself, to form a device equivalent to a Schottky diode in parallel with an N channel vertical DMOS transistor. The Schottky diode effectively replaces the body diode of the transistor when forward biasing voltages are applied to the DMOS transistor. Thus, the body diode is never forward biased and there is no recovery time associated with the body diode. This speeds up the turn-on of the DMOS transistor since there are no minority carriers in the P-N junction body diode to recombine. Also, the parasitic bipolar junction transistor (BJT), formed by the source, body region, and drain, cannot turn on, thus preventing second breakdown of the BJT.

Heterojunction Bipolar Transistors for Microwave and Millimeter-Wave Integrated Circuits

Abstract: This paper reviews the present status of GaAIAs/GaAs HBT technology and projects the impact of these devices on microwave and millimeter-wave integrated circuits. Devices with F/sub max/ above 120 GHz are described. Differential amplifiers are shown to have offset voltages with standard deviation below 2 mV and voltage gain as high as 200 per stage. Breakdown voltiages (BV/sub CB0/) above 20 V are demonstrated. Frequency dividers operating above 20 GHz are described.