Showing papers on "Transistor published in 1990"

75-GHz f/sub T/ SiGe-base heterojunction bipolar transistors

Abstract: The fabrication of silicon heterojunction bipolar transistors which have a record unity-current-gain cutoff frequency (f/sub T/) of 75 GHz for a collector-base bias of 1 V, an intrinsic base sheet resistance (R/sub bi/) of 17 k Omega / Square Operator , and an emitter width of 0.9 mu m is discussed. This performance level, which represents an increase by almost a factor of 2 in the speed of a Si bipolar transistor, was achieved in a poly-emitter bipolar process by using SiGe for the base material. The germanium was graded in the 45-nm base to create a drift field of approximately 20 kV/cm, resulting in an intrinsic transit time of only 1.9 ps. >

Bistable dmd addressing circuit and method

Abstract: Bidirectional operation of the bistable DMD is preferred over unidirectional operation because it eliminates contrast degradation caused by duty-factor effects and permits lower voltage operation. However, bidirectional addressing requires either two drain lines and two transistors per pixel or one drain line and three transistors per pixel. An addressing scheme for bidirectional operation is disclosed that requires only a single drain line and one transistor per pixel. For megapixel DMDs used for high-definition television applications, this addressing scheme dramatically lowers the transistor count, with expected improvements in chip yield and cost.

The oligothiophene‐based field‐effect transistor: How it works and how to improve it

Abstract: Metal‐insulator‐semiconductor field‐effect transistors (MISFETs) based on organic semiconductors, mainly conjugated organic polymers and oligomers, have been reported recently. Unlike conventional MISFETs, these devices work through the modulation of an accumulation layer at the semiconductor‐insulator interface. A model for organic MISFETs, derived by changing the classical equations according to this particular operating mode is proposed. The ohmic current, parallel to the channel current, and due to the nonrectifying character of source and drain contacts, has also been taken into account. According to this model, the characteristics of these organic devices can be improved by decreasing the doping level and the thickness of the semiconducting layer. Simple rules are deduced and applied to devices based on α‐conjugated sexithienyl.

Method and apparatus for calibration and controlling multiple heaters

Abstract: Multiple heaters are calibrated and controlled by a microcomputer, and a multiplexer for this system. The heaters are sequentially sampled and resistance calculated from voltage and current measurements. The operator enters a temperature for the calculated resistance to establish a calibrated resistance value. During run, the computer energizes and samples each heater to calculate its resistance. The calculated resistance if divided by the calibrated resistance to determine a resistance ratio. A look-up table is stored in the computer having resistance ratios for corresponding temperature. The computer compares the calculated ratio to that of the look-up table to determine actual heater temperatures. Based upon heater temperatures, the computer controls energization of the heaters until set points are achieved. Negative temperature coefficient and positive temperature coefficient transistors and semiconductors can be utilized.

A voltage-controllable linear MOS transconductor using bias offset technique

Abstract: A linear large-signal MOS transconductor with the gain adjustable linearly by a voltage is described. A perfect linear transfer characteristic is obtained by two cross-coupled differential transistor pairs operating in saturation pairwise at unequal bias, offering offset-free operation, with both differential or single-ended input and differential output. Single-ended output is achievable by use of a current mirror. The nonlinearity caused by mobility reduction, channel-length modulation, mismatch, etc. is discussed. A test circuit with transconductance of 6.25 mu mho has been built with 3- mu m MOS components, and a linearity error of less than +or-1% was measured for an input voltage range from -4 to 4 V. >

An MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers

Abstract: An MOS four-quadrant analog multiplier is described. It is based on the square-law dependence of the MOS-transistor drain current on the gate-to-source voltage in the saturation region. One input is applied to the gate directly while the other input is applied to the source through a source-follower buffer stage. The circuit is realized with only 12 MOS transistors and two resistors. The circuit has been fabricated using a metal-gate NMOS process which has separate p-wells to eliminate the substrate bias effect. The multiplier achieves less than 0.45% nonlinearity when the input voltage range is 40% of the supply voltages, and it achieves a -3-dB bandwidth of 30 MHz. The total harmonic distortion is less than 0.6%. The power consumption and chip size are 8 mW and 1.2 mm/sup 2/, respectively. The second-order effects for this type of multiplier are considered in detail. >

In‐plane‐gated quantum wire transistor fabricated with directly written focused ion beams

Abstract: A new unipolar electronic device with a quasi‐one‐dimensional (1D) tunable carrier channel defined by directly written focused ion beams has been fabricated and characterized. Special features of the device are simple and rapid fabrication in one single technology step, inherent self‐alignment, and linear instead of planar gates with very low capacitances. High integration as well as ultrahigh speed operation in logical and linear applications are feasible. The striking new aspect of this in‐plane‐gate structure is that the confining electric field is parallel to the two‐dimensional electron gas, and the distorted, insulating region serves as a dielectric. Ballistic 1D transport is observed at low temperatures, and field‐effect transistor operation of the device is demonstrated up to room temperature.

Method of fabricating an high-performance insulated-gate field-effect transistor

Abstract: An improved device fabrication method and transistor structure 36 provide shallow, heavily doped, source/drain junction regions 64 and a uniformly doped lower gate region 50 having a high concentration of dopants efficiently distributed near the gate electrode/gate interface 51. The gate, source, and drain terminals of transistor 36 may be interconnected to other neighboring or remote devices through the use of reacted refractory metal interconnect segments 98 and 100. Transistor structure 36 of the present invention may be constructed in an elevated source/drain format to include elevated source/drain junction regions 87 which may be fabricated simultaneous with a primary upper gate electrode region 88. This elevated source/drain junction feature is provided without added device processing complexity.

Modeling and simulation of interconnection delays and crosstalks in high-speed integrated circuits

Abstract: A computer model for n parallel microstrip lines is developed for circuit simulation. This model for the lossy transmission line system can be readily implemented into circuit simulators and can accurately simulate the delay and crosstalk effects of interconnects in high-speed integrated circuits. Modal analysis is applied to decouple the n-coupled-line system into n independent lines, and the characteristic solutions of telegraph equations are represented by a set of simple time-varying equivalent circuits. The model has been implemented in a general-purpose circuit simulator, iSMILE, which is compatible with SPICE. Simulation results on propagation delay times and crosstalk are presented for high-speed GaAs HEMT (high-electron-mobility transistor) integrated circuits. >

EPROM virtual ground array

Abstract: An electrically programmable read only memory contains alternating metal bit lines and diffused bit lines. Each diffused bit line is broken into a plurality of segments. Each of the segments of the diffused bit line comprises a virtual source. A multiplicity of floating gate transistors are arranged in rows and columns. The floating gate transistors in each column are divided into M groups of N floating gate transistors each. The floating gate transistors in the n th and the (n+1) th columns, where n is an odd integer given by 1≦n≦N and (N+1) is the maximum number of columns in the array are connected to the segments of one diffused bit line placed between the n th and the (n+1) th columns. At least one first transfer transistor is arranged to connect one segment comprising a virtual source to a first metal bit line. The first metal bit line functions as the source for the N floating gate transistors in the (n+1) th column connected to said one segment. At least one second transfer transistor connects the same one segment comprising a virtual source to a second metal bit line. The second metal bit line functions as a source for the N floating gate transistors in the n th column connected to said one segment. The removal of each select transistor from the cell where it previously resided in series with its corresponding floating gate transistor, and the combining of a plurality of select transistors into one select transistor substantially reduces the area taken by each memory cell in the array.

Monte Carlo analysis of semiconductor devices: the DAMOCLES program

Abstract: The behavior of small semiconductor devices is simulated using an advanced Monte Carlo carrier transport model. The model improves upon the state of the art by including the full band structure of the semiconductor, by using scattering rates computed consistently with the band structure, and by accounting for both long- and short-range interactions between carriers. It is sufficiently flexible to describe both unipolar and bipolar device operation, for a variety of semiconductor materials and device structures. Various results obtained with the associated DAMOCLES program for n- and p-channel Si MOSFETs, GaAs MESFETs, and Si bipolar junction transistors are presented.

A fully depleted lean-channel transistor (DELTA)-a novel vertical ultrathin SOI MOSFET

Abstract: A fully depleted lean-channel transistor (DELTA) that has a gate with a vertical ultrathin SOI structure is reported. In the deep submicrometer region, selective oxidation is useful in realizing SOI isolation. It provides high crystalline quality, as good as that of conventional bulk single-crystal devices. Using experiments and three-dimensional simulation, it was shown that the gate structure has effective channel controllability and its vertical ultrathin SOI structure provides superior device characteristics. >

Flat-cell read-only-memory integrated circuit

Abstract: A flat-cell ROM array reduces the number of block select transistors utilized, allows for the layout of straight metal lines, while sharing the metal lines between even and odd banks, and achieves very high density and high performance. Parallel buried diffusion regions are deposited in the substrate. A gate oxide is laid over the substrate. A plurality of polysilicon word lines are laid over the gate oxide perpendicular to the buried diffusion regions, so that the areas between the respective pairs of buried diffusion regions and under the polysilicon word lines, form columns of flat cell field effect transistors. An insulating layer is laid over the polysilicon word lines, and a plurality of metal bit lines and virtual ground lines is deposited. These metal lines are shared by even and odd columns of field effect transistors. Access to the metal lines is made through a plurality of LOCOS block select transistors connected to every other buried diffusion bit line. The alternate buried diffusion bit lines are connected through either a buried diffusion region to its left or a buried diffusion region to its right to the metal lines, by means of bank right and left select transistors.

On charge injection in analog MOS switches and dummy switch compensation techniques

Abstract: Theoretical and experimental results of the clock-feedthrough phenomenon (charge injection) in sample-and-hold circuits using minimum feature size transistors of a self-aligned 3- mu m CMOS technology are compared. The lumped RC model of the conductive channel has been used and verified in different switch configurations, including variable input voltages. Special emphasis is laid on the feasibility and limits of charge cancellation techniques using dummy switch designs. >

Self-aligned overlap MOSFET and method of fabrication

Abstract: A high speed submicron transistor which exhibits a high immunity to hot electron degradation and is viable for VLSI manufacturing. An inner gate member is formed on a p type substrate. A first source region and a first drain region are disposed in the p type substrate in alignment with the inner gate member for forming a lightly doped region. A conductive spacer is formed adjacent to and is coupled to each side of the inner gate member on the gate oxide layer for forming a gate member which overlaps the lightly doped region. A second source region and a second drain region are disposed in the first source region and first drain regions, respectively, self-aligned with the outer edges of the conductive spacers to form source and drain contact areas.

The multistable charge-controlled memory effect in SOI MOS transistors at low temperatures

Abstract: A phenomenon called the MCCM (multistable charge-controlled memory) effect is observed in SOI MOS transistors working at lot temperatures. This MCCM effect essentially results in a controllable setting of the transistor threshold voltage by applying adequate voltage pulses (or up-down voltage sweeps) to one or more electrodes of the structure. A change in threshold voltage of several volts can be obtained. Stability on the order of hours and longer, depending on temperature and operational conditions, is observed. The physics behind the MCCM effect is discussed, and a simple analytical model is proposed. Some new applications based on the MCCM effect are briefly highlighted. >

Output buffer for reducing switching induced noise

Abstract: An output buffer for reducing switching induced noise in high speed integrated circuit devices incorporates a relatively small current carrying capacity secondary pulldown transistor (N1) element with the current path first and second terminal leads coupled in parallel with the current path first and second terminal leads of the primary pulldown transistor element. A separate pulldown (R1) delay resistance element of selected value is coupled in series between the control terminal leads of the secondary (N1) and primary (N3) pulldown transistor elements. The secondary pulldown transistor (N1) element control terminal lead is coupled in the output buffer to receive a signal propagating through the output buffer before the primary pulldown transistor (N3) element control terminal lead. A relatively small discharge current is therefore initiated from the output before turn on of the relatively large discharge current of the primary pulldown (N3) transistor element. The separate pulldown delay resistance (R1) element delays turn on of the primary pulldown transistor (N3) element a specified time delay after turn on of the secondary pulldown transistor (N1) element during transition from high to low potential at the output. As result ground bounce is divided into two spikes and the ground rise in potential is constrained to approximately one half that of conventional ground bounce levels. A secondary pullup transistor element with associated noise reduction components can similarly be used on the supply side to reduce Vcc droop.

Transistor provided with strained germanium layer

Abstract: A transistor having a high carrier mobility and suited for a high-speed operation can be formed by utilizing a fact that the carrier mobility in a strained germanium layer (2, 21) is large. A strain control layer (31, 31A) is provided beneath the germanium layer (2, 21) to impose a compressive strain on the germanium layer (2, 21), and the composition of the strain control layer (31, 31A) in a predetermined range is used to generate the compressive strain surely.

Programmable interconnect architecture having interconnects disposed above function modules

Abstract: A user-configurable circuit architecture includes a two dimensional array of functional circuit modules disposed within a semiconductor substrate. A first interconnect layer disposed above and insulated from the semiconductor substrate contains a plurality of conductors and is used for internal connections within the functional circuit modules. A second interconnect layer disposed above and insulated from the first interconnect layer contains a plurality of segmented tracks of conductors running in a first direction and is used to interconnect functional circuit module inputs and outputs. A third interconnect layer disposed above and insulated from the second interconnect layer contains a plurality of segmented tracks of conductors running in a second direction, some of the segments of conductors forming intersections with ones of the segments of the conductors in the second interconnect layer, and is used to interconnect functional circuit module inputs and outputs to implement the desired applications. A plurality of user-configurable interconnect elements are placed directly between the second the third interconnect layers at the intersections of selected segments of the segmented conductors in the second and third interconnect layers. More user-configurable interconnect elements are located between adjacent segments of the segmented conductors in both the second and third interconnect layers. Pass transistors located in the semiconductor substrate in between the functional circuit modules are connected between adjacent segments in both the second and third interconnect layers and between selected intersecting segments in the second and third interconnect layers.

High density SRAM circuit with ratio independent memory cells

Abstract: Briefly, a high density, static, random access memory (SRAM) circuit with ratio independent memory cells employs a number (plurality) of (4T-2R) or (6T) type SRAM cells and a regenerative sense amplifier. Each of the SRAM cells of the present invention differs from corresponding, prior art type SRAM cells in that the SRAM cells of the present invention each include transistors of similar size (channel width).

The DC characteristics of GaAs/AlGaAs heterojunction bipolar transistors with application to device modeling

Abstract: A complete DC model for the heterojunction bipolar transistor (HBT) is presented. The DC characteristics of the HBT are compared with the Ebers-Moll (EM) model used by conventional bipolar junction transistors (BJTs) and implemented in simulation and modeling programs. It is shown that although the details of HBT operation can differ markedly from those of a BJT, a model and a parameter extraction technique can be developed which have physical meaning and are exactly compatible with the EM models widely used for BJTs. Device I-V measurements at 77 and 300 K are used to analyze the HBT physical device performance in the context of an EM model. A technique is developed to extract the device base, emitter, and collector series resistances directly from the measured I-V data without requiring an ideal exp(qV/sub be//kT) base current as reference. Accuracies of the extracted series resistances are assessed. AC parameters of HBT are calculated numerically from the physical device structure. For modeling purposes, these parameters are shown to be comparable with those of conventional BJTs. >

High efficiency charge pump circuit

Abstract: An integrated circuit includes a charge pump to provide current at a potential which is greater than a supply potential. An oscillator provides an output to a pair of capacitors. Each capacitor is bypassed respectively by one of a pair of clamp circuits. An output transistor is gated by one of the clamp circuits to maintain a continuous output at an elevated potential, while reducing power loss caused by impedances within the charge pump circuit. By using the charge pump as a source of elevated potential, the circuit layout of the DRAM array is simplified and the potential boosting circuitry can be locataed outside of the array, on the periphery of the integrated circuit. When used with an integrated circuit device, such as a DRAM, the current from the charge pump may be supplied to nodes on isolation devices and nodes on word lines, thereby improving the performance of the DRAM without substantially changing the circuit configuration of the DRAM array.

Semiconductor integrated circuit device

Abstract: PURPOSE:To restrain a leakage current from being generated and to easily execute a testing operation to measure a very small leakage current intrinsically generated in an IC by a method wherein a resistance element is cut off arbitrarily and electrically by using a bidirectional buffer. CONSTITUTION:When an input/output control terminal 2 is at H, a buffer 5 for output use becomes a nonconducting state; a signal from an internal signal input terminal 1 is not transferred to an external signal input/output terminal 4. At this time, a signal at H from the terminal 2 is input to a signal inverter 2a and becomes at L; it is input to a gate part of a P-channel MOS transistor 7 as a first semiconductor forming a pull-up resistor. At this stage, the transistor 7 becomes a conducting state when a gate potential is at L and a part between other two terminals has a certain resistance value; when the gate potential is at H, the part between the other two terminals has an infinitely large resistance value and becomes a nonconducting state. The transistor 7 to which the L has been input becomes a conducting state; when the signal from the terminal 4 is neither H nor L and in a high resistance state, it passes through the transistor 7 and an input buffer 6 from a power supply 8; the H is transferred to an internal signal output terminal 3.

Regulated cascode switched-current memory cell

Abstract: A new sampled-current signal processing cell is presented. When operated with its memory transistor in saturation it can be designed with high signal swing and low supply voltage. Alternatively, with the addition of a simple clock circuit to produce nearly constant switch charge injection, the memory transistor may be operated in nonsaturation to improve accuracy.

Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits

Abstract: A linearity study of the propagation delay of bipolar circuits carried out using a SPICE program is discussed. It is found that the behavior of the propagation delay is quite linear, and therefore analytical propagation delay expressions for ECL and CML circuits are derived using a sensitivity analysis. The validity of the expressions is checked by SPICE simulations and comparison to experimental data published in the literature, and agreement is within 5%. The expressions indicate that there is an optimum value of load resistance for logic circuits in order to achieve a minimum propagation delay. For present technology, logic circuits for silicon transistors can operate at the current density corresponding to maximum f/sub T/, and logic circuits for AlGaAs-GaAs heterojunction bipolar transistors (HBTs) should operate at a current density lower than that of maximum f/sub T/. Therefore, it is important to increase the collector current density of maximum f/sub T/ for silicon bipolar circuits, or to decrease the base resistance R/sub B/ and the forward transit time tau /sub F/ for HBT circuits, in order to increase the circuit speed. >

Optimization of RESURF LDMOS transistors: an analytical approach

Abstract: The high-voltage behavior of the lateral double-diffused MOS transistor (LDMOST) is investigated using an analytical approach. Expressions for the breakdown voltage of an LDMOST fabricated on both thick and thin epitaxial layers are derived. On the basis of this information, a strategy for the optimization of RESURF LDMOSTs is developed. The accuracy of the analytical expressions is verified by comparison with two-dimensional simulation results. >

Vertical transistor device fabricated with semiconductor regrowth

Abstract: A vertical transistor device is characterized by active regions vertically separated by a narrower control region. The control region is defined by conducting layer extensions which extend into a groove within which semiconductor material is regrown during device fabrication. The device is further characterized by regions of isolating material, located horizontally adjacent to the active regions, said isolating material serving to reduce parasitic capacitance and improve thermal distribution within the device, thereby improving frequency and power performance.

Esd protection for soi circuit

Abstract: PURPOSE: To make a protective circuit decreasing the thermal dissipation requirements of a thin semiconductor layer in SOI structure making feasible of the easy manufacture and the compatibility with another transistor on a chip by a method wherein a semiconductor body specifying a conductive channel between a semiconductor drain and a semiconductor source is provided with a FET formed of an SOI structure CONSTITUTION: An electrostatic discharge(ESD) protective device for SOI circuit is composed of an SOI structure containing a semiconductor material 20 conforming to the formation of a transistor therein, a conductor transmitting the signals relating to this transistor circuit and a field effect transistor 14 connected to this conductor conducting an ESD current and provided with a semiconductor body specifying a conductive channel 26 between a semiconductor drain 24 and source 22 while the semiconductor body contains the FET 14 formed of the SOI structure For example, the bulk material 26 in the conductive channel of the FET 14 is electrically separated from the residual semiconductor material 20 while a contact for connecting to the source region 22 is provided on a gateconductor 30

Experimental confirmation of a new semiconductor detector principle

Abstract: A new detector-amplification principle proposed by Kemmer and Lutz in 1986 has been experimentally verified. Outstanding features of this device are the built-in amplification, the signal charge storage capability and the possibility of repeated non-destructive readout. The device was used for detection of X-rays from a 241 Am and from Am and from an 55 Fe source. Very low noise figures ( σ =30 electrons corresponding to an energy resolution of FWHM = 250 eV at 6 keV energy) have been obtained at room temperature. Various applications of the structure either as detector or as purely electronic element are possible. One of the most intriguing is the use as a pixel detector with random access non-destructive readout. This device may be operated at very low power, as only reading (of one single pixel at a time), not storing, consumes power. Further options of the device are fast clearing, gating and variation of the pixel size during readout. The latter property can be used to drastically increase the readout speed compared to more standard two dimensional devices as e.g. CCD detectors, as one may restrict the high density readout to regions of interest determined beforehand by a coarse scan of the whole detector. An alternative use of the device is as an analog or digital memory, or as a simple transistor with drastically reduced parasitic capacitances. Possible further developments are the combination with a novel three dimensional analog storage device which may either be used as a detector with built-in storage of several charge images or as a three dimensional analog memory.

A ratio-independent algorithmic analog-to-digital converter combining current mode and dynamic techniques

Abstract: An algorithmic analog-to-digital converter (ADC) that combines current mode and dynamic techniques is presented. The converter does not rely on high-gain amplifiers or well-matched components to achieve high resolution and is inherently insensitive to the amplifier's offset voltage. An analysis of the converter's limitations indicates that the resolution of practical circuits will be limited by the switch-induced charge injection. Ultimately, however, the kT/C noise leads to an area/resolution tradeoff and the transistor's thermal noise leads to a speed/power tradeoff. A prototype fabricated using a 3- mu m CMOS process achieved 10-bit resolution at a sampling rate of 25 kHz on an area of only 0.18 mm/sup 2/. >