Showing papers on "Transistor published in 1993"

High electron mobility transistor based on a GaN‐AlxGa1−xN heterojunction

Abstract: In this letter we report the fabrication and dc characterization of a high electron mobility transistor (HEMT) based on a n‐GaN‐Al0.14Ga0.86N heterojunction. The conduction in our low pressure metalorganic chemical vapor deposited heterostructure is dominated by two‐dimensional electron gas at the heterostructure interface. HEMT devices were fabricated on ion‐implant isolated mesas using Ti/Au for the source drain ohmic and TiW for the gate Schottky. For a device with a 4 μm gate length (10 μm channel opening, i.e., source‐drain separation), a transconductance of 28 mS/mm at 300 K and 46 mS/mm at 77 K was obtained at +0.5 V gate bias. Complete pinchoff was observed for a −6 V gate bias.

Membrane dielectric isolation ic fabrication

Abstract: General purpose methods for the fabrication of integrated circuits (24, 26, 28,... 30) from flexible membranes (20, 36) formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices (24, 26, 38,... 30) are formed in a semiconductor layer of the membrane (36). The semiconductor membrane layer (36) is initially formed from a substrate (18) of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multichip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Method for forming a film and method for manufacturing a thin film transistor

Abstract: A crystal silicon film deposited on an insulating film made of a binary system material or a binary system semiconductor film formed by an atomic layer deposition method has a grain as large as approximately 200 nm. Thus, the mobility of carriers is increased. The crystal silicon thereof is grown within a temperature range of 250° C. to 400° C. Accordingly, when a planar type thin film transistor, an inverted stagger type thin film transistor or a stagger type thin film transistor is formed using crystal silicon formed on these films made of a binary system material, transistor characteristics thereof are improved. Further, when an impurity containing silicon film is formed by a chemical vapor deposition method between a source electrode and a drain electrode of a thin film transistor and a silicon film connected to these electrodes, and a flow rate of impurity containing gas is regulated so that impurity density becomes larger as approaching to the source electrode and the drain electrode, a leakage current in an OFF-state of the transistor is reduced. Since the impurity containing silicon film is grown by a chemical vapor deposition method in this case, the impurity density thereof can be controlled easily and the control accuracy is also improved.

A 1.5-ns 32-b CMOS ALU in double pass-transistor logic

Abstract: Describes circuit techniques for fabricating a high-speed adder using pass-transistor logic. Double pass-transistor logic (DPL) is shown to improve circuit performance at reduced supply voltage. Its symmetrical arrangement and double-transmission characteristics improve the gate speed without increasing the input capacitance. A carry propagation circuit technique called conditional carry selection (CCS) is shown to resolve the problem of series-connected pass transistors in the carry propagation path. By combining these techniques, the addition time of a 32-b ALU can be reduced by 30% from that of an ordinary CMOS ALU. A 32-b ALU test chip is fabricated in 0.25- mu m CMOS technology using these circuit techniques and is capable of an addition time of 1.5 ns at a supply voltage of 2.5 V. >

A 4500 V injection enhanced insulated gate bipolar transistor (IEGT) operating in a mode similar to a thyristor

Abstract: This paper proposes a new MOS-gate transistor structure (IEGT) for the first time, that realizes enhanced electron injection so that the carrier distribution takes a form similar to that of a thyristor and a low forward voltage drop is attained even for 4500 V devices. A developed simple analytical one dimensional model can predict a sufficiently accurate current voltage curve and clarifies a new design criterion for IEGT operation. A fabricated 4500 V IEGT realized a 2.5 V forward voltage drop at 100 A/cm/sup 2/. The IEGT had a current density over ten times that of conventional trench gate IGBT at 2.5 V forward voltage drop. An operation mode of IEGT has been theoretically and experimentally confirmed. >

Polythienylenevinylene thin‐film transistor with high carrier mobility

Abstract: A thin‐film transistor (TFT) with high carrier mobility has been fabricated using precursor‐route poly(2,5‐thienylenevinylene) (PTV) as semiconductor. The carrier mobility has been determined to be 0.22 cm2/V s, which is in the same level of that of amorphous silicon TFT. It has also been made clear that the carrier mobility is linearly proportional to the conversion ratio from the insulated precursor polymer to π‐conjugated PTV. The π‐conjugation length is crucial to obtain high carrier mobility in π‐conjugated polymer TFT.

Neuron MOS binary-logic integrated circuits. I. Design fundamentals and soft-hardware-logic circuit implementation

Abstract: Described are the fundamental design principles for binary-logic circuits using a highly functional device called the neuron MOS transistor ( nu MOS), a single MOS transistor simulating the function of biological neurons. To facilitate logic design employing this transistor, a graphical technique called the floating-gate potential diagram has been developed. It is shown that any Boolean functions can be generated using a common circuit configuration of two-stage nu MOS inverters. One of the most striking features of nu MOS binary-logic application is the realization of a so-called soft hardware logic circuit. The circuit can be made to represent any logic function (AND, OR, NAND, NOR, exclusive-NOR, exclusive-OR, etc.) by adjusting external control signals without any modifications in its hardware configuration. The circuit allows real-time reconfigurable systems to be built. Test circuits were fabricated by a double-polysilicon CMOS process and their operation was experimentally verified. >

Thin-film transistor and a liquid crystal matrix display device using thin-film transistors of this type

Abstract: A thin-film transistor comprises a gate electrode formed on a glass substrate, a gate insulating film formed essentially over an entire surface of the substrate to cover the gate electrode, a non-single-crystal silicon semiconductor film placed on the gate insulating film to cover the gate electrode; and a drain electrode and a source electrode spaced a specified distance apart on the semiconductor film and electrically connected to the semiconductor film so as to form the channel region of the transistor. The gate electrode is made of titanium-containing aluminum.

Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's

Abstract: A switched-source-impedance (SSI) CMOS circuit is proposed as a means of reducing the exponential increase of subthreshold current with threshold-voltage scaling. Inserting a switched impedance at the source of a MOS transistor reduces the standby subthreshold current of giga-scale LSI's operating at room temperature by three to four orders of magnitude and suppresses the current variation caused by threshold-voltage and temperature fluctuations. The scheme is applicable to any combinational and sequential CMOS logic circuits as long as their standby node voltages are predictable. The standby current of a 16-Gb DRAM is expected to be reduced from 1.1 A to 0.29 mA using this scheme. Hence, battery backup of giga-scale LSI's will be possible even at room temperature and above. >

Charge separation in bipolar transistors

Abstract: The effects of the midgap-level interface trap density and net oxide charge on the total-dose gain degradation of a bipolar transistor are separately identified. The superlinear dose dependence of the excess base current is explained.

A pulsewidth-modulated inverter with parallel connected transistors using current-sharing reactors

Abstract: A technique for parallel connection of transistors by using current-sharing reactors for the pulse-width-modulated (PWM) transistor inverter is reported. The technique not only increases current capacity, but also decreases the output harmonic contents. The output voltage waveforms of the proposed inverter have certain voltage levels during their half cycles, and thus it is anticipated that it will be difficult to analyze the output harmonics. For such waveforms, a frequency analysis approach is described, and its results are verified by experiments. >

Vertical field effect transistor and diode

Abstract: A vertical field effect transistor (1400) and diode (1450) formed on a single III-V substrate. The diode cathode and the transistor drain or collector may be formed in a common layer (1408).

Semiconductor integrated circuit incorporated with substrate bias control circuit

Abstract: The semiconductor IC according to this invention comprises an internal circuit including a plurality of transistors formed on a P-type or an N-type substrate (or a well) which carries out a prescribed signal processing operation during the time of operation mode, a standby detection circuit which generates a standby detection signal of active level by detecting standby mode, a bias potential generating circuit which generates a forward bias potential from the substrate (well) of the transistor to the source electrode, and a switching circuit which supplies to the substrate (well) the potential of the source electrode and the bias potential in response to the active level and the inactive level, respectively, of the standby detection signal. At the time of the operation mode, a high speed operation is secured by bringing the transistors to a low threshold voltage by receiving the supply of the bias potential, while at the time of the standby mode, the generation of malfunctions and defective data holding are prevented and the power consumption is saved by raising the threshold voltage of the transistors through a halt of supply of the bias voltage to the substrate (well).

Linear networks based on transistors

Abstract: Any network of linear resistors in which only currents are considered can be implemented solely by transistors. Values are controlled by sizes of transistors in the general case, and by their gate voltage for weak inversion. The voltage range is compressed and the concept of virtual ground facilitates the extraction of any current flowing to ground. An edge-detecting silicon retina is described as an example of application.

Method for forming an insulated gate field effect transistor

Abstract: In an inverted stagger type thin-film transistor, the preparing process thereof can be simplified, and the unevenness of the thin film transistor prepared thereby can be reduced That is, disclosed is a preparing method which comprises selectively doping a semiconductor on a gate insulating film with an impurity to form source, drain, and channel forming regions, and conducting a laser annealing to them, or a preparing method which comprises selectively doping the semiconductor region with an impurity by a laser doping method

On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications. I. Transistor DC design considerations

Abstract: The DC design considerations associated with optimizing epitaxial Si- and SiGe-base bipolar transistors for the 77-K environment are examined in detail. Transistors and circuits were fabricated using four different vertical profiles, three with a graded-bandgap SiGe base, and one with a Si base for comparison. All four epitaxial-base profiles yield transistors with DC properties suitable for high-speed logic applications in the 77-K environment. The differences between the low-temperature DC characteristics of Si and SiGe transistors are highlighted both theoretically and experimentally. A performance tradeoff associated with the use of an intrinsic spacer layer to reduce parasitic leakage at low temperatures and the consequent base resistance degradation due to enhanced carrier freeze-out is identified. Evidence that a collector-base heterojunction barrier effect severely degrades the current drive and transconductance of SiGe-base transistors operating at low temperatures is provided. >

ESD protection circuit

Abstract: An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure Several splitting structures are disclosed, each combining a resistor in series with each segment to distribute current evenly The transistor takes advantage of the snap-back effect to increase current carrying capacity Layout positions metal contacts away from regions of highest energy dissipation Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels Critical corners are rounded rather than sharp Certain P-type channel stop implants are positioned away from nearby N-regions to increase breakdown voltage

Non-volatile random access memory cell constructed of silicon carbide

Abstract: A non-volatile random access memory (NVRAM) cell that utilizes a simple, single-transistor DRAM cell configuration. The present NVRAM employs an enhancement mode nMOS transistor made as an accumulation mode transistor. The transistor has an n-type silicon carbide channel layer on a p-type silicon carbide buffer layer, with the channel and buffer layers being on a highly resistive silicon carbide substrate. The transistor also has n+ source and drain contact regions on the channel layer. A polysilicon/oxide/metal capacitor is preferably used which has a very low leakage current. Furthermore, this type of capacitor can be stacked on top of the transistor to save area and achieve high cell density. It is preferred to use a non-reentrant (edgeless) gate transistor structure to further reduce edge effects.

An improved calibration technique for on-wafer large-signal transistor characterization

Abstract: The on-wafer measurement of complex quantities and absolute power levels of active devices is truly significant for nonlinear device characterization and modeling. An original procedure, which allows one to perform both the vector and the power calibrations at the RF wafer probe tips used for on-wafer measurement of two-port devices, is presented. The measurement system is based on an automatic vector network analyzer with coaxial directional couplers and RF coplanar wafer probes. A new error model of the dual directional coupler, which samples the power waves traveling at device output, allows one to take advantage of the coaxial section at the output of the measuring system for calibrating the power level up to the on-wafer probe tips. >

Insulated-gate field-effect transistor structure and method

Abstract: An insulated-gate field-effect transistor 10 is formed on a semiconductor substrate 8. The source 12 and/or drain 20 junction region comprises a heavily doped region 14 (22), a non-overlapped lightly doped region 16 (24), and an overlapped lightly doped region 18 (26). The doping concentration and junction depth of the overlapped 18 and non-overlapped 16 lightly doped regions may be controlled and optimized independently. An insulating layer 50 is formed over a channel region 28 which separates the source 12 and drain 20, and also over the overlapped portions of the source 18 and drain 26. A gate 42 is formed over the insulating layer 50. Two exemplary methods of fabrication are disclosed in detail herein as well as other systems and methods.

Active matrix electroluminescent display and method of operation

Abstract: An active matrix electroluminescent display (AMELD) having an improved light emitting efficiency and methods of operating the AMELD to produce gray scale operation are disclosed. The invention is an AMELD comprising a plurality of pixels, each pixel (42) including a first transistor (44) having its gate connected to a select line (46), its source connected to a data line (48) and its drain connected to the gate of a second transistor (50), the second transistor (50) having its source connected to the data line (48) and its drain connected to a first electrode of an electroluminescent (EL) cell. The EL cell's second electrode is connected to alternating high voltage source (59). A method for producing gray scale performance including the step of varying the length of time the second transistor is on while the alternating voltage is applied to the EL cell is also disclosed.

Method for fabricating monolithic chip containing integrated circuitry and suspended microstructure

Abstract: The invention comprises a method for fabricating a monolithic chip containing integrated circuitry as well as a suspended polysilicon microstructure. The inventive method comprises 67 processes which are further broken down into approximately 330 steps. The processes and their arrangement allow for compatible fabrication of transistor circuitry and the suspended polysilicon microstructure on the same chip.

High-efficient class F GaAs FET amplifiers operating with very low bias voltages for use in mobile telephones at 1.75 GHz

Abstract: High-efficiency class F GaAs power FET amplifiers working with a very low drain bias voltage of 3 V, for use in portable telephones, are reported. The transistor used has an optimized gate periphery of 2000 mm and a gate length of 0.7 mu m. Under class F operation with a drain voltage of 3 V, it has demonstrated an output power of 24.5 dBm with 71% of power-added efficiency at the operating frequency of 1.75 GHz. Output harmonic levels lower than -25 dBc have been measured. The results obtained present the state of the art as published for low-bias-voltage, low-power-consumption amplifiers for mobile telephone systems. >

Batch fabrication and operation of GaAs-Al/sub x/Ga/sub 1-x/As field-effect transistor-self-electrooptic effect device (FET-SEED) smart pixel arrays

Abstract: The structure, processing, and performance of arrays of integrated field-effect transistor-self-electrooptic effects devices (FET-SEEDs) consisting of doped-channel field-effect transistors, multiple quantum-well (MQW) modulators, and p-i-n MQW detectors are discussed. The performance of the FETs and SEEDs such as g/sub m/ and contrast, is equivalent to that obtained when they are made separately. Typical values are g/sub m/=80 mS/mm and contrast of 3. The largest arrays contain 128 circuits. The circuits operate at speeds as fast as 500 Mb/s, with optical input switching energy of approximately=400 fJ. At 170 Mb/s, the required optical input switching energy is approximately=70 fJ. This optical energy is at least a factor of 20 less than for symmetric SEEDs (S-SEEDs) with the same optical window sizes. Hence, FET-SEEDs provide superior performance compared to conventional S-SEEDs. >

Apparatus and method for providing AC isolation while supplying DC power

Abstract: A source power coupler for coupling a power source to a first transmission line and a second transmission line. DC power from the power source is conducted by the source power coupler to the first and the second transmission lines while AC signals on the first and the second transmission lines are isolated from the power source by the source power coupler. The source power coupler is comprised of an operational amplifier having a non-inverting input and an inverting input. The gate of a transistor is coupled to an output of the operational amplifier. The transistor's drain is coupled to one of the transmission lines. And the transistor's source is coupled to the inverting input of the op-amp. Thereby, a control loop is formed, which provides an AC impedance between the power source and one of the transmission lines. A resistor is coupled between the source of the transistor and the power source, and a capacitor is coupled between the non-inverting input of the op-amp and the power source. Another resistor is coupled between the non-inverting input of the op-amp one of the transmission lines. The capacitor and the second resistor provide a second control loop. This control loop provides a constant direct current voltage across the transistor.

High frequency analog transistors, method of fabrication and circuit implementation

Abstract: A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.

DC-DC converter operable in an asyncronous or syncronous or linear mode

Abstract: A DC-DC converter is provided which is operable to drive a reactive circuit (10) that includes both a series inductor (12) and a capacitor (14) disposed between the output node and ground. The DC-DC converter includes two switches, a transistor switch (20) connected between a positive supply and an input node (16) and a second transistor (28) connected between the node (16) and ground. In one mode of operation, the transistors (20) and (28) operate in an asynchronous regulation mode with clock signals provided to the gates thereof. In a second asynchronous mode of operation, transistor (28) is turned off and replaced by its junction isolation diode (48). The transistor (20) is driven by a clock signal in accordance with an asynchronous regulation mode of operation. In a third mode of operation, the modified asynchronous duty cycle to the gate of transistor (20) is altered. In a fourth mode of operation, a linear regulation circuit (51) and an internal regulation transistor (49) are provided which are connected to the node (16) through a resistor (44). During this mode of operation, transistors (20) and (28) are turned off. By sensing current to the input of transistor (20) during the first, second and third modes of operation, a determination can be made for switching between the first three modes of operation and from the third mode of operation to the fourth mode of operation. The voltage on the input node (16) is sensed through resistor (44) to make a decision to switch from the first to the second mode of operation. At any time, the output voltage on node (18) can be sensed by a switching regulator control circuit (26) to determine that the regulation provided thereby falls below a predetermined regulation threshold and then the asynchronous mode of operation selected.

Simulating single-event burnout of n-channel power MOSFET's

Abstract: Single-event burnout of power MOSFETs is a sudden catastrophic failure mechanism that is initiated by the passage of a heavy ion through the device structure. The passage of the heavy ion generates a current filament that locally turns on a parasitic n-p-n transistor inherent to the power MOSFET. Subsequent high currents and high voltage in the device induce second breakdown of the parasitic bipolar transistor and hence meltdown of the device. This paper presents a model that can be used for simulating the burnout mechanism in order to gain insight into the significant device parameters that most influence the single-event burnout susceptibility of n-channel power MOSFETs. >

An AlGaAs/InGaAs pseudomorphic high electron mobility transistor with improved breakdown voltage for X- and Ku-band power applications

Abstract: The authors determined that RF drain current degradation is responsible for the poor power performance of wide-recessed pseudomorphic high-electron-mobility transistors (PHEMTs). A model based on surface states was proposed to explain this phenomenon, which then led to the use of charge-screen layers and a double-recessed gate process to suppress surface effects. Combined, these two modifications increased the device's gate-drain reverse breakdown voltage without causing a degradation in the transistor's RF drain current. This allowed the simultaneous achievement of high power-added efficiency and high power density which established a new performance record for power PHEMTs at X- and Ku-bands. Delay time analysis of single- and double-recessed PHEMTs revealed that the benefit of a larger breakdown voltage in the latter device design came at the cost of a larger drain delay time. Drain delay accounted for 45% of the total delay when the 0.35- mu m double-recessed PHEMT was biased at V/sub ds/=6 V. >

Integrated circuit with diode-connected transistor for reducing ESD damage

Abstract: A diode-connected transistor device for IC protection against electrostatic discharge (ESD) that functions as a transistor in the active region during an ESD event. The device cell includes an annular collector at the outer reaches of the cell, a circular base diffusion concentric with the collector, and an annular emitter near the outer edge of the base. The base and emitter regions are connected together by metallization external to the transistor cell. With the base contact enclosed by the annular emitter, during an ESD spike the initial reverse bias current flow is from the collector, under the emitter diffusion and out of the base contact. Eventually, as the magnitude of the ESD spike increases, the reverse biased current becomes sufficient to locally forward bias the base-emitter junction changing the primary ESD current path from collector to base, to collector to emitter, thus lowering the ESD current density in the active base-collector junction. Hence, the active emitter area is significantly increased with only a small increase in transistor area, resulting in reduced power density and joule heating, and increased overall ESD tolerance without significant change in parasitic capacitance.