Showing papers on "Transistor published in 1994"

All-polymer field-effect transistor realized by printing techniques

Abstract: A field-effect transistor has been fabricated from polymer materials by printing techniques. The device characteristics, which show high current output, are insensitive to mechanical treatments such as bending or twisting. This all-organic flexible device, realized with mild techniques, opens the way for large-area, low-cost plastic electronics.

Design of analog integrated circuits and systems

Abstract: MOS transistor models bipolar transistor models feedback and sensitivity in analogue integrated circuits elementary transistor stages behavioural modelling of operational and transconductance amplifiers operational amplifier design fundamentals of continuous-time and sampled-data active filters design and implementation of integrated active filters.

New efficient designs for XOR and XNOR functions on the transistor level

Abstract: Two new methods are proposed to implement the exclusive-OR and exclusive-NOR functions on the transistor level. The first method uses non-complementary signal inputs and the least number of transistors. The other one improves the performance of the prior method but two more transistors are utilized. Both of them have been fully simulated by HSPICE on a SUN SPARC 2 workstation. >

A new architecture for polymer transistors

Abstract: THE transistor, in its various forms, is a three-terminal amplifying electronic device1. Transistors are usually based on inorganic semiconductors, such as silicon or gallium arsenide1, but there is increasing interest in the use of organic semiconductors2–1, motivated by their structural flexibility and tunable electronic properties. The organic transistors fabricated to date have used a conventional 'field-effect' architecture; unfortunately, such devices involve relatively long conduction pathways which, owing to the low carrier mobilities of the organic materials, render them inherently slow. In an attempt to circumvent this problem, we have developed a different device geometry, more closely related to that of the vacuum-tube triode. The structure consists of a thin film of a semiconducting polymer sandwiched between two electrodes, with the third electrode―a layer of a porous metallic polymer5― embedded within the semiconductor. The third electrode plays a role similar to that of the grid in a vacuum tube, controlling the current flow between the two outermost electrodes. This thin-film architecture reduces the length of the conduction pathway, resulting in a relatively fast response time and, in contrast to conventional field-effect transistors, does not require lateral patterning.

Evaluation of a dual bias dual metal oxide-silicon semiconductor field effect transistor detector as radiation dosimeter

Abstract: A new type of direct reading semiconductordosimeter has been investigated as a radiation detector for photon and electron therapy beams of various energies. The operation of this device is based on the measurement of the threshold voltage shift in a custom‐built metal oxide‐silicon semiconductorfield effect transistor(MOSFET). This voltage is a linear function of absorbed dose. The extent of the linearity region is dependent on the voltage controlled operation during irradiation. Operating two MOSFETS at two different biases simultaneously during irradiation will result in sensitivity (V/Gy) reproducibility better than ±3% over a range in dose of 100 Gy and at a dose per fraction greater than 20×10−2 Gy. The modes of operation give this device many advantages, such as continuous monitoring during irradiation, immediate reading, and permanent storage of total dose after irradiation. The availability and ease of use of these MOSFETdetectors make them very promising in clinical dosimetry.

Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels

Abstract: An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range. If the comparison results under employment of the first voltage shows that an irregularly written cell transistor remains with an insufficient threshold voltage which is so low as to fail to fall within the range, the write operation continues for the same cell transistor. If the comparison results under employment of the second voltage shows that an excess-written cell transistor remains, the block is rendered "protected" at least partially.

Series-parallel association of FET's for high gain and high frequency applications

Abstract: This paper presents a simple approach in the design of composite field effect transistors with low output conductance. These transistors consist of the series association of two transistors, with the transistor connected to the drain terminal wider than the transistor connected to the source terminal. It is shown that this composite transistor has the same DC characteristics as a long-channel transistor of uniform width. A composite transistor has two main advantages over its "DC equivalent" transistor of uniform width: significant area savings and a higher cutoff frequency. The main application is low-voltage, high-frequency analog circuits. The proposed technique is particularly suited for analog design in gate arrays. >

Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility

Abstract: An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier. Alternatively, improved transistors for electrostatic discharge protection can be formed in the silicon film by fabricating the transistor in a plurality of electrically isolated segments, each segment having source and drain regions separated by a channel region with the regions being electrically interconnected with like regions in other segments. Increased ESD current can be realized as compared to the ESD current for a wider unsegmented device.

Vertical power mosfet having thick metal layer to reduce distributed resistance

Abstract: The on-resistance of a vertical power transistor is substantially reduced by forming a thick metal layer on top of the relatively thin metal layer that is conventionally used to make contact with the individual transistor cells in the device. The thick metal layer is preferably plated electrolessly on the thin metal layer through an opening that is formed in the passivation layer.

Total dose effects in conventional bipolar transistors and linear integrated circuits

Abstract: Total dose damage is investigated for discrete bipolar transistors and linear integrated circuits that are fabricated with older processing technologies, but are frequently used in space applications. The Kirk effect limits the current density of discrete transistors with high collector breakdown voltage, increasing their sensitivity to ionizing radiation because they must operate low injection levels. Bias conditions during irradiation had different effects on discrete and integrated circuit transistors: discrete devices were strongly dependent on bias conditions, whereas damage in the linear ICs was nearly the same with or without bias. There were also large differences in the response of these devices at low dose rates. None of the discrete transistors exhibited enhanced damage at low dose rates, whereas substantially more damage occurred in the linear devices under low dose rate conditions, particularly for parameters that rely directly on p-n-p transistors. The threshold for dose rate effects in p-n-p transistors was about 0.01 rad(Si)/s, which is approximately two orders of magnitude lower than the corresponding threshold for n-p-n transistors in integrated circuits. >

Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits

Abstract: As the number of transistors integrated on a circuit continues to increase, roughly doubling every 18 months, the impact of transistor variations on circuit performance becomes more significant. Even in the absence of systematic variations (implant nonuniformities, Leff and Weff variations), there exists a fundamental variability in the threshold voltage V/sub T/ due to the finite number of dopant atoms in the extremely small MOSFET channel area. This work presents for the first time the impact of these fundamental V/sub T/ variations on SRAM cell stability and CMOS logic performance. We also analyze the impact of device scaling on these V/sub T/ variations and propose guidelines for future SRAM cell design. >

A self-aligned dual-bit split gate (dsg) flash eeprom cell

Abstract: An EEPROM cell structure includes two floating gate transistors (20, 22) separated by a select gate transistor (24) with the select transistor being shared by the two floating gate transistors in programming, reading, and erasing a floating gate transistor The floating gates (20B, 22B) of the two transistors are formed from a first polysilicon layer, the control gates (20C, 22C) of the two transistors are formed from a second polysilicon layer, and the select gate (24A) is formed from a third polysilicon layer The channel length (24G) of the select transistor is fully self-aligned to the floating gate transistors (20, 22) A word line (28) is formed over the control gates and forms the select gate The word line (28) runs generally perpendicular to bit lines (22A, 20A) which contact the drain regions of the two floating gate transistors Accordingly, a virtual ground flash EEPROM memory array can be fabricated using the EEPROM cell structure

Intrinsic noise of the single-electron transistor.

Abstract: The paper is devoted to calculation of the ``classical'' (thermal and/or shot) intrinsic noise of the single-electron transistor (SET) caused by the stochastic character of electron tunneling. Exact solution of the master equation describing the dynamics of the SET is obtained in the frequency representation. The low-frequency limit for the spectral calculations is considered in detail.

Complementary junction heterostructure field-effect transistor

Abstract: A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

Vertical insulated gate transistor and method of manufacture

Abstract: A vertical insulated gate transistor such as a UMOSFET is manufactured. A source region of first conductivity type is formed on the bottom surface of a substrate. A base region of second conductivity type is formed on the source region. A low-impurity-concentration drift region is formed on the base region. On the top surface of this multilayer structure, a truncated U groove is formed. A buried gate electrode is formed inside the truncated U groove. This structure is effective to reduce gate-drain capacitance Cgd, gate-source capacitance Cgs, and drain resistance r d , thereby realizing a high-frequency high-output device. A distance between the gate and the drain is determined in a self-aligning manner, so that a fine structure and a high-frequency operation are easily realized and production yield is improved.

Silicon field-effect transistor based on quantum tunneling

Abstract: This letter explores regulation of current flow within a silicon field‐effect transistor by gate‐induced tunneling through a Schottky barrier located at the interface between a metallic source electrode and the Si channel. The goal here is to forestall short‐channel effects which are expected to prevent further size reductions in conventional devices when linewidths reach ∼1000 A. Control of tunneling appears to be possible at minimum channel lengths L∼250 A or less while simultaneously eliminating the need for large‐area source and drain contacts, so that scaling of Si transistors could be significantly extended if this principle proves technically feasible.

Electrical and thermal characterization of MESFETs, HEMTs, and HBTs

Abstract: Physical Modeling of III-V Semiconductor Devices. How to Measure Temperature-dependent Equivalent Circuits. Self-heating in Transistors. GaAs MESFET Equivalent Circuits (Room Temperature). Temperature-dependent MESFET Equivalent Circuits. HEMT Equivalent Circuits (Room Temperature). Temperature-dependent HEMT Equivalent Circuits. Gate Currents in MESFETs and HEMTs. Heterojunction Bipolar Transistors. Circuit Modeling.

Nonvolatile semiconductor memory

Abstract: A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors. The semiconductor memory employs an arrangement for effectively using a plurality of source voltages and applying a verify voltage to sense amplifiers and word lines, a write verify arrangement for detecting an output of the sense amplifiers, an arrangement for comparing an output of the sense amplifiers with a reference value to determine whether or not a written state of the memory cell transistors is acceptable, an arrangement for adjusting an output of the sense amplifiers with use of inverters and transistors in response to a current flowing to the memory cell transistors, to improve a drive speed of the sense amplifiers, an internal source voltage generating arrangement using an n-channel depletion transistor connected to an external source voltage (Vcc), the gate of the transistor being connected to a low source voltage (Vss) to provide an internal source voltage (Vci), a combination of an arrangement for dropping the external source voltage (Vcc) for read to a predetermined value to drive a read circuit in the memory and an arrangement for dropping an external voltage (Vpp) for write, to generate a word line potential for a verify-after-write operation, an arrangement for setting a reference voltage (Vref) as a lower threshold (Vth) allowed for cell transistors (11 00 to 11 22 ), and comparing the voltage of a data bus (13) with the reference voltage (Vref), to simultaneously carry out an erase-verify operation on all memory cell transistors, and a pre-read arrangement for accessing the next address during a read time of the sense amplifiers, to improve a read speed.

An experimental high-density DRAM cell with a built-in gain stage

Abstract: A new high-density DRAM cell concept is proposed and experimentally demonstrated. This cell, composed of two transistors and one capacitor, generates a large bit line signal with a small cell capacitance during the read cycle. Since it does not need a large storage capacitance and one transistor is stacked on the top of the other transistor, the cell size is small and can be easily scaled down for future generations of memory devices. The unit cell size fabricated using a 4 M SRAM process without any process modification is 1.8 /spl mu/m/spl times/2.85 /spl mu/m. The proposed cell can be adopted to store multi-bit information. The fabricated prototype cell shows a resolution of about 3.5 bit. >

A capacitorless dram device on silicon-on-insulator substrate

Abstract: A DRAM device has a first semiconductor region (18) of one conductivity on the silicon film of a silicon-on-insulator substrate (22). A second (16) and a third (14) semiconductor region of the opposite conductivity are formed in the first semiconductor region (18). A fourth semiconductor region (12) of the same conductivity type as the first semiconductor region (18) is formed within the second semiconductor region (16) with higher doping concentration. A insulating layer (11) is formed on the semiconductor surface. On top of the insulating layer (11), a gate electrode (10) is formed and is at least partially overlapped with the first (18), the second (16), the third (14), and the fourth (12) semiconductor region. A storage node (24) is formed in the first semiconductor region (18) between the second (16) and the third (14) semiconductor region where the information is stored. The amount of charge stored in the storage node (24) is controlled by a first transistor including the fourth semiconductor region (12), the second semiconductor region (16), the storage node (24), and the gate electrode (10).

A semi-static complementary gain cell technology for sub-1 V supply DRAM's

Abstract: A new semi-static complementary gain cell for future low power DRAM's has been proposed and experimentally demonstrated. This gain cell consists of a write-transistor and its opposite conduction type read-transistor with a heating gate as a storage node which causes a shift in the threshold voltage. This gain cell provides a two orders of magnitude larger cell signal output and higher immunity to noise on the bitlines when compared with a conventional one-transistor DRAM cell without increasing the storage capacitance even at a supply voltage of 0.8 V. The 0.87 /spl mu/m/sup 2/ cell size is achieved by using a 0.25 /spl mu/m design rule with a polysilicon thin-film transistor built in the trench and phase shifted i-line lithography. >

Enhancement mode metal‐semiconductor field effect transistors using homoepitaxial diamonds

Abstract: Enhancement mode‐type metal‐semiconductor field effect transistors using diamond have been fabricated. The transistor operation is based on the control of surface p‐type conduction of a hydrogen terminated homoepitaxial layer. Boron doping was not used for the conduction. An aluminum contact is used for the Schottky gate and gold ohmic contacts are used for the source and drain. The obtained transconductance is 20–200 μs/mm using aluminum gates of 10–40 μm in length. The active region on the homoepitaxial layer is thin enough for the total depletion of carriers when the gate bias is zero.

The use of parasitic nonlinear capacitors in class E amplifiers

Abstract: The most common class E amplifier configuration uses a single transistor with a shunt capacitor and a series resonant output filter. Until now a linear shunt capacitance has been assumed. However, to achieve operation at 900 MHz and above, it is of interest to rely solely upon the nonlinear parasitic collector-substrate capacitance of the transistor. An analytical theory for operation at 50% duty cycle and nonlinear capacitance is presented in this correspondence, and the effects on the power capability of the amplifier are discussed. >

Method of and apparatus for providing offset for light detector

Abstract: The invention provides a solid state light imager or x-ray detector including an array of rows and columns of elements, each element including a photo diode, which converts photons to an electrical signal, and a transistor. Each photo diode has a capacitance associated with it. The cathode of the photo diode in each element is connected to the source of the transistor in the element. The amount of charge removed from each photo diode, after exposure to light, is used to create an image. The image is capable of accurate measurement of charge removed from the photo diodes after the array has been exposed to light, using unipolar measuring circuitry, in spite of charge retention by the transistors and a problem caused by the combination of changes in row voltage and parasitic row to column capacitance.

Method of making a high-density DRAM structure on SOI

Abstract: A high density, DRAM cell array with a very short channel, vertical gate transfer transistor that can be manufactured using conventional photolithography process steps. The conventional four-by-four DRAM array shown schematically in FIG. 1a is rearranged to the shared-gate, double-bit array shown schematically in FIG. 1b. Trench storage capacitors and vertical FET transistors are arranged in pairs with a common vertical gate and a common substrate, allowing both bit and substrate contacts to be shared by adjacent cells.

Inverted spacer transistor

Abstract: A method for forming narrow length transistors by forming a trench in a first layer over a semiconductor substrate. Spacers are then formed within the trench and a gate dielectric is formed between the spacers at the bottom of the trench on the semiconductor substrate. The trench is then filled with a gate electrode material which is chemically-mechanically polished back to isolate the gate electrode material within the trench, and the first layer is removed leaving the gate dielectric, gate electrode and spacers behind.

Flexible panel display having thin film transistors driving polymer light-emitting diodes

Abstract: A non-planar electronic light-emitting display has a display area divided into a matrix of pixels. Each pixel includes two primary elements, an electronic driver and a light-emitting diode based on a light-emitting polymer. The electronic driver is a thin film transistor device of amorphous silicon formed on the insulating substrate. The diode has a first electrode connected to and driven by the electronic transistor, a layer of light-emitting polymer deposited on the electrode, and an overlying electrode normally biased on. Energization of the driver biases the diode to cause the polymer to emit light. Each pixel is configured with the two-component structure described above, and row and column lines to the matrix of pixels are decoded by the drivers to cause selective illumination of the pixels.

Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay

Abstract: An improved model for the ramp response of a CMOS inverter has been derived where the influences of the short-circuit current and the input-to-output coupling capacitance are considered. These effects modify the ideal linear relationship between the inverter propagation delay and the input ramp rise/fall time by adding a term proportional to the charge supplied by the short-circuiting transistor. This term is shown to contain first- and second-order contributions of the input ramp rise/fall time where the second-order contribution effectively models the propagation delay roll-off for slow input ramps. Both the first and the second-order effects are found to be affected by the P-to-N-channel gain ratio. The model shows excellent agreement with SPICE level 3 simulations; even when the short-circuiting transistor has a driving capability twice that of the charging/discharging transistor the error in the propagation delay is only about 2% for a slow input ramp (input-to-output slope-ratio at V/sub DD//2 equal to 1:2). >

Method for forming a field-effect transistor including anodic oxidation of the gate

Abstract: An insulated-gate field-effect transistor adapted to be used in an active-matrix liquid-crystal display. The channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.