Showing papers on "Transistor published in 1995"

Metal oxide semiconductor device forming a pn junction with a thin film transistor of metal oxide semiconductor of copper suboxide and manufacture thereof

Abstract: PURPOSE: To obtain an excellent PN junction by doping controlled metal oxide semiconductor with impurities, by controlling defects by introducing hydrogen or the like in the defects due to the excessive oxygen in a part of metal oxide semiconductor of copper suboxide or the like, and controlling the carrier density and the conductivity type. CONSTITUTION: A metal oxide semiconductor 25 is metal semiconductor obtained by oxidizing metal films 24, 24'. An insulating protective film is formed on the surfaces of an insulating film 26 and the metal oxide semiconductor 25. By leading out electrodes connected with source drain electrodes 24, 24', a transistor having a gate electrode 22 is formed. The carrier density and the conductivity type are controlled by eliminating oxygen defects. The P-type conductivity or the N-type conductivity, and the resistivity can be controlled by impurity doping. In these cases, ion implantation method or the like can be applied. Thereby a thin film transistor of high mobility can be formed in a large area by low temperature treatment.

Organic Heterostructure Field-Èffect Transistors

Abstract: Organic field-effect transistors have been developed that function as either n-channel or p-channel devices, depending on the gate bias. The two active materials are α-hexathienylene (α-6T) and C 60 . The characteristics of these devices depend mainly on the molecular orbital energy levels and transport properties of α-6T and C 60 . The observed effects are not unique to the two materials chosen and can be quite universal provided certain conditions are met. The device can be used as a building block to form low-cost, low-power complementary integrated circuits.

Electrical Characterization of Silicon-on-Insulator Materials and Devices

Abstract: 1. Introduction. 2. Methods of Forming SOI Wafers. 3. SOI Devices. 4. Wafer Screening Techniques. 5. Transport Measurements. 6. SUS Capacitor Based Characterization Techniques. 7. Diode Measurements. 8. Transistor Characteristics. 9. Transistor Based Characterization Techniques. 10. Monitoring the Transistor Degradation. Index.

Complete guide to semiconductor devices

Abstract: Preface. Preface to the First Edition. Introduction. DIODES I: RECTIFIERS. p-n Junction Diode. p-i-n Diode. Schottky-Barrier Diode. Planar-Doped-Barrier (PDB) Diode. Isotype Heterojunction. DIODES II: NEGATIVE RESISTANCE N-SHAPED. Tunnel Diode. Transferred-Electron Device (TED). Resonant-Tunneling Diode. Resonant-Interband-Tunneling (RIT) Diode. Single-Barrier Tunnel Diode. Single-Barrier Tunnel Diode. Single-Barrier Interband-Tunneling Diode. Real-Space-Transfer (RST) Diode. DIODES III: NEGATIVE RESISTANCE S-SHAPED. Metal-Insulator-Semiconductor Switch (MISS). Planar-Doped-Barrier (PDB) Switch. Amorphous Threshold Switch. Heterostructure Hot-Electron Diode (HHED). DIODES IV: NEGATIVE RESISTANCE TRANSIT-TIME. Impact-Ionization-Avalanche Transit-Time (IMPATT) Diode. Barrier-Injection Transit-Time (BARITT) Diode. RESISTIVE AND CAPACITIVE DEVICES. Resistor. Metal-Oxide-Semiconductor (MOS) Capacitor. Charge-Coupled Device (CCD). TRANSISTORS I: FIELD-EFFECT. Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Junction Field-Effect Transistor (JFET). Metal-Semiconductor Field-Effect Transistor (MESFET). Modulation-Doped Field-Effect Transistor (MODFET). Permeable-Base Transistor. Static-Induction Transistor (SIT). Real-Space-Transfer (RST) Transistor. Planar-Doped Field-Effect Transistor. Surface-Tunnel Transistor. Lateral Resonant-Tunneling Field-Effect Transistor (LRTFET). Stark-Effect Transistor. Velocity-Modulation Transistor (VMT). TRANSISTOR II: POTENTIAL-EFFECT. Bipolar Transistor. Tunneling Hot-Electron-Transfer Amplifier (THETA). Metal-Base Transistor. Bipolar Inversion-Channel Field-Effect Transistor (BICFET). Tunnel-Emitter Transistor (TETRAN). Planar-Doped-Barrier (PDB) Transistor. Heterojunction Hot-Electron Transistor (HHET). Induced-Base Transistor. Resonant-Tunneling Bipolar Transistor (RTBT/RBT). Resonant-Tunneling Hot-Electron Transistor (RHET). Quantum-Well-Base Resonant-Tunneling Transistor (QWBRTT). Spin-Valve Transistor. NONVOLATILE MEMORIES. Floating-Gate Avalanche-Injection Metal-Oxide-Semiconductor (FAMOS) Transistor. Metal-Nitride-Oxide-Semiconductor (MNOS) Transistor. THYRISTORS AND POWER DEVICES. Silicon-Controlled Rectifier (SCR). Insulated-Gate Bipolar Transistor (IGBT). Static-Induction Thyristor (SIThy). Unijunction Transistor. PHOTONICS I: LIGHT SOURCES. Light-Emitting Diode (LED). Injection Laser. PHOTONICS II: PHOTODETECTORS. Photoconductor. p-i-n Photodiode. Schottky-Barrier Photodiode. Charge-Coupled Image Sensor (CCIS). Avalanche Photodiode (APD). Phototransistor. Metal-Smiconductor-Metal (MSM) Photodetector. Quantum-Well Infrared Photodetector (QWIP). Quantum-Dot Infrared Photodetector (QDIP). Blocked-Impurity-Band (BIB) Photodetector. Negative-Electron-Affinity (NEA) Photocathode. Photon-Drag Detector. PHOTONICS III: BISTABLE OPTICAL DEVICES. Self-Electrooptic-Effect Device (SEED). Bistable Etalon. PHOTONICS IV: OTHER DEVICES. Solar Cell. Electroabsorption Modulator. Thermistor. Hall Plate. Strain Gauge (Gage). Interdigital Transducer (IDT). Ion-Sensitive Field-Effect Transistor (ISFET). Appendix A: Selected Nonsemiconductor Devices. Appendix B: Physical Phenomena. Appendix C: General Applications of Device Groups. Appendix D: Physical Properties. Appendix E: Background Information. Index.

Perpendicular hot electron spin-valve effect in a new magnetic field sensor: The spin-valve transistor.

Abstract: A new magnetic field sensor is presented, based on perpendicular hot electron transport in a giant magnetoresistance (Co/Cu)4 multilayer, which serves as a base region of an n-silicon metal-base transistor structure. A 215% change in collector current is found in 500 Oe (77 K), with typical characteristics of the spin-valve effect. The in-plane magnetoresistance was only 3%. The transistor structure allows the investigation of energy resolved perpendicular transport properties, and in particular spin-dependent scattering of hot electrons in transition-metal as well as rare-earth-based multilayers.

Silicon surface tunnel transistor

Abstract: A silicon surface tunneling transistor structure, based on lateral band‐to‐band tunneling, is presented The theory, fabrication, and operation of the device is described Band‐to‐band tunneling is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier The operation of the device is confirmed in both experimental results and two‐dimensional computer simulations Dramatic differences in drain current are observed for different gate bias

Volatile and non-volatile memories in silicon with nano-crystal storage

Abstract: A single transistor memory structure, with changes in threshold voltage exceeding /spl ap/0.25 V corresponding to single electron storage in individual nano-crystals, operating in the sub-3 V range, and exhibiting long term to non-volatile charge storage is reported. As a consequence of Coulombic effects, operation at 77 K shows a saturation in threshold voltage in a range of gate voltages with steps in the threshold voltage corresponding to single and multiple electron storage. The plateauing of threshold shift, operation at ultra-low power, low voltages, and single element implementation utilizing current sensing makes this an alternative memory at speeds lower than those of DRAMs and higher than those of E/sup 2/PROMs, but with potential for significantly higher density, lower power, and faster read.

Current-dependent light-emitting element drive circuit for use in active matrix display device

Abstract: In a light-emitting element drive circuit in an active matrix display device, at least one current-control transistor controls a current flowing through a light-emitting element. The current-control transistor and the light-emitting element are connected in parallel to each other. A constant current source is connected to a junction between one electrode of the light-emitting element and one electrode of the transistor through which the current 8s controlled to flow. The other electrodes of the light-emitting element and the transistor are connected to a common electrode which may be grounded via a resistor. In other configuration, it may be arranged that the light-emitting element and a capacitance are connected in parallel to each other. In this case, the current-control transistor is connected to a function between the light-emitting element and the capacitance so as to use charging and discharging operations of the capacitance for driving the light-emitting element.

Insulated-gate transistor having narrow-bandgap-source

Abstract: A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Six Ge1-x, Six Sn1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Direct-current measurements of oxide and interface traps on oxidized silicon

Abstract: A direct-current current-voltage (DCIV) measurement technique of interface and oxide traps on oxidized silicon is demonstrated It uses the gate-controlled parasitic bipolar junction transistor of a metal-oxide-silicon field-effect transistor in a p/n junction isolation well to monitor the change of the oxide and interface trap density The dc base and collector currents are the monitors, hence, this technique is more sensitive and reliable than the traditional ac methods for determination of fundamental kinetic rates and transistor degradation mechanisms, such as charge pumping >

Top-drain trench based resurf DMOS transistor structure

Abstract: A top drain trench based RESURF DMOS (reduced surface field double diffused MOS) transistor structure provides improved RDSon performance by minimizing transistor cell pitch. The transistor includes a gate, a source and drain. The trench may include a nonuniform dielectric lining. A drain drift region partially surrounds the trench. Current flows laterally enabling multiple trench based RESURF DMOS transistors to be formed on a single semiconductor die. The addition of an isolation region to electrically isolate the source from the substrate allows the power transistor to be incorporated into high side driver applications as well as other application mandating electrical isolation between the source and ground.

Low-voltage circuits building blocks using multiple-input floating-gate transistors

Abstract: A systematic approach for designing analog circuits with low supply voltage requirements is discussed. This approach is based on the utilization of multiple-input floating-gate transistors. Current mirrors and differential pair building blocks are discussed as well as a low voltage BiCMOS operational amplifier based on these building blocks.

Novel transistor with ultra shallow tip and method of fabrication

Abstract: A novel transistor (200) with a low resistance ultra shallow tip region (214) and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip region (210) comprising an ultra shallow region (214) which extends beneath the gate electrode and a raised region (216).

Integrated circuit having both vertical and horizontal devices and process for making the same

Abstract: An integrated circuit (10) has a vertical device, such as a transistor (71), formed by epitaxial growth from a substrate (12) and a horizontal device, such as a transistor (73, 75) grown epitaxially from the vertical device. In accordance with one embodiment of the invention, all six transistors of an SRAM cell can be formed in single crystal material for improved device characteristics and increased cell density. Utilization of various combinations of vertical and horizontal devices permits a large degree of vertical integration within semiconductor devices.

Dynamic random access memory array having a cross-point layout, tungsten digit lines buried in the substrate, and vertical access transistors

Abstract: This invention is a DRAM array having stacked-capacitor cells of potentially 4F 2 surface area (F being the photolithographic minimum feature width), and a 5-mask process for fabricating such an array. The array has a cross-point cell layout (i.e., a memory cell is located at each intersection of each digit line and each word line) and tungsten digit lines formed using a damascene process buried in the substrate. Each cell in the array has a vertical transistor, with the source/drain regions and channel region of the transistor being formed from epitaxially grown single crystal silicon. The stacked capacitor is fabricated on top of the vertical transistor.

Introduction to electronic devices

Abstract: Basics of Quantum Mechanics. Basics of Solid State Physics. Electrons and Holes in Semiconductors. Diodes and Contacts. Bipolar Junction Transistors. MOSFETs. Compound Semiconductor FETs and Thin Film Transistors (TFTs). Photonic Devices. Device Fabrication and Novel Devices. Appendices. Glossary. Index.

Layout method for semiconductor integrated circuit and layout apparatus for semiconductor integrated circuit

Abstract: There is disclosed a layout method for a semiconductor integrated circuit for use in design by a symbolic layout which expresses a configuration of the semiconductor integrated circuit by symbols. The layout method comprises the steps of extracting a mask layout to be processed, changing dimensions of a symbolic layout included in the mask layout, replacing transistor symbols included in the mask layout with symbols having diffusion layer terminals each having a constant length in the channel width direction and not having extent in the channel length direction, shortening a length of wiring included in the mask layout in the channel width direction of the transistor, and compacting the mask layout in the channel length direction of the transistor.

Field-effect transistor having a semiconductor layer made of an organic compound

Abstract: A field-effect transistor using a conjugated oligomer having an ionization potential of 4.8 eV or above in the semiconductor layer thereof works stably and has a long life-time and can be used in a liquid crystal display device as a switching element to give excellent contrast and good performances.

Transistor-level timing and simulator and power analyzer

Abstract: A method for accurately simulating the timing and power behavior of digital MOS circuits is provided. The method includes piece-wise linear modeling of transistors, dynamic and static construction of channel connected components, event driven simulation and current measuring capabilities for power supplies, grounds, and individual resistors and transistors.

Transistor with low resistance tip and method of fabrication in a CMOS process

Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first gate electrode are formed on a first portion of a semiconductor substrate having a first conductivity type, and a second gate dielectric and a said gate electrode are formed on a second portion of semiconductor substrate having a second conductivity type. A silicon nitride layer is formed over the first portion of the semiconductor substrate including the first gate electrode and over the second portion of the semiconductor substrate including the second gate electrode. The silicon nitride layer is removed from the second portion of the silicon substrate and from the top of the second gate electrode to thereby form a first pair of silicon nitride spacers adjacent to opposite sides of the second gate electrode. A pair of recesses are then formed in the second portion of the semiconductor substrate in alignment with the first pair of sidewall spacers. A selectively deposited semiconductor material is then formed in the recesses.

Minimization of circuit delay and power through transistor sizing

Abstract: A method for minimizing signal delay and power consumption is provided. Through combined power simulation and delay analysis, iterative transistor resizing is performed based on a variety of factors including relative delay of associated circuit paths, nodal switching activities and association of transistors in channel-connected sets.

Memory with isolatable expandable bit lines

Abstract: The invention enables random read and write operations into cells in an array that contains connections from the memory cells that include at least one field effect transistor (FET transistor) to embedded bit line segments which are selectively isolatable and selectively expandable to achieve compactness of number of cell per unit area. In a given segment of the array a first select transistor is connected between a given embedded bit line segment and a first access bit line which functions as a path from a first reference voltage to the drain of a first FET memory transistor set when the first select transistor is turned off, and wherein the first access bit line functions as a path from the source of a second FET memory transistor set to a second reference voltage when the first select transistor is turned on. A second select transistor connected between the embedded bit line segment and a second bit line which functions as a path from said first reference voltage to the drain of a second Memory FET set when the second select transistor is turned off, and wherein said second bit line functions as a path from the source of the first Memory FET set to a second reference voltage when said first select transistor is turned on. The invention also reduces the diffusion isolation spacing between bit-lines by using shield transistors.

Performance of the 3-D PENCIL flash EPROM cell and memory array

Abstract: A promising new 3-D Programmable Erasable Nonvolatile CylIndricaL (PENCIL) flash EPROM cell that offers significant area and performance advantages over conventional planar approaches has been implemented in a novel memory array. The 3-D PENCIL cell is a vertical device formed on the sidewalls of an etched silicon pillar. The cell is a single transistor stacked gate structure with the floating gate and control gate completely surrounding the pillar. Current flows vertically from the bit line contact at the top of the pillar to the source lying at the bottom of the pillar. When implemented in a novel self-aligned array, the cell size approaches the square of the minimum pitch and has an area less than half that of the conventional NOR type structure. The cell and array architecture also promise to be highly scalable. Experimental data reveals that the cells have up to 3/spl times/ larger read current than comparable planar cells, are suitable for 5 V only operation and have fast program and erase speeds at moderate voltage levels. Uniformity and endurance characteristics are also promising. >

A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's

Abstract: This paper describes a novel circuit technology with Surrounding Gate Transistors (SGT's) For ultra high density DRAM's. In order to reduce the chip size drastically, an SGT is employed to all the transistors within a chip. SGT's connected in series and a common source SGT have been newly developed for the core circuit, such as a sense amplifier designed by a tight design rule. Furthermore, to reduce the inherent cell array noise caused by a relaxed open bit line (BL) architecture, a noise killer circuit placed in the word line (WL) shunt region and a twisted BL architecture within the sense amplifier region combined with a novel separation sensing scheme have been newly introduced. Using the novel circuit technology, a 32.9% smaller chip size can be successfully achieved for a 64-Mb DRAM and 34.4% for a 1-Gb DRAM compared with a DRAM composed of the planar transistor without sacrificing the access time, power dissipation, and V/sub cc/ margin. Furthermore,the effectiveness of this technology is verified by using the circuit simulation of the internal main nodes such as WL and BL. >

Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer

Abstract: A process is disclosed for preparing a silicon-on-sapphire wafer suited for fabrication of fully depleted field effect transistors. A fully depleted field effect transistor (FET) which has minimum parasitic charge in the conduction channel and a process to make same are described. The device is made in and relies on the silicon layer on sapphire which has minimal charge intentionally introduced into the conduction channel. Both N-type and P-type transistors are described. Methods for defining threshold voltage are also described. Specific examples of the devices are presented including specific materials selections for threshold voltage options. Manufacturing processes are described, including a preferred embodiment based on ultra thin silicon on sapphire. The devices can be fabricated using conventional silicon techniques; both silicided and non-silicided versions are presented. Advantages include threshold voltages determined by fundamental material properties; high performance devices due to reduced carrier scattering, low transverse electric fields and elimination of the body effect; threshold voltages virtually independent of temperature; simplicity of modeling due to reduction or elimination of parasitic effects; device and process simplicity; ease of scaling and an option for inherently symmetric threshold voltages for N-channel and P-channel MOSFETs (i.e. .linevert split.V tn .linevert split.=.linevert split.V tp .linevert split.).

Possible performance of capacitively coupled single‐electron transistors in digital circuits

Abstract: We have carried out a theoretical analysis of the possible performance of single‐electron transistors with capacitive coupling in simple logic and memory circuits. Both resistively loaded and complementary transistors have been analyzed, with a detailed account of parasitic factors including thermal fluctuations and background charge variations. The analysis shows that at optimal values of the parameters including the background charge, the maximum operation temperature is close to 0.025e2/CkB, where C is the capacitance of the smallest tunnel junction. At T∼0.01e2/CkB the parameter margins are relatively wide; for the structures with 2‐nm minimum feature size, the latter temperature is close to 77 K. A typical margin for background charge fluctuations is on the order of 0.1e; these fluctuations may be a major obstacle for practical ultradense single‐electron circuits.

Experimental investigation of a PtSi source and drain field emission transistor

Abstract: A p‐type PtSi source and drain, no ‘‘gap,’’ metal oxide semiconductor field effect transistor (MOSFET) has been successfully fabricated and experimentally investigated in detail down to 4.2 K. Gate curves (source current versus gate voltage) clearly show that, in the ‘‘on’’ state, the current flow mechanism from the source metal into the channel gradually changes from primarily thermal emission over the small ∼0.2 eV Schottky barrier to holes to completely field emission through the triangular Schottky barrier as the temperature is lowered below ∼100 K. Gate curves for different channel lengths also show minimal short channel effects down to 1.0 μm, in agreement with previous simulations. Drain curves (source current versus drain voltage) demonstrate that the drive current is comparable to that of a conventional MOSFET, and that the Schottky barrier is rendered transparent to the flow of holes when the device is strongly ‘‘on.’’

High-speed current mirror resistive compensation technique

Abstract: In the Letter the authors propose a very simple but powerful method of speed and bandwidth enhancement for general CMOS current mirror circuits. Introducing a compensation resistor between the gates of the primary transistor pair of the current mirror can lead to a significant bandwidth enhancement. Simulated and measured results are presented.

Semiconductor memory device comprising multi-level logic value of the threshold voltage

Abstract: A semiconductor memory device including a semiconductor substrate, and an array of a plurality of memory cells formed and arranged on the semiconductor substrate. Each memory cell contains a first transistor provided with a gate, and the semiconductor substrate includes element separating trenches arranged at least in part of the respective memory cells and each of the element separating trenches is embedded at least partly with an element separating insulative film. An electrically conductive film is embedded in at least part of the remaining area of the trench, a second transistor is constructed by at least part of the lateral sides of each of the element separating trenches having an embedded conductive film forming a part of a channel region, and a third transistor is constructed by another part of the the lateral sides of each of the element separating trenches forming part of a channel region. Diffusion layers of sources and drains of the second transistor and the third transistor are shared and the second and third transistors are connected in parallel to construct the first transistor of the memory cell. The threshold voltage of the second transistor having the conductive film formed as a second gate is set to a voltage higher than a voltage applied to the second gate selected in a read operation.