Showing papers on "Transistor published in 1998"

Room-temperature transistor based on a single carbon nanotube

Abstract: The use of individual molecules as functional electronic devices was first proposed in the 1970s (ref 1) Since then, molecular electronics2,3 has attracted much interest, particularly because it could lead to conceptually new miniaturization strategies in the electronics and computer industry The realization of single-molecule devices has remained challenging, largely owing to difficulties in achieving electrical contact to individual molecules Recent advances in nanotechnology, however, have resulted in electrical measurements on single molecules4,5,6,7 Here we report the fabrication of a field-effect transistor—a three-terminal switching device—that consists of one semiconducting8,9,10 single-wall carbon nanotube11,12 connected to two metal electrodes By applying a voltage to a gate electrode, the nanotube can be switched from a conducting to an insulating state We have previously reported5 similar behaviour for a metallic single-wall carbon nanotube operated at extremely low temperatures The present device, in contrast, operates at room temperature, thereby meeting an important requirement for potential practical applications Electrical measurements on the nanotube transistor indicate that its operation characteristics can be qualitatively described by the semiclassical band-bending models currently used for traditional semiconductor devices The fabrication of the three-terminal switching device at the level of a single molecule represents an important step towards molecular electronics

Integrated Optoelectronic Devices Based on Conjugated Polymers

Abstract: An all-polymer semiconductor integrated device is demonstrated with a high-mobility conjugated polymer field-effect transistor (FET) driving a polymer light-emitting diode (LED) of similar size. The FET uses regioregular poly(hexylthiophene). Its performance approaches that of inorganic amorphous silicon FETs, with field-effect mobilities of 0.05 to 0.1 square centimeters per volt second and ON-OFF current ratios of >10 6 . The high mobility is attributed to the formation of extended polaron states as a result of local self-organization, in contrast to the variable-range hopping of self-localized polarons found in more disordered polymers. The FET-LED device represents a step toward all-polymer optoelectronic integrated circuits such as active-matrix polymer LED displays.

Theory of the field-effect mobility in amorphous organic transistors

Abstract: The field-effect mobility in an organic thin-film transistor is studied theoretically. From a percolation model of hopping between localized states and a transistor model an analytic expression for the field-effect mobility is obtained. The theory is applied to describe the experiments by Brown et al. [Synth. Met. 88, 37 (1997)] on solution-processed amorphous organic transistors, made from a polymer (polythienylene vinylene) and from a small molecule (pentacene). Good agreement is obtained, with respect to both the gate voltage and the temperature dependence of the mobility.

The radio-frequency single-electron transistor (RF-SET): A fast and ultrasensitive electrometer

Abstract: A new type of electrometer is described that uses a single-electron transistor (SET) and that allows large operating speeds and extremely high charge sensitivity. The SET readout was accomplished by measuring the damping of a 1.7-gigahertz resonant circuit in which the device is embedded, and in some ways is the electrostatic “dual” of the well-known radio-frequency superconducting quantum interference device. The device is more than two orders of magnitude faster than previous single-electron devices, with a constant gain from dc to greater than 100 megahertz. For a still-unoptimized device, a charge sensitivity of 1.2 × 10 −5 e / hertz was obtained at a frequency of 1.1 megahertz, which is about an order of magnitude better than a typical, 1/ f -noise-limited SET, and corresponds to an energy sensitivity (in joules per hertz) of about 41 ℏ.

SiGe HBT technology: a new contender for Si-based RF and microwave circuit applications

Abstract: The silicon-germanium heterojunction bipolar transistor (SiGe HBT) is the first practical bandgap-engineered device to be realized in silicon. SiGe HBT technology combines transistor performance competitive with III-V technologies with the processing maturity, integration levels, yield, and hence, cost commonly associated with conventional Si fabrication. In the ten-and-one-half years since the first demonstration of a functional transistor, SiGe HBT technology has emerged from the research laboratory, entered manufacturing on 200-mm wafers, and is poised to enter the commercial RF and microwave market. State-of-the-art SiGe HBT's can deliver: (1) f/sub T/ in excess of 50 GHz; (2) f/sub max/ in excess of 70 GHz; (3) minimum noise figure below 0.7 dB at 2.0 GHz; (4) 1/f noise corner frequencies below 500 Hz; (5) cryogenic operation; (6) excellent radiation hardness; (7) competitive power amplifiers; and (8) reliability comparable to Si. A host of record-setting digital, analog, RF, and microwave circuits have been demonstrated in the past several years using SiGe HBT's, and recent work on passives and transmission lines on Si suggest a migratory path to Si-based monolithic microwave integrated circuits (MMIC's) is possible. The combination of SiGe HBT's with advanced Si CMOS to form an SiGe BiCMOS technology represents a unique opportunity for Si-based RF system-on-a-chip solutions. This paper reviews state-of-the-art SiGe HBT technology and assesses its potential for current and future RF and microwave systems.

A new generation of high voltage MOSFETs breaks the limit line of silicon

Abstract: For the first time a new device concept for high voltage power devices has been realized in silicon. Our 600 V-COOLMOS/sup TM/ reaches an area specific on-resistance of typically 3.5 /spl Omega//spl middot/mm/sup 2/. Our technology thus offers a shrink factor of 5 versus the actual state of the art in power MOSFETs. The device concept is based on charge compensation in the drift region of the transistor. We increase the doping of the vertical drift region roughly by one order of magnitude and counterbalance this additional charge by the implementation of fine structured columns of the opposite doping type. The blocking voltage of the transistor remains thus unaltered. The charge compensating columns do not contribute to the current conduction during the turn-on state. Nevertheless the drastically increased doping of the drift region allows the above mentioned reduction of the on-resistance.

Designing 1-V op amps using standard digital CMOS technology

Abstract: This paper addresses the difficulty of designing 1-V capable analog circuits in standard digital complementary metal-oxide-semiconductor (CMOS) technology, Design techniques for facilitating 1-V operation are discussed and 1-V analog building block circuits are presented. Most of these circuits use the bulk-driving technique to circumvent the metal-oxide-semiconductor field-effect transistor turn-on (threshold) voltage requirement. Finally, techniques are combined within a 1-V CMOS operational amplifier with rail-to-rail input and output ranges. While consuming 300 /spl mu/W, the 1-V rail-to-rail CMOS op amp achieves 1.3-MHz unity-gain frequency and 57/spl deg/ phase margin for a 22-pF load capacitance.

Self-assembly of single electron transistors and related devices

Abstract: For the past 40 years, since the invention of the integrated circuit, the number of transistors on a computer chip has doubled roughly every 18 months. As the limits of photolithography are rapidly approached, however, it is becoming clear that continued increases in circuit density will require fairly dramatic changes in the way transistors are designed and operated. This review summarizes current strategies for fabricating transistors which operate based on the flow of single electrons through nanometre-sized metal and semiconductor particles; i.e. single electron transistors (SETs). Because the room temperature operation of SETs requires nanoparticles <10 nm in diameter, we focus mainly on devices which have the potential for being assembled from the solution phase (non-lithographic systems). Several applications of SETs are discussed in addition to the major hurdles which must be overcome for their implementation in electronic device technology.

Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks

Abstract: Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The standby leakage current model has been verified by IISPICE. We demonstrate that the dependence of leakage power on primary input combinations can be accounted for by this model. Based on our analysis we can determine good bounds for leakage power in the standby mode. As a by-product of this analysis, we can also determine the set of input vectors which can put the circuits in the low-power standby mode. Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.

Characterization of ultra-thin oxides using electrical C-V and I-V measurements

Abstract: The measurement of electrical parameters from capacitance-voltage (C-V) and current-voltage (I-V) curves provides a fast means of characterizing oxides in MOS capacitors or transistor structures. For ultra-thin oxides (<2 nm), conventional, well-established techniques must be reconsidered and modified due to several increasingly important physical effects including polysilicon depletion and surface quantum mechanical effects. In this work these effects have been incorporated into a rapid analysis program for extracting ultra-thin oxide parameters from measured C-V and I-V data. The technique uses a physically based model of structure charge and potential combined with a non-linear least squares fitting technique to extract device parameters.

MOS Scaling: Transistor Challenges for the 21st Century

Abstract: Conventional scaling of gate oxide thickness, source/drain extension (SDE), junction depths, and gate lengths have enabled MOS gate dimensions to be reduced from 10μm in the 1970’s to a present day size of 0.1μm. To enable transistor scaling into the 21 century, new solutions such as high dielectric constant materials for gate insulation and shallow, ultra low resistivity junctions need to be developed. In this paper, for the first time, key scaling limits are quantified for MOS transistors (see Table 1). We show that traditional SiO2 gate dielectrics will reach fundamental leakage limits, due to tunneling, for an effective electrical thickness below 2.3 nm. Experimental data and simulations are used to show that although conventional scaling of junction depths is still possible, increased resistance for junction depths below 30 nm results in performance degradation. Because of these limits, it will not be possible to further improve short channel effects. This will result in either unacceptable off-state leakage currents or strongly degraded device performance for gate lengths below 0.10μm. MOS transistor limits will be reached for 0.13μm process technologies in production during 2002. Because of these problems, new solutions will need to be developed for continued transistor scaling. We discuss some of the proposed solutions including high dielectric constant gate materials and alternate device architectures.

Silicon single-electron quantum-dot transistor switch operating at room temperature

Abstract: We fabricated a silicon single-electron quantum-dot transistor, which showed drain current oscillations at room temperature. These oscillations are attributed to electron tunneling through a single silicon quantum dot inside a narrow wire channel. Analysis of its current–voltage characteristic indicates that the energy level separation is about 110 meV and the silicon dot diameter is about 12 nm.

Transistor matching in analog CMOS applications

Abstract: This paper gives an overview of MOSFET mismatch effects that form a performance/yield limitation for many designs. After a general description of (mis)matching, a comparison over past and future process generations is presented. The application of the matching model in CAD and analog circuit design is discussed. Mismatch effects gain importance as critical dimensions and CMOS power supply voltages decrease.

A new technique for standby leakage reduction in high-performance circuits

Abstract: A new standby leakage control technique, which exploits the leakage reduction offered by transistor stacks with "more than one 'off' device", demonstrates 2/spl times/ reduction in standby leakage power for a 32-bit static CMOS adder in a low-Vt, sub-1V, 0.1 /spl mu/m technology. Leakage reduction is achieved with minimal overheads in area, power and process technology. The dynamics of leakage reduction due to transistor stacks, and its influence on the overall leakage power of large circuits are elucidated for the first time.

An MOS transistor model for analog circuit design

Abstract: This paper presents a physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits. Static and dynamic characteristics of the MOS field-effect transistor are accurately described by single-piece functions of two saturation currents in all regions of operation. Simple expressions for the transconductance-to-current ratio, the drain-to-source saturation voltage, and the cutoff frequency in terms of the inversion level are given. The design of a common-source amplifier illustrates the application of the proposed model.

A folded-channel MOSFET for deep-sub-tenth micron era

Abstract: Deep-sub-tenth micron MOSFETs with gate length down to 20 nm are reported To improve the short channel effect immunities, a novel folded channel transistor structure is proposed The quasi-planar nature of this new variant of the vertical double-gate SOI MOSFETs simplified the fabrication process The special features of the structure are: (1) a transistor is formed in a vertical ultra-thin Si fin and is controlled by a double-gate, which suppresses short channel effects; (2) the two gates are self-aligned and are aligned to the S/D; (3) S/D is raised to reduce the parasitic resistance; (4) new low-temperature gate or ultra-thin gate dielectric materials can be used because they are deposited after the S/D; and (5) the structure is quasi-planar because the Si fins are relatively short

Integrated circuit technology options for RFICs-present status and future directions

Abstract: This paper will summarize the technology tradeoffs that are involved in the implementation of radio frequency integrated circuits for wireless communications. Radio transceiver circuits have a very broad range of requirements-including noise figure, linearity, gain, phase noise, and power dissipation. The advantages and disadvantages of each of the competing technologies-Si CMOS and bipolar junction transistors (BJTs), Si/SiGe HBTs and GaAs MESFETs, PHEMTS and HBTs will be examined in light of these requirements.

Broad-band power amplifier using dielectric photonic bandgap structure

Abstract: Two class AB GaAs field-effect transistor (FET) power amplifiers have been designed and fabricated in the 4.4-4.8 GHz range. In the first case, a dielectric PBG line was incorporated in the design to tune the second harmonic. In the second case, a 50-/spl Omega/ line is used with no harmonic tuning. The PBG structure allows broad-band harmonic tuning and is inexpensive to fabricate. A 5% improvement in power-added efficiency was achieved at the design frequency of 4.5 GHz, in both simulation and measurement.

Active matrix light emitting diode pixel structure and method

Abstract: A LED pixel structure (200, 300, 400, 600, 700) that reduces current nonuformities and threshold voltage variations in a 'drive transistor' of the pixel structure is disclosed. The LED pixel structure incorporates a current source for loading data into the pixel via a data line. Alternatively, an auto zero voltage is determined for the drive transistor prior to the loading of data.

Crystallization processing of semiconductor film regions on a substrate, and devices made therewith

Abstract: Semiconductor integrated devices such as transistors are formed in a film of semiconductor material formed on a substrate. For improved device characteristics, the semiconductor material has regular, quasi-regular or single-crystal structure. Such a structure is made by a technique involving localized irradiation of the film with one or several pulses of a beam of laser radiation, locally to melt the film through its entire thickness. The molten material then solidifies laterally from a seed area of the film. The semiconductor devices can be included as pixel controllers and drivers in liquid-crystal display devices, and in image sensors, static random-access memories (SRAM), silicon-on-insulator (SOI) devices, and three-dimensional integrated circuit devices.

Handbook of III-V Heterojunction Bipolar Transistors

Abstract: Basic Properties and Device Physics of III--V Materials. Two--Terminal Heterojunction Devices. D.C. Current Gain. Nonideal D.C. Characteristics. Thermal--Electrical Properties. Collapse of Current Gain. Failure Mechanisms and Reliability Issues. Small--Signal Properties. Epitaxial Layer Design. Geometrical Layout Design. Power Amplifier. Distortion and Noise. Switching Characteristics and Spice Models. Transistor Fabrication. Measured Transistor Performances. Appendices. Glossary of Symbols. Index.

MTCMOS hierarchical sizing based on mutual exclusive discharge patterns

Abstract: Multi-threshold CMOS is a popular circuit style that will provide high performance and low power operation. Optimally sizing the gating sleep transistor to provide adequate performance is difficult because the overall delay characteristics are strongly dependent on the discharge patterns of internal gates. This paper proposes a methodology for sizing the sleep transistor for a large module based on mutual exclusive discharge patterns of internal blocks. This algorithm can be applied at all levels of a circuit hierarchy, where the internal blocks can represent transistors, cells within an array, or entire modules. This methodology will give an upper bound for the sleep transistor size required to meet any performance constraint.

High density flash memory

Abstract: A high density flash EEPROM provides increased nonvolatile storage capacity. A memory cell array includes densely packed memory cells, each cell having a semiconductor pillar providing shared source/drain regions for two vertical floating gate transistors that have individual floating and control gates distributed on opposing sides of the pillar. The control gates are formed together with interconnecting gate lines. First source/drain terminals are row addressable by interconnection lines disposed substantially orthogonal to the gate lines. Second source/drain terminals are column addressable by data lines disposed substantially parallel to the gate lines. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data, an area of only 2F 2 is needed per bit of data, where F is the minimum lithographic feature size. If multiple charge states (more than two) are used, an area of less than 2F 2 is needed per bit of data.

Effect of temperature on Ga2O3(Gd2O3)/GaN metal–oxide–semiconductor field-effect transistors

Abstract: Ga2O3(Gd2O3) was deposited on GaN for use as a gate dielectric in order to fabricate a depletion metal–oxide–semiconductor field-effect transistor (MOSFET). Analysis of the effect of temperature on the device shows that gate leakage is significantly reduced at elevated temperature relative to a conventional metal–semiconductor field-effect transistor fabricated on the same GaN layer. MOSFET device operation in fact improved upon heating to 400 °C. Modeling of the effect of temperature on contact resistance suggests that the improvement is due to a reduction in the parasitic resistances present in the device.

Low power radio frequency transmitter with controllable gain

Abstract: A low power transmitter useful for vehicle remote keyless entry systems, for example, includes a transmitter circuit portion and a gain control circuit portion. The gain control circuit portion preferably includes an inductive load that introduces a resonant frequency that provides radio frequency gain control. The transmitter circuit portion preferably includes a transistor having a collector node and an emitter node. The gain controller circuit preferably includes a capacitive load coupled between the emitter node and the collector node of the transistor. The inductive load preferably is coupled between the emitter node of the transistor and ground.

Room Temperature-Operating Spin-Valve Transistors Formed by Vacuum Bonding

Abstract: Functional integration between semiconductors and ferromagnets was demonstrated with the spin-valve transistor. A ferromagnetic multilayer was sandwiched between two device-quality silicon substrates by means of vacuum bonding. The emitter Schottky barrier injected hot electrons into the spin-valve base. The collector Schottky barrier accepts only ballistic electrons, which makes the collector current very sensitive to magnetic fields. Room temperature operation was accomplished by preparing Si-Pt-Co-Cu-Co-Si devices. The vacuum bonding technique allows the realization of many ideas for vertical transport devices and forms a permanent link that is useful in demanding adhesion applications.

Gate insulated field effect transistors and method of manufacturing the same

Abstract: A thin film field effect transistors and manufacturing method for the same are described. The channel region of the transistor is spoiled by an impurity such as oxygen, carbon, nitrogen. The photosensitivity of the channel region is reduced by the spoiling impurity and therefore the transistor is endowed with immunity to illumination incident thereupon which would otherwise impair the normal operation of the transistor. The spoiling impurity is not introduced into transistors which are located in order not to receive light rays.

RTD/HFET low standby power SRAM gain cell

Abstract: A 50-nW standby power compound semiconductor tunneling-based static random access memory SRAM (TSRAM) cell is demonstrated by combining ultralow current-density resonant-tunneling diodes (RTDs) and heterostructure field-effect transistors (HFETs) in one integrated process on an InP substrate. This power represents over two orders of magnitude improvement over previous III-V static memory cells. By increasing the number of vertically integrated RTD's we obtain a 100 nW tri-state memory cell. The cell concept applies to any material system in which low current-density negative differential resistance devices are available.

Layout designing apparatus for integrated circuit, transistor size determining apparatus, circuit characteristic evaluating method, and transistor size determining method

Abstract: The present invention realizes the optimization of a transistor size with higher precision and in a shorter time, in designing a layout for an integrated circuit. A diffusion sharing estimation section estimates a diffusion-sharing region in the layout of the integrated circuit based on circuit data. A circuit characteristic evaluation section evaluates the characteristics, such as area, delay and power consumption, of the integrated circuit in accordance with the information about the diffusion-sharing region estimated by the diffusion sharing estimation section. A transistor size optimization section sets various size candidates for each of the transistors, which constitute the integrated circuit, provides these size candidates to the diffusion sharing estimation section and the circuit characteristic evaluation section, and then selects an optimum transistor size from the transistor size candidates thus set in accordance with the evaluation results obtained by the circuit characteristic evaluation section. Thus, a transistor size can be determined while taking the diffusion sharing into consideration. In addition, unlike a conventional method, it is no longer necessary to repeatedly re-determine a transistor size and perform a compaction.

OLED active matrix using a single transistor current mode pixel design

Abstract: The present invention is a current driver for an active matrix organic light emitting device display. As embodied herein, the driver relies upon a single transistor, driven in a saturation regime to provide a current source for an OLED. This results in a pulse drive. The driver of the present invention is compatible with high speed integrated drivers and can be fabricated on the same substrate as the OLED. A technique for driving an OLED is disclosed that will produce a good quality gray scale image.