Showing papers on "Transistor published in 1999"

Class AB H-bridge using current sensing MOSFETs

Abstract: An apparatus and method for supplying bi-directional load current to a load device. Four current sensing metal oxide semiconductor field effect transistors are operably configured to form an H-bridge with the load device, each transistor having separately insulated gate, source and drain and sense terminals with a source to drain conductivity determined in relation to a voltage applied to the gate terminal and a sense current from the sense terminal determined in relation to a magnitude of source to drain current. Drive voltages are applied to the gate terminals of alternating pairs of the transistors to apply the load current to the load device. The sense currents are used to provide adaptive, closed-loop clamping of the drive voltages at levels sufficient to maintain the non-load current conducting transistors in a quiescent state.

Method for printing of transistor arrays on plastic substrates

Abstract: Electronic devices such as transistors and diodes are manufactured by ink-jet printing using a transfer member. These electronic devices are used in addressing an electronic display.

Nitride based transistors on semi-insulating silicon carbide substrates

Abstract: A high electron mobility transistor (HEMT) is disclosed that includes a semi-insulating silicon carbide substrate, an aluminum nitride buffer layer on the substrate, an insulating gallium nitride layer on the buffer layer, an active structure of aluminum gallium nitride on the gallium nitride layer, a passivation layer on the aluminum gallium nitride active structure, and respective source, drain and gate contacts to the aluminum gallium nitride active structure.

Distortion in elementary transistor circuits

Abstract: In this paper the distortion components are defined for elementary transistor stages such as a single-transistor amplifier and a differential pair using bipolar transistors or MOSTs Moreover, the influence of feedback is examined Numerical examples are given for sake of illustration

A new RTD-FET logic family

Abstract: We describe a new family of clocked logic gates based on the resonant-tunneling diode (RTD). Pairs of RTDs form storage latches, and these are connected by networks consisting of field-effect transistors (FETs), saturated resistors, and RTDs. The design, operation, and expected performance of both a shift register and a matched filter using this logic are discussed. Simulations show that the RTD circuits can achieve higher performance in terms of speed and power in many signal processing applications. Compared to circuits using III-V FETs alone, the RTD circuits are expected to run nearly twice as fast at the same power or at the same speed with reduced power. Compared to circuits using Lincoln Laboratory's fully depleted silicon-on-insulator CMOS, implementation using state-of-the-art RTDs should operate five times faster when both technologies follow the CMOS design rules.

Image display device with element driving device for matrix drive of multiple active elements

Abstract: An image display device has multiple active elements arranged therein, such as an organic EL (Electro-Luminescence) element to matrix-drives these active elements. In the image display device, when a switching element is turned on with a control signal applied to a control electrode, a control current on a signal electrode is converted to a control voltage by a second transistor, held in a holding capacitor, and applied to a gate electrode of a first transistor. Thus, the signal electrode is applied with the control current, not with a control voltage, for controlling the operation of the active element. A drive voltage to be applied to a power supply electrode is converted to a drive current and supplied to the active element.

Fast organic thin-film transistor circuits

Abstract: We have fabricated organic thin-film transistors and integrated circuits using pentacene as the active material. Devices were fabricated on glass substrates using low-temperature ion-beam sputtered silicon dioxide as the gate dielectric and a double-layer photoresist process to isolate devices. These transistors have carrier mobility near 0.5 cm/sup 2//V-s and on/off current ratio larger than 10/sup 7/. Using a level-shifting design that allows circuits to operate over a wide range of threshold voltages, we have fabricated ring oscillators with propagation delay below 75 /spl mu/s per stage, limited by the level-shifting circuitry. When driven directly, inverters without level shifting show submicrosecond rise and fall time constants.

Spin-valve effects in a semiconductor field-effect transistor: A spintronic device

Abstract: We present a spintronic semiconductor field-effect transistor. The injector and collector contacts of this device were made from magnetic permalloy thin films with different coercive fields so that they could be magnetized either parallel or antiparallel to each other in different applied magnetic fields. The conducting medium was a two-dimensional electron gas (2DEG) formed in an AlSb/InAs quantum well. Data from this device suggest that its resistance is controlled by two different types of spin-valve effect: the first occurring at the ferromagnet-2DEG interfaces; and the second occurring in direct propagation between contacts.

Method of increasing the mobility of MOS transistors by use of localized stress regions

Abstract: A method of modifying the mobility of a transistor. First, a substance is implanted into a substrate. The substrate is then annealed such that the implanted substance forms at least one void in the substrate. Then, a transistor is formed on the substrate.

MOS transistor with assisted-gates and ultra-shallow “Psuedo” source and drain extensions for ultra-large-scale integration

Abstract: A MOS transistor and a method of fabricating the same for Ultra Large Scale Integration applications includes a composite gate structure. The composite gate structure is comprised of a main gate electrode and two assisted-gate electrodes disposed adjacent to and on opposite sides of the main gate electrode via an oxide layer. Areas underneath the two assisted-gate electrodes form ultra-shallow “pseudo” source/drain extensions. As a result, these extensions have a more shallow depth so as to enhance immunity to short channel effects.

Methods for designing standard cell transistor structures

Abstract: Disclosed are methods for designing standard cell transistor layouts for minimizing transistor delays and for minimizing power consumption. The method of minimizing transistor delays includes defining a transistor model for a P-type transistor and an N-type transistor of a CMOS standard cell. The method then includes minimizing a ratio between the P-type transistor and the N-type transistor. The ratio is defined by dividing a P-type gate width of the P-type transistor by an N-type gate width of the N-type transistor. The optimizing is performed by substantially minimizing an average delay for the transistor structure. In this embodiment, the CMOS standard cell will define a transistor structure that is implemented to make a logic circuit. The CMOS standard cell is one of a library of standard cells, where each standard cell defines a particular logic circuit.

Semiconductor memory device allowing high-speed operation of internal data buses

Abstract: A current mirror-type load circuit is provided for a global data line pair. A read gate amplifier used as a block select gate for each of the local data line pairs. A read gate amplifier includes a MOS transistor having its gate connected to a corresponding local data line. A data write driver writes the logic-inverted data of the write data upon equalization after the data write operation. A high-speed access becomes possible by reducing the time required for reading of data and by reducing the write recovery time.

Low-temperature polysilicon thin-film transistor driving with integrated driver for high-resolution light emitting polymer display

Abstract: A high-resolution low-temperature polysilicon thin-film transistor driven light emitting polymer display (LT p-Si TFT LEPD) with integrated drivers has been developed. We adopted conductance control of the TFT and optimized design and voltage in order to achieve good gray scale and simple pixel circuit. A p-channel TFT is used in order to guarantee reliability in dc bias. An inter-layer reduces parasitic capacitance of bus lines. Because of the combination of the LT p-Si TFT and LEP, the display is thin, compact, and lightweight, as well as having low power consumption, wide viewing angle, and fast response.

Low-leakage germanium-seeded laterally-crystallized single-grain 100-nm TFTs for vertical integration applications

Abstract: We report on 100-nm channel-length thin-film transistors (TFTs) that are fabricated using germanium-seeded lateral crystallization of amorphous silicon. Germanium seeding allows the fabrication of devices with control over grain boundary location. Its effectiveness improves with reduced device geometry, allowing "single-grain" device fabrication. In the first application of this technology to deep submicron devices, we report on 100-nm devices having excellent performance compared to conventional TFTs, which have randomly located grains. Devices have on-off ratio >10/sup 6/ and subthreshold slope of 107 mV/decade, attesting to the suitability of germanium-seeding for the fabrication of high-performance TFTs, suitable for use in vertically integrated three-dimensional (3-D) circuits.

Thin-film transistor circuitry with reduced sensitivity to variance in transistor threshold voltage

Abstract: A circuit design technique polysilicon thin-film transistor (TFT) circuitry produces circuits that are relatively less sensitive to threshold variations among the TFT's than circuits designed using conventional techniques. The circuit is designed such that thin-film transistors that are sensitive to threshold variations are made larger than other thin-film transistors in the circuitry to minimize threshold variations among similar transistors implemented in the circuit. In one embodiment, a pixel structure for an active matrix display device implemented in polysilicon includes two transistors, a select transistor and a drive transistor. The drive transistor in the pixel structure is a thin film metal oxide silicon (MOS) transistor that includes a gate to source capacitance sufficient to hold an electrical potential which keeps the transistor in a conducting state for an image field interval. One embodiment of the pixel structure includes only the select transistor and the drive transistor. The pixel storage capacitance is entirely realized by the gate to source capacitance of the drive transistor. Another embodiment of the pixel structure includes a capacitor which is much smaller than the capacitor of a conventional active matrix pixel structure. This capacitor holds the pixel in a non-illuminated state when the drive transistor is turned off. This pixel structure may be used with any display technology that uses an active matrix and stores image data on a capacitance in the pixel, including without limitation, organic light emitting diodes, electroluminescent devices, and inorganic light emitting diodes.

Fundamentals of III-V Devices: HBTs, MESFETs, and HFETs/HEMTs

Abstract: Basic Properties and Device Physics of III-V Materials. Two-Terminal Heterojunction Devices. HBT D.C. Characteristics. HBT High-Frequency Properties. FET D.C. Characteristics. FET High-Frequency Properties. Transistor Fabrication and Device Comparison. Appendices. Index.

DRAM sense amplifier for low voltages

Abstract: Structures and methods for improving sense amplifier operation are provided. A first embodiment includes a sense amplifier having a pair of cross-coupled inverters. Each inverter includes a transistor of a first conductivity type and a pair of transistors of a second conductivity type which are coupled at a drain region and are coupled at a source region. The drain region for the pair of transistors is coupled to a drain region of the transistor of the first conductivity type. A pair of input transmission lines are included where each one of the pair of input transmission lines is coupled to a gate of a first one of the pair of transistors in each inverter. A pair of output transmission lines is included where each one of the pair of output transmission lines is coupled to the drain region of the pair of transistors and the drain region of the transistor of the first conductivity type in each inverter. High performance, wide bandwidth or very fast CMOS amplifiers are possible using the new circuit topology of the present invention. The new modified sense amplifier for low voltage DRAMs is as much as 100 times faster than a conventional voltage sense amplifier when low power supply voltages, e.g. Vdd less than 1.0 Volts, are utilized. In the novel sense amplifier, the bit line capacitance is separated from the output nodes of the sense amplifier.

Active matrix light emitting diode display

Abstract: An active matrix pixel within an active matrix display includes a photodiode that is optically connected to a light emitting diode within the pixel in order to detect a portion of the luminous flux that is generated by the light emitting diode. The photodiode discharges excess charge within the pixel in response to the detected portion of luminous flux. Once the excess charge is discharged, the light emitting diode stops emitting light. In an embodiment, the gate of a drive transistor is controlled by the charge on a storage node. If the charge on the storage node sets a voltage that exceeds the threshold voltage of the drive transistor then the drive transistor conducts. The amount of charge on the storage node above that which is needed to set the threshold voltage is referred to as the excess charge.

A GaN/4H-SiC heterojunction bipolar transistor with operation up to 300°C

Abstract: We report on the fabrication and characterization of GaN/4H-SiC n-p-n heterojunction bipolar transistors (HBTs). The device structure consists of an n-SiC collector, p-SiC base, and selectively grown n-GaN emitter. The HBTs were grown using metalorganic chemical vapor deposition on SiC substrates. Selective GaN growth through a SiO2 mask was used to avoid damage that would be caused by reactive ion etching. In this report, we demonstrate common base transistor operation with a modest dc current gain of 15 at room temperature and 3 at 300°C.

AlGaN/GaN heterojunction bipolar transistor

Abstract: We demonstrate the first GaN bipolar transistor. An AlGaN/GaN HBT structure was grown by MOCVD on c-plane sapphire substrate. The emitter was grown with an Al/sub 0.1/Ga/sub 0.9/N barrier to increase the emitter injection efficiency. Cl/sub 2/ RIE was used to pattern the emitter mesa, and selectively regrown base contact pads were implemented to reduce a contact barrier associated with RIE etch damage to the base surface. The current gain of the devices was measured to be as high as three with a base width of 200 nm. DC transistor characteristics were measured to 30 V V/sub CE/ in the common emitter configuration, with an offset voltage of 5 V. A gummel plot and base contact characteristics are also presented.

Semiconductor device and method for fabricating the same

Abstract: A semiconductor device includes at least one thin-film transistor, which includes a semiconductor layer, a gate electrode and a gate insulating film In the semiconductor layer, a crystalline region, including a channel forming region, a source region and a drain region, is defined The gate electrode is provided to control the conductivity of the channel forming region The gate insulating film is provided between the gate electrode and the semiconductor layer The semiconductor layer includes a gettering region outside of the crystalline region thereof

Transistor circuit, display panel and electronic apparatus

Abstract: A transistor circuit is provided including a driving transistor where conductance between the source and the drain is controlled in response to a supplied voltage, and a compensating transistor where the gate is connected to one of the source and the drain, the compensating transistor being connected so as to supply input signals to the gate of the driving transistor through the source and drain. In a transistor circuit where conductance control in a driving transistor is carried out in response to the voltage of input signals, it is possible to control the conductance by using input signals of a relatively low voltage and a variance in threshold characteristics of driving transistors is compensated. With this transistor circuit, a display panel that can display picture images with reduced uneven brightness is achieved.

Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk. SOI and thin film structures and method of forming same

Abstract: A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS transistors on the vertical surfaces thereof. The complementary NMOS and PMOS transistors form a CMOS transistor pair. The transistors are preferably used in structures such as memory circuits, e.g., DRAMs, which are, in turn, used in a processor-based system. Ideally, the deep sub-micron NMOS and PMOS transistors are operated in velocity saturation for optimal switching operation.

Display comprising organic smart pixels

Abstract: A display apparatus according to our invention comprises a multiplicity of nominally identical smart pixels, a given pixel comprising an organic light emitting diode and an organic or inorganic (e.g., amorphous or polycrystalline Si) pixel FET. The display also comprises drive/compensation circuitry adapted for mitigating or eliminating non-idealities associated with the organic components. Among the non-idealities are variations in mobility and/or threshold voltage of the pixel FET from transistor to transistor, change in mobility and/or threshold voltage with time in a given pixel FET, change over time of the LED characteristics, capacitive signal feed-through through the gate insulator of the pixel FETs by short rise/fall time pulses, poor on-off ratio of the pixel FET, and charge leakage through the gate dielectric. Exemplary drive/compensation circuitry is disclosed.

Body contacted dynamic memory

Abstract: A dynamic memory circuit in which the inherent bipolar transistor effect within a floating body transistor is utilized to store an information bit. A floating body of a storage transistor stores an information bit in the form of an electric charge. The floating body is charged and discharged via an access transistor during data write operations. The inherent bipolar transistor resident within the floating body transistor increases the effective capacitance of the floating body which acts as the storage node, and thereby enhances the magnitude of the discharge current which represents the stored information bit during read operations.

A new dynamic electro-thermal nonlinear model for silicon RF LDMOS FETs

Abstract: The development and behavior of a new model for Motorola's LDMOS transistor is described. The model includes self-heating effects, produces accurate small-signal simulations as well as large-signal, harmonic-balance simulations and also operates in the transient mode. It is simpler than previous models, yet it accurately predicts mixed signal effects, such as intermodulation distortion.

Measurement of drift mobility in AlGaN/GaN heterostructure field-effect transistor

Abstract: Low-field mobilities for electrons in the channel of an Al0.15Ga0.85N/GaN heterostructure field-effect transistor are derived from direct current transistor characteristics. The dependencies of mobility on gate bias, sheet carrier concentration, and temperature are obtained. For negative gate bias voltages, mobility is found to increase monotonically with increasing sheet carrier concentration, which we interpret as a consequence of increased screening of carrier scattering. For positive gate bias voltages, mobility is found to decrease with increasing gate bias due to the onset of parallel conduction in the AlGaN barrier layer. The mobility varies approximately as T−α with α≈1.6–1.8 for temperature ranging from 200 to 400 K, indicating that phonon scattering is dominant in the two-dimensional electron gas in this temperature range.

High-voltage-tolerant I/O buffers with low-voltage CMOS process

Abstract: This paper presents high-voltage-tolerant I/O buffer designs for a 1.9-V external cache interface and a 3.3-V system interface using 1.9-V MOS transistors in a 0.21-/spl mu/m process with 40-/spl Aring/ gate-oxide thickness. Various circuit techniques are used for 1.9- and 3.3-V I/O buffers to ensure that the voltage across the gate oxide of every MOS element is below specified limits of 2.2 V for transient (short duty cycle) and 1.9 V for steady state. Only one PMOS pullup driver transistor between the bond pad and the power supply, and one NMOS pulldown driver transistor between the bond pad and ground, are used for the 1.9-V I/O buffer design, while cascoded MOS transistors between the bond pad and power supply or ground terminals are used for the 3.3-V I/O buffer design. The primary design goal is to ensure the reliability of MOS elements by avoiding excessive gate oxide stress due to high electric fields. However, due to differences in requirements for speed, power-supply voltage, and tristate leakage current, completely different circuit techniques have been used for the two designs. Both of the designs have been successfully implemented in a 400-MHz UltraSPARC microprocessor.

Power semiconductor device

Abstract: PROBLEM TO BE SOLVED: To reliably make overcurrent protection of a power transistor, by suppressing the dispersion in the maximum value of a load current. SOLUTION: A power PNP transistor 18 is fixed onto and electrically connected to a surface 16 of a metal radiating plate 15 through a platelike resistor 17. Further, a controlling integrated circuit device 20 is fixed onto the surface 16 through an electrically insulating paste 19, and the resistor 17, the transistor 18 and the device 20 are connected using thin metal wires 42 to 44. A load current Io from an input terminal flows from the emitter to the collector of the transistor 18, and further flows through the resistor 17 in a thickness direction to reach the plate 15. The device 20 detects a voltage across the resistor 17 corresponding to the current Io between the plate 15 and the surface of the resistor 17 on the side of the transistor 18. When such voltage becomes high, the device 20 excessively changes the impedance of the transistor 18 to suppress an overcurrent.