Showing papers on "Transistor published in 2002"

Carbon nanotubes as schottky barrier transistors.

Abstract: We show that carbon nanotube transistors operate as unconventional "Schottky barrier transistors," in which transistor action occurs primarily by varying the contact resistance rather than the channel conductance. Transistor characteristics are calculated for both idealized and realistic geometries, and scaling behavior is demonstrated. Our results explain a variety of experimental observations, including the quite different effects of doping and adsorbed gases. The electrode geometry is shown to be crucial for good device performance.

Transparent thin film field effect type transistor using homologous thin film as active layer

Abstract: PROBLEM TO BE SOLVED: To solve the problem that in ZnO as a transparent oxide semiconductor, it is difficult to reduce an electric conductivity and it is impossible to constitute a normally off field effect type transistor, or as it is difficult to form an amorphous state, an amorphous transistor adaptive for a large area cannot be manufactured. SOLUTION: In a homologous compound InMO 3 (ZnO) m (M=In, Fe, Ga or Al; m=an integer of 1 to 49) single crystal thin film manufactured by a reactive solid-phase epitaxial method, a deviation from a stoichiometry is very small and a good insulator is obtained near room temperatures. By using the homologous compound single crystal InMO 3 (ZnO) m (M=In, Fe, Ga or Al; m=an integer of 1 to 49) thin film as an active layer, a transparent thin film field effect type transistor having a good switching characteristic can be manufactured by a normally off operation. COPYRIGHT: (C)2004,JPO

High-κ dielectrics for advanced carbon- nanotube transistors and logic gates

Abstract: The integration of materials having a high dielectric constant (high-kappa) into carbon-nanotube transistors promises to push the performance limit for molecular electronics. Here, high-kappa (approximately 25) zirconium oxide thin-films (approximately 8 nm) are formed on top of individual single-walled carbon nanotubes by atomic-layer deposition and used as gate dielectrics for nanotube field-effect transistors. The p-type transistors exhibit subthreshold swings of S approximately 70 mV per decade, approaching the room-temperature theoretical limit for field-effect transistors. Key transistor performance parameters, transconductance and carrier mobility reach 6,000 S x m(-1) (12 microS per tube) and 3,000 cm2 x V(-1) x s(-1) respectively. N-type field-effect transistors obtained by annealing the devices in hydrogen exhibit S approximately 90 mV per decade. High voltage gains of up to 60 are obtained for complementary nanotube-based inverters. The atomic-layer deposition process affords gate insulators with high capacitance while being chemically benign to nanotubes, a key to the integration of advanced dielectrics into molecular electronics.

Beyond the conventional transistor

Abstract: This paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials. Starting from an analysis of the sources of improvements in device performance, we present technology options for achieving these performance enhancements. These options include high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET, and strained-silicon FET. Nanotechnology is examined in the context of continuing the progress in electronic systems enabled by silicon microelectronics technology. The carbon nanotube field-effect transistor is examined as an example of the evaluation process required to identify suitable nanotechnologies for such purposes.

High-Mobility Nanotube Transistor Memory

Abstract: A high-mobility (9000 cm2/V·s) semiconducting single-walled nanotube transistor is used to construct a nonvolatile charge-storage memory element operating at room temperature. Charges are stored by application of a few volts across the silicon dioxide dielectric between nanotube and silicon substrate, and detected by threshold shift of the nanotube field-effect transistor. The high mobility of the nanotube transistor allows the observation of discrete configurations of charge corresponding to rearrangement of a single or few electrons. These states may be reversibly written, read, and erased at temperatures up to 100 K.

Essential physics of carrier transport in nanoscale MOSFETs

Abstract: The device physics of nanoscale MOSFETs is explored by numerical simulations of a model transistor. The physics of charge control, source velocity saturation due to thermal injection, and scattering in ultrasmall devices are examined. The results show that the essential physics of nanoscale MOSFETs can be understood in terms of a conceptually simple scattering model.

I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q

Abstract: One of the "fundamental" problems in the continued scaling of MOSFETs is the 60 mV/decade room temperature limit in subthreshold slope. In this paper, we report initial studies on a new kind of transistor, the I-MOS. The I-MOS uses modulation of the breakdown voltage of a gated p-i-n structure in order to switch from the OFF to the ON state and vice versa. Since impact-ionization is an abrupt function of the electric field (or the carrier energy), simulations show that the device has a subthreshold slope much lower than kT/q. Simulations also show that it is indeed possible to make complementary circuits with switching speeds comparable to or exceeding CMOS. Experimental results on a silicon based prototype verify the basic concept and show very steep subthreshold slopes with high speed turn-on and turn-off. Lower bandgap materials are also being investigated to reduce the value of the breakdown voltage and permit lower voltage operation.

SiC power-switching devices-the second electronics revolution?

Abstract: Silicon carbide (SiC) offers significant advantages for power-switching devices because the critical field for avalanche breakdown is about ten times higher than in silicon. SiC power devices have made remarkable progress in the past five years, demonstrating currents in excess of 100 A and blocking voltages in excess of 19000 V. In this paper we describe the latest progress in three classes of SiC devices: diodes (p-i-n and Schottky), transistors (junction field-effect transistor, metal-oxide-semiconductor field-effect transistor, and bipolar junction transistor), and thyristors (gate turn-off).

Memory design using one-transistor gain cell on SOI

Abstract: A 512-kb memory has been developed featuring a one-transistor gain cell of size 7F/sup 2/ (F = 0.18 /spl mu/m) on SOI. The cell named the floating body transistor cell (FBC) has the ability to achieve a 4F/sup 2/ cell using self-aligned contact technologies and is proved to be scalable with respect to a cell signal. A basic operation was verified by device simulation and hardware measurement. An array driving method is disclosed which makes selective write possible. A cell signal sensing system consisting of a pair of reference cells written opposite data and comparing the combined current with the doubled cell current is shown to be robust against cell parameter variations in process and temperature. A random access time of 40 ns was simulated. Nondestructive readout and C/sub b//C/sub s/. free signal development drastically improve cell efficiency.

Process for making and programming and operating a dual-bit multi-level ballistic flash memory

Abstract: An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate. In addition to the dual-bit nature of the cell, density can be even further improved by multi-level storage. In one embodiment, the dual multi-level structure is applied to the ballistic step split gate side wall transistor. In a second embodiment, the dual multi-level structure is applied to the ballistic planar split gate side wall transistor. Both types of ballistic transistors provide fast, low voltage programming. The control gates are used to override or suppress the various threshold voltages on associated floating gates, in order to program to and read from individual floating gates. The targets for this non-volatile memory array are to provide the capabilities of high speed, low voltage programming (band width) and high density storage.

Carrier transport and density of state distributions in pentacene transistors

Abstract: We present a density of state model for the transport properties of pentacene field effect transistors. Using a one-dimensional transistor model we study the effect of different localized trap distributions on the current-voltage characteristics of such devices. We find that a distributed trap model with a steep exponential band tail of donors and a shallower exponential tail of acceptors inside the band gap can describe consistently our experimental data obtained from bottom-gate polycrystalline pentacene transistors for different gate dielectrics and under various external conditions.

Contact effects in polymer transistors

Abstract: Polymer thin film transistors based on the polyfluorene F8T2 exhibit a nonohmic contact resistance, particularly when in the coplanar device geometry. We show how to obtain the current–voltage relation for the contact from the transistor output characteristics measured with different channel lengths. The diode-type relation is attributed to the contact injection properties of the metal Schottky barrier. No significant increase in mobility with gate or drain field is observed.

Light emitting diode driver

Abstract: A LED driver (10) is disclosed. The LED driver (10) includes a high frequency inverter (20) and an impedance circuit (30). The high frequency inverter (20) operates to produce a high frequency voltage source whereby the impedance circuit (30) directs a flow of alternating current through a LED array (40) including one or more anti-parallel LED pairs, one or more anti-parallel LED strings, and/or one or more anti-parallel LED matrixes. A transistor (T3) can be employed to divert the flow of the alternating current from the LED array (40), or to vary the flow of the alternating current through LED array (40).

An all-organic sensor-transistor based on a novel electrochemical transducer concept printed electrochemical sensors on paper

Abstract: A novel transducer concept based on an organic electrochemical transistor is described. Its function as an integral part of an air humidity sensor, in which the proton conductor Nafion acts as sensitivity layer has been realised. The resulting electrochemical sensor–transistor, based on the conducting polymer PEDOT:PSS, operates at low voltages, on the order of 1 V. The sensor response, measured as the drain–source current of the electrochemical transistor, versus air humidity, has a close to exponential behaviour. The sensor can be realised using exclusively printing and coating fabrication techniques. Here, we demonstrate devices realised on plastic foils and on ordinary coated fine paper substrates. This organic electrochemical transducer promise future applications such as all-integrated low-cost sensor tags for single-use chemical sensors.

Driving circuit for current control element and image display device

Abstract: PROBLEM TO BE SOLVED: To eliminate the influence of variance in the threshold characteristic of a driving transistor. SOLUTION: The disclosed driving circuit for the current control element has the driving transistor 6 and current control element 7 which are connected in series between a power line 1 and a ground line 2, a hold capacitor 5 which is connected between the connection point between the driving transistor 6 and current control element 7 and the gate electrode of the driving transistor 6, and a select gate transistor 4 which is connected between a signal line 3 and the gate electrode of the driving transistor 6. Then the driving circuit turns on the select gate transistor 4 in a selection period to input a 1st signal voltage from the signal line 3, inputs and holds a 2nd signal voltage from the signal line 3 in the hold capacitor 5 after discharging signal charges written to the hold capacitor 5 through the driving transistor 6, and turns off the select gate transistor 4 in a non-selection period to supply a current to the current control element 7 through the driving transistor 6. COPYRIGHT: (C)2003,JPO

The toughest transistor yet [GaN transistors]

Abstract: GaN transistors withstand extreme heat and are capable of handling frequencies and power levels well beyond those possible with silicon, gallium arsenide, silicon carbide, or essentially any other semiconductor yet fabricated. Frequency and power-handling capabilities of this caliber could make all the difference in amplifiers, modulators, and other key components of the advanced communications networks. GaN transistors could double or triple the efficiency of base-station amplifiers, so that a given area could be covered by fewer base stations or, more likely, be flooded with more data at much higher rates. These same characteristics of speed, high-power handling, and heat resistance would also suit the transistors for many other uses.

Leakage control with efficient use of transistor stacks in single threshold CMOS

Abstract: The state dependence of leakage can be exploited to obtain modest leakage savings in complementary metal-oxide-semiconductor (CMOS) circuits. However, one can modify circuits considering state dependence and achieve larger savings. We identify a low-leakage state and insert leakage-control transistors only where needed. Leakage levels are on the order of 35% to 90% lower than those obtained by state dependence alone. Using a modified standard-cell-design flow, area overhead for combinational logic was found to be on the order of 18%. The proposed technique minimizes performance impact, does not require multiple-threshold voltages, and supports a standard-cell-design flow.

SiC and GaN transistors - is there one winner for microwave power applications?

Abstract: Wide bandgap semiconductors show promise for high-power microwave electronic devices. Primarily due to low breakdown voltage, it has not been possible to design and fabricate solid-state transistors that can yield radio-frequency (RF) output power on the order of hundreds to thousands of watts. This has severely limited their use in power applications. Recent improvements in the growth of wide bandgap semiconductor materials, such as SiC and the GaN-based alloys, provide the opportunity to now design and fabricate microwave transistors that demonstrate performance previously available only from microwave tubes. The most promising electronic devices for fabrication in wide bandgap semiconductors for these applications are metal-semiconductor field-effect transistors (MESFETs) fabricated from the 4H-SiC polytype and heterojunction field-effect transistors (HFETs) fabricated using the AlGaN/GaN heterojunction. These devices can provide RF output power on the order of 5-6 W/mm and 10-12 W/mm of gate periphery, respectively. 4H-SiC MESFETs should produce useful performance at least through X band and AlGaN/GaN HFETs should produce useful performance well into the millimeter-wave region, and potentially as high as 100 GHz.

Resonant detection of subterahertz radiation by plasma waves in a submicron field-effect transistor

Abstract: The resonant detection of subterahertz radiation by two-dimensional electron plasma confined in a submicron gate GaAs/AlGaAs field-effect transistor is demonstrated. The results show that the critical parameter that governs the sensitivity of the resonant detection is ωτ, where ω is the radiation frequency and τ is the momentum scattering time. By lowering the temperature and hence increasing τ and increasing the detection frequency ω, we reached ωτ∼1 and observed resonant detection of 600 GHz radiation in a 0.15 μm gate length GaAs field-effect transistor. The evolution of the observed photoresponse signal with temperature and frequency is reproduced well within the framework of a theoretical model.

Nanotechnology goals and challenges for electronic applications

Abstract: Si metal-oxide-semiconductor field-effect transistor (MOSFET) scaling trends are presented along with a description of today's 0.13-/spl mu/m generation transistors. Some of the foreseen limits to future scaling include increased subthreshold leakage, increased gate oxide leakage, increased transistor parameter variability and interconnect density and performance. Basic device and circuit requirements for electronic logic and memory products are described. These requirements need to be kept in mind when evaluating nanotechnology options such as carbon nanotube field-effect transistors (FETs), nanowire FETs, single electron transistors and molecular devices as possible future replacements for Si MOSFETs.

Determination of channel temperature in AlGaN/GaN HEMTs grown on sapphire and silicon substrates using DC characterization method

Abstract: Self-heating effects and temperature rise in AlGaN/GaN HEMTs grown on silicon and sapphire substrates are studied, exploiting transistor DC characterization methods A negative differential output resistance is observed for high dissipated power levels An analytical formula for a source-drain current drop as a function of parasitic source resistance and threshold voltage changes is proposed to explain this behavior The transistor source resistance and threshold voltage is determined experimentally at different elevated temperatures to construct channel temperature versus dissipated power transfer characteristic It is found that the HEMT channel temperature increases rapidly with dissipated power and at 6 W/mm reaches values of /spl sim/320/spl deg/C for sapphire and /spl sim/95/spl deg/C for silicon substrate, respectively

High-voltage lateral transistor with a multi-layered extended drain structure

Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

Organic oscillator and adaptive amplifier circuits for chemical vapor sensing

Abstract: Organic transistor based circuits that can be employed for chemical vapor sensing, are described. Such circuits have improved sensing characteristics in comparison with discrete transistor based sensors. Complementary ring oscillator based sensors have a stronger response to analytes such as octanol and allyl propionate compared to a single transistor. A fabrication process that combines organic semiconductor circuitry with Si is described. The design and advantages of adaptive differential amplifiers with high gain and feedback are described. Voltage gains of ∼20 allow the detection of weak odorant inputs and the adaptive feedback allows for improved background elimination.

An MOS transistor model for RF IC design valid in all regions of operation

Abstract: This paper presents an overview of MOS transistor modeling for RF integrated circuit design. It starts with the description of a physical equivalent circuit that can easily be implemented as a SPICE subcircuit. The MOS transistor is divided into an intrinsic part, representing mainly the active part of the device, and an extrinsic part responsible for most of the parasitic elements. A complete charge-based model of the intrinsic part is presented. The main advantage of this new charge-based model is to provide a simple and coherent description of the DC, AC, nonquasi-static (NQS), and noise behavior of the intrinsic MOS that is valid in all regions of operation. It is based on the forward and reverse charges q/sub f/ and q/sub r/ defined as the mobile charge densities, evaluated at the source and at the drain. This intrinsic model also includes a new simplified NQS model that uses a bias and frequency normalization allowing one to describe the high-order frequency behavior with only two simple functions. The extrinsic model includes all the terminal access series resistances, and particularly the gate resistance, the overlap, and junction capacitances as well as a substrate network. The latter is required to account for the signal coupling occurring at RF from the drain to the source and the bulk, through the junction capacitances. The noise model is then presented, including the effect of the substrate resistances on the RF noise parameters. All the aspects of the model are validated for a 0.25-/spl mu/m CMOS process.

Electrical Interfacing of Nerve Cells and Semiconductor Chips

Abstract: The electrical interfacing of individual nerve cells and silicon microstructures is considered, as well as the assembly of elementary hybrid systems made of neuronal networks and semiconductor microelectronics. Without electrochemical processes, coupling of the electron-conducting semiconductor and the ion-conducting neurons relies on a close contact of cell membrane and oxidised silicon with a high resistance of the junction and a high conductance of the attached membrane. Neuronal excitation can be elicited and recorded from the chip by capacitive contacts and by field-effect transistors with an open gate. Integrated iono-electronic system are obtained by the outgrowth of neuronal networks on the surface of the silicon chip, by implementing electrical circuits in the chip and by two-way interfacing of the neuronal and the electronic components.

Impact of negative bias temperature instability on digital circuit reliability

Abstract: We have examined the impact of NBTI degradation on digital circuits through the stressing of ring oscillator circuits. By subjecting the circuit to pMOS NBTI stress, we have unambiguously determined the circuit reliability impact of NBTI. We demonstrate that the relative frequency degradation of the NBTI stressed ring oscillator increases as the voltage at operation decreases. This behavior can be explained by reduced transistor gate overdrive and reduced voltage headroom at the circuit level. We present evidence that donor interface state generation during NBTI stress is a significant component of the transistor degradation. Furthermore, we show that the Static Noise Margin of a SRAM memory cell is degraded by NBTI and the relative degradation increases as the operating voltage decreases.

A compact scattering model for the nanoscale double-gate MOSFET

Abstract: An analytically compact model for the nanoscale double gate metal-oxide semiconductor field effect transistor (MOSFET) based on McKelvey's flux theory is developed. The model is continuous above and below threshold and from the linear to saturation regions. Most importantly, it describes nanoscale MOSFETs from the diffusive to ballistic regimes. In addition to its use in exploring the limits and circuit applications of double gate MOSFETs, the model also serves as an example of how semiclassical scattering theory can be used to develop physically sound models for nanoscale transistors.

Subthreshold characteristics of field effect transistors based on poly(3-dodecylthiophene) and an organic insulator

Abstract: The properties of field effect transistors with organic insulator and semiconducting regions, fabricated with a top-gate architecture, have been investigated. Thin films (d≈30 nm) of regioregular poly(3-dodecylthiophene) were employed as the active semiconductor and the gate insulator was formed by a 500-nm-thick layer of poly(4-vinylphenol). Both were solution-processed on top of poly(ethylenetherephthalate) films, which were used as substrates. The output characteristics show a pronounced saturation behavior with an unconventional nonquadratic saturation current dependence on the gate voltage. Hence the (hole) mobility of 0.002–0.005 cm2/Vs has been estimated from the linear region of the transfer characteristics. The transistor turn-on occurs at a threshold voltage of approximately Vth=0 V, and the device can be operated with a supply voltage of between 15 and 20 V. As is usually observed for organic transistors, the inverse subthreshold slope (S) is very high, in our case S≈7 V/dec, by contrast with S...

Gate array core cell for VLSI ASIC devices

Abstract: A very efficient gate array core cell in which the base core cell consists of a group of 6 PMOS transistors and a group of 6 NMOS transistors. It also includes pre-wiring of 2 of the 6 PMOS transistors, with 2 of the 6 NMOS transistors at polysilicon level or at local interconnect level while leaving the remaining PMOS and NMOS transistors as individual transistors to be interconnected during the functional ASIC metallization process. The core cell also has 2 polysilicon or local interconnect wires embedded in it, which can be used to interconnect transistors for logic function implementation. The core cell defined in this invention is highly flexible and has been analyzed to interconnect all types of logic and memory functions needed for ASIC designs. The layout of the transistors, pre-wiring of the strategic transistors at polysilicon level or at local interconnect level, and embedded polysilicon or local interconnect wires reduce the core cell size significantly. This core cell design reduces the overall wiring lengths, parasitic capacitance, which in turn reduce delays, power dissipation and increase ASIC performance and circuit density. Gate array ASIC components designed using this core cell provide circuit density, performance and power dissipation characteristics comparable to the Standard Cell ASICs but with the advantage of reducing the mask cost and processing time by about 50 percent.

El display panel and el display apparatus comprising it

Abstract: In a source driver (14) which an EL display apparatus comprises, the gate voltage of the first-stage current source by a transistor (631) is impressed on the gate of an adjacent transistor (632a) of the second-stage current source. As a result, a current flowing through the transistor (632a) is delivered to a transistor (632b) of the second-stage current source. The gate voltage by the transistor (632b) of the second-stage current source is impressed on the gate of a transistor (633a) of the third-stage current source. As a result, a current flowing through the transistor (633a) is delivered to a transistor (633b) of the third-stage current source. The gate of the transistor (633b) of the third-stage current source is provided with many current sources (634) according to a necessary number of bits.