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Showing papers on "Transistor published in 2004"


Journal ArticleDOI
25 Nov 2004-Nature
TL;DR: A novel semiconducting material is proposed—namely, a transparent amorphous oxide semiconductor from the In-Ga-Zn-O system (a-IGZO)—for the active channel in transparent thin-film transistors (TTFTs), which are fabricated on polyethylene terephthalate sheets and exhibit saturation mobilities and device characteristics are stable during repetitive bending of the TTFT sheet.
Abstract: Transparent electronic devices formed on flexible substrates are expected to meet emerging technological demands where silicon-based electronics cannot provide a solution. Examples of active flexible applications include paper displays and wearable computers1. So far, mainly flexible devices based on hydrogenated amorphous silicon (a-Si:H)2,3,4,5 and organic semiconductors2,6,7,8,9,10 have been investigated. However, the performance of these devices has been insufficient for use as transistors in practical computers and current-driven organic light-emitting diode displays. Fabricating high-performance devices is challenging, owing to a trade-off between processing temperature and device performance. Here, we propose to solve this problem by using a novel semiconducting material—namely, a transparent amorphous oxide semiconductor from the In-Ga-Zn-O system (a-IGZO)—for the active channel in transparent thin-film transistors (TTFTs). The a-IGZO is deposited on polyethylene terephthalate at room temperature and exhibits Hall effect mobilities exceeding 10 cm2 V-1 s-1, which is an order of magnitude larger than for hydrogenated amorphous silicon. TTFTs fabricated on polyethylene terephthalate sheets exhibit saturation mobilities of 6–9 cm2 V-1 s-1, and device characteristics are stable during repetitive bending of the TTFT sheet.

7,301 citations


Journal ArticleDOI
12 Mar 2004-Science
TL;DR: This method, which eliminates exposure of the fragile organic surface to the hazards of conventional processing, enables fabrication of rubrene transistors with charge carrier mobilities as high as ∼15 cm2/V·s and subthreshold slopes as low as 2nF·V/decade·cm2.
Abstract: We introduce a method to fabricate high-performance field-effect transistors on the surface of freestanding organic single crystals. The transistors are constructed by laminating a monolithic elastomeric transistor stamp against the surface of a crystal. This method, which eliminates exposure of the fragile organic surface to the hazards of conventional processing, enables fabrication of rubrene transistors with charge carrier mobilities as high as approximately 15 cm2/V.s and subthreshold slopes as low as 2nF.V/decade.cm2. Multiple relamination of the transistor stamp against the same crystal does not affect the transistor characteristics; we exploit this reversibility to reveal anisotropic charge transport at the basal plane of rubrene.

1,593 citations


Journal ArticleDOI
TL;DR: Flexible active-matrix monochrome electrophoretic displays based on solution-processed organic transistors on 25-μm-thick polyimide substrates based on 1,888 transistors are demonstrated, which are the largest organic integrated circuits reported to date.
Abstract: At present, flexible displays are an important focus of research1,2,3 Further development of large, flexible displays requires a cost-effective manufacturing process for the active-matrix backplane, which contains one transistor per pixel One way to further reduce costs is to integrate (part of) the display drive circuitry, such as row shift registers, directly on the display substrate Here, we demonstrate flexible active-matrix monochrome electrophoretic displays based on solution-processed organic transistors on 25-μm-thick polyimide substrates The displays can be bent to a radius of 1 cm without significant loss in performance Using the same process flow we prepared row shift registers With 1,888 transistors, these are the largest organic integrated circuits reported to date More importantly, the operating frequency of 5 kHz is sufficiently high to allow integration with the display operating at video speed This work therefore represents a major step towards 'system-on-plastic'

1,577 citations


Journal ArticleDOI
TL;DR: In this paper, the authors reported high performance ZnO thin-film transistor (ZnO-TFT) fabricated by rf magnetron sputtering at room temperature with a bottom gate configuration.
Abstract: We report high-performance ZnO thin-film transistor (ZnO-TFT) fabricated by rf magnetron sputtering at room temperature with a bottom gate configuration. The ZnO-TFT operates in the enhancement mode with a threshold voltage of 19V, a saturation mobility of 27cm2∕Vs, a gate voltage swing of 1.39V∕decade and an on/off ratio of 3×105. The ZnO-TFT presents an average optical transmission (including the glass substrate) of 80% in the visible part of the spectrum. The combination of transparency, high mobility, and room-temperature processing makes the ZnO-TFT a very promising low-cost optoelectronic device for the next generation of invisible and flexible electronics.

1,499 citations


Patent
14 Jun 2004
TL;DR: In this paper, thin-film transistors and circuits with indium oxide-based channel layers are presented for the fabrication of flexible and transparent substrates for electronic display and imaging applications.
Abstract: In electronic displays or imaging units, the control of pixels is achieved by an array of transistors. These transistors are in a thin film form and arranged in a two-dimensional configuration to form switching circuits, driving circuits or even read-out circuits. In this invention, thin film transistors and circuits with indium oxide-based channel layers are provided. These thin film transistors and circuits may be fabricated at low temperatures on various substrates and with high charge carrier mobilities. In addition to conventional rigid substrates, the present thin film transistors and circuits are particularly suited for the fabrication on flexible and transparent substrates for electronic display and imaging applications. Methods for the fabrication of the thin film transistors with indium oxide-based channels are provided.

1,149 citations


Journal ArticleDOI
TL;DR: A class of liquid crystalline regioregular polythiophenes, PQTs, that possess sufficient air stability to enable achievement of excellent TFT properties under ambient conditions and will help bring the long-standing concept of low-cost organic/polymer transistor circuits closer to commercial reality.
Abstract: Conjugated polymers have been widely studied as potential semiconductor materials for organic thin-film transistors (TFTs). However, they have provided functionally poor transistor properties when the TFTs are fabricated in air. We have developed a class of liquid crystalline regioregular polythiophenes, PQTs, that possess sufficient air stability to enable achievement of excellent TFT properties under ambient conditions. These polythiophenes exhibit unique self-assembly ability and form highly structured thin films when deposited from solution under appropriate conditions. TFTs fabricated in air with PQT channel layers have provided high field-effect mobility to 0.14 cm2 V-1 s-1 and high current modulation to over 107, together with other desirable transistor properties. These high-performance polythiophenes will therefore help bring the long-standing concept of low-cost organic/polymer transistor circuits closer to commercial reality.

1,029 citations


Journal ArticleDOI
TL;DR: In this paper, the authors describe the evolution and properties of a new class of MOSFETs, called triple-plus (3 + )-gate devices, which offer a practical solution to the problem of the ultimate, yet manufacturable, silicon MOS-FET.
Abstract: In an ever increasing need for higher current drive and better short-channel characteristics, silicon-on-insulator MOS transistors are evolving from classical, planar, single-gate devices into three-dimensional devices with multiple gates (double-, triple- or quadruple-gate devices). The evolution and the properties of such devices are described and the emergence of a new class of MOSFETs, called triple-plus (3 + )-gate devices offer a practical solution to the problem of the ultimate, yet manufacturable, silicon MOSFET.

878 citations


Journal ArticleDOI
21 Oct 2004-Nature
TL;DR: This work demonstrates a manufacturing process for TFTs with a 2.5-nm-thick molecular self-assembled monolayer (SAM) gate dielectric and a high-mobility organic semiconductor (pentacene), which operate with supply voltages of less than 2 V yet have gate currents that are lower than those of advanced silicon field-effect transistors with SiO2 dielectrics.
Abstract: Organic thin film transistors (TFTs) are of interest for a variety of large-area electronic applications, such as displays, sensors and electronic barcodes. One of the key problems with existing organic TFTs is their large operating voltage, which often exceeds 20 V. This is due to poor capacitive coupling through relatively thick gate dielectric layers: these dielectrics are usually either inorganic oxides or nitrides, or insulating polymers, and are often thicker than 100 nm to minimize gate leakage currents. Here we demonstrate a manufacturing process for TFTs with a 2.5-nm-thick molecular self-assembled monolayer (SAM) gate dielectric and a high-mobility organic semiconductor (pentacene). These TFTs operate with supply voltages of less than 2 V, yet have gate currents that are lower than those of advanced silicon field-effect transistors with SiO2 dielectrics. These results should therefore increase the prospects of using organic TFTs in low-power applications (such as portable devices). Moreover, molecular SAMs may even be of interest for advanced silicon transistors where the continued reduction in dielectric thickness leads to ever greater gate leakage and power dissipation.

801 citations


Journal ArticleDOI
TL;DR: In this paper, the authors demonstrate a bottom-up integration of a semiconductor 1D nanowire, using zinc oxide (ZnO) as an example, to obtain a vertical surround-gate field effect transistor (VSG-FET).
Abstract: Harnessing the potential of single crystal inorganic nanowires for practical advanced nanoscale applications requires not only reproducible synthesis of highly regular one-dimensional (1D) nanowire arrays directly on device platforms but also elegant device integration which retains structural integrity of the nanowires while significantly reducing or eliminating complex critical processing steps. Here we demonstrate a unique, direct, and bottom-up integration of a semiconductor 1D nanowire, using zinc oxide (ZnO) as an example, to obtain a vertical surround-gate field-effect transistor (VSG-FET). The vertical device structure and bottom-up integration reduce process complexity, compared to conventional top-down approaches. More significantly, scaling of the vertical channel length is lithographically independent and decoupled from the device packing density. A bottom electrical contact to the nanowire is uniquely provided by a heavily doped underlying lattice-match substrate. Based on the nanowire-integrated platform, both n- and p-channel VSG-FETs are fabricated. The vertical device architecture has the potential for use in tera-level ultrahigh-density nanoscale memory and logic devices.

668 citations


Journal ArticleDOI
Meikei Ieong1, Bruce B. Doris1, J. Kedzierski1, K. Rim1, Min Yang1 
17 Dec 2004-Science
TL;DR: Challenges and possible solutions are discussed for continued silicon device performance trends down to the sub-10-nm gate regimes, which will lead to devices with gate lengths below 10 nanometers.
Abstract: In the next decade, advances in complementary metal-oxide semiconductor fabrication will lead to devices with gate lengths (the region in the device that switches the current flow on and off) below 10 nanometers (nm), as compared with current gate lengths in chips that are now about 50 nm. However, conventional scaling will no longer be sufficient to continue device performance by creating smaller transistors. Alternatives that are being pursued include new device geometries such as ultrathin channel structures to control capacitive losses and multiple gates to better control leakage pathways. Improvement in device speed by enhancing the mobility of charge carriers may be obtained with strain engineering and the use of different crystal orientations. Here, we discuss challenges and possible solutions for continued silicon device performance trends down to the sub-10-nm gate regimes.

549 citations


Journal ArticleDOI
TL;DR: In this paper, the authors demonstrate controllable shift of the threshold voltage and the turn-on voltage in pentacene thin film transistors and rubrene single crystal field effect transistors by the use of nine organosilanes with different functional groups.
Abstract: We demonstrate controllable shift of the threshold voltage and the turn-on voltage in pentacene thin film transistors and rubrene single crystal field effect transistors (FET) by the use of nine organosilanes with different functional groups. Prior to depositing the organic semiconductors, the organosilanes were applied to the SiO2 gate insulator from solution and form a self-assembled monolayer (SAM). The observed shifts of the transfer characteristics range from −2to50V and can be related to the surface potential of the layer next to the transistor channel. Concomitantly the mobile charge carrier concentration at zero gate bias reaches up to 4×1012∕cm2. In the single crystal FETs the measured transfer characteristics are also shifted, while essentially maintaining the high quality of the subthreshold swing. The shift of the transfer characteristics is governed by the built-in electric field of the SAM and can be explained using a simple energy level diagram. In the thin film devices, the subthreshold re...

Journal ArticleDOI
TL;DR: In this paper, the complementary Si-based tunneling transistors are investigated in detail, and it is found that the band-to-band tunneling current is controlled by the gate-tosource voltage.
Abstract: The metal oxide semiconductor field effect transistor (MOSFET) is scaling to a “tunneling epoch”, in which multiple leakage current induced by different tunneling effects exist. The complementary Si-based tunneling transistors are presented in this paper. The working principle of this device is investigated in detail. It is found that the band-to-band tunneling current is be controlled by the gate-to-source voltage. Due to the reverse biased p-i-n diode structure, an ultra-low leakage current is achieved. The sub-threshold swing of TFET is not limited by kt/q, which is the physical limit of the MOSFET. Using the CMOS compatible processes, the complementary TFETs (CTFET) are fabricated on one wafer. From a circuit point of view, the compatibility between TFET and MOSFET enables the transfer of CMOS circuits to CTFET circuits.

Journal ArticleDOI
TL;DR: In this article, a high-voltage high-electron mobility transistors have been fabricated using multiple field plates over dielectric passivation layers, and the device breakdown voltage was found to increase with the addition of the field plates.
Abstract: High-voltage Al/sub 0.22/Ga/sub 0.78/N-GaN high-electron mobility transistors have been fabricated using multiple field plates over dielectric passivation layers. The device breakdown voltage was found to increase with the addition of the field plates. With two field plates, the device showed a breakdown voltage as high as 900 V. This technique is easy to apply, based on the standard planar transistor fabrication, and especially attractive for the power switching applications.

Journal ArticleDOI
TL;DR: Inorganic field-effect transistors are the fundamental building blocks for basic analytical circuits, as well as the key elements for digital combinational logic circuits, such as adders, shifters, inverters, and arithmetic logic units.

Journal ArticleDOI
TL;DR: In this article, a 3D quantum simulator for the silicon nanowire transistor (SNWT) is presented, where the authors use Buttiker probes to simulate the effects of scattering on both internal device characteristics and terminal currents.
Abstract: The silicon nanowire transistor (SNWT) is a promising device structure for future integrated circuits, and simulations will be important for understanding its device physics and assessing its ultimate performance limits. In this work, we present a three-dimensional (3D) quantum mechanical simulation approach to treat various SNWTs within the effective-mass approximation. We begin by assuming ballistic transport, which gives the upper performance limit of the devices. The use of a mode space approach (either coupled or uncoupled) produces high computational efficiency that makes our 3D quantum simulator practical for extensive device simulation and design. Scattering in SNWTs is then treated by a simple model that uses so-called Buttiker probes, which was previously used in metal-oxide-semiconductor field effect transistor simulations. Using this simple approach, the effects of scattering on both internal device characteristics and terminal currents can be examined, which enables our simulator to be used f...

Journal ArticleDOI
13 Sep 2004
TL;DR: In this paper, a very low power interface IC used in implantable pacemaker systems is presented, which contains amplifiers, filters, ADCs, battery management system, voltage multipliers, high voltage pulse generators, programmable logic and timing control.
Abstract: Low power consumption is crucial for medical implant devices. A single-chip, very-low-power interface IC used in implantable pacemaker systems is presented. It contains amplifiers, filters, ADCs, battery management system, voltage multipliers, high voltage pulse generators, programmable logic and timing control. A few circuit techniques are proposed to achieve nanopower circuit operations within submicron CMOS process. Subthreshold transistor designs and switched-capacitor circuits are widely used. The 200 k transistor IC occupies 49 mm/sup 2/, is fabricated in a 0.5-/spl mu/m two-poly three-metal multi-V/sub t/ process, and consumes 8 /spl mu/W.

Journal ArticleDOI
TL;DR: In this paper, a 3D quantum simulator for the silicon nanowire transistor (SNWT) is presented, where the authors use Buttiker probes to simulate the effects of scattering on both internal device characteristics and terminal currents.
Abstract: The silicon nanowire transistor (SNWT) is a promising device structure for future integrated circuits, and simulations will be important for understanding its device physics and assessing its ultimate performance limits. In this work, we present a three-dimensional quantum mechanical simulation approach to treat various SNWTs within the effective-mass approximation. We begin by assuming ballistic transport, which gives the upper performance limit of the devices. The use of a mode space approach (either coupled or uncoupled) produces high computational efficiency that makes our 3D quantum simulator practical for extensive device simulation and design. Scattering in SNWTs is then treated by a simple model that uses so-called Buttiker probes, which was previously used in metal-oxide-semiconductor field effect transistor (MOSFET) simulations. Using this simple approach, the effects of scattering on both internal device characteristics and terminal currents can be examined, which enables our simulator to be used for the exploration of realistic performance limits of SNWTs.

Journal ArticleDOI
TL;DR: In this article, two mobility metrics, μavg and μinc, are developed and proposed as relevant tools in the characterization of non-ideal TFTs, which are employed to characterize the ZnO-channel thin-film transistor (TFT) reported in this paper.
Abstract: ZnO-channel thin-film transistor (TFT) test structures are fabricated using a bottom-gate structure on thermally oxidized Si; ZnO is deposited via RF sputtering from an oxide target, with an unheated substrate. Electrical characteristics are evaluated, with particular attention given to the extraction and interpretation of transistor channel mobility. ZnO-channel TFT mobility exhibits severe deviation from that assumed by ideal TFT models; mobility extraction methodology must accordingly be recast so as to provide useful insight into device operation. Two mobility metrics, μavg and μinc, are developed and proposed as relevant tools in the characterization of nonideal TFTs. These mobility metrics are employed to characterize the ZnO-channel TFTs reported herein; values for μinc as high as 25 cm2/V s are measured, comprising a substantial increase in ZnO-channel TFT mobility as compared to previously reported performance for such devices.

Journal ArticleDOI
TL;DR: In this paper, the resonant, voltage tunable emission of terahertz radiation (0.4 − 1.0 THz) from a gated two-dimensional electron gas in a 60 nm InGaAs high electron mobility transistor was investigated.
Abstract: We report on the resonant, voltage tunable emission of terahertz radiation (0.4–1.0 THz) from a gated two-dimensional electron gas in a 60 nm InGaAs high electron mobility transistor. The emission is interpreted as resulting from a current driven plasma instability leading to oscillations in the transistor channel (Dyakonov–Shur instability).

Journal ArticleDOI
TL;DR: In this paper, a SnO2 transparent thin-film transistor (TTFT) was demonstrated, and the authors achieved the maximum field effect mobilities of 0.8 cm2 V−1 s−1 and 2.0 cm 2 V− 1 s− 1 for enhancement and depletion modes, respectively.
Abstract: A SnO2 transparent thin-film transistor (TTFT) is demonstrated. The SnO2 channel layer is deposited by RF magnetron sputtering and then rapid thermal annealed in O2 at 600°C. The TTFT is highly transparent, and enhancement-mode behaviour is achieved by employing a very thin channel layer (10–20 nm). Maximum field-effect mobilities of 0.8 cm2 V−1 s−1 and 2.0 cm2 V−1 s−1 are obtained for enhancement- and depletion-mode devices, respectively. The transparent nature and the large drain current on-to-off ratio of 105 associated with the enhancement-mode behaviour of these devices may prove useful for novel gas-sensor applications.

Journal ArticleDOI
Tae Wook Kim1, Bonkee Kim, Kwyro Lee1
TL;DR: In this article, a high-level linear receiver RF front-end adopting MOSFET transconductance linearization by linearly superposing several common-source FET transistors in parallel (multiple gated transistor, or MGTR), combined with some additional circuit techniques are reported.
Abstract: Highly linear receiver RF front-end adopting MOSFET transconductance linearization by linearly superposing several common-source FET transistors in parallel (multiple gated transistor, or MGTR), combined with some additional circuit techniques are reported. In MGTR circuitry, linearity is improved by using transconductance linearization which can be achieved by canceling the negative peak value of g/sub m/'' of the main transistor with the positive one in the auxiliary transistor having a different size and gate drive combined in parallel. This enhancement, however, is limited by the distortion originated from the combined influence of g/sub m/' and harmonic feedback, which can greatly be reduced by the cascoding MGTR output for the amplifier and by the tuned load for the mixer. Experimental results designed using the above techniques show IIP/sub 3/ improvements at given power consumption by as much as 10 dB for CMOS low-noise amplifier at 900 MHz and 7 dB for Gilbert cell mixer at 2.4 GHz without sacrificing other features such as gain and noise figure.

Journal ArticleDOI
TL;DR: In this paper, an emerging factor that may disrupt this trend is the slowing speed of signal propagation within the chip, caused by the interconnection wiring, increase with each generation of scaling and may limit the overall performance of the integrated system.

Journal ArticleDOI
TL;DR: In this article, a light-emitting organic field effect transistor (OFET) with pronounced ambipolar current characteristics is demonstrated, where the light intensity is controlled by both the drain-source voltage VDS and the gate voltage VG.
Abstract: We demonstrate a light-emitting organic field-effect transistor (OFET) with pronounced ambipolar current characteristics. The ambipolar transport layer is a coevaporated thin film of α-quinquethiophene (α-5T) as hole-transport material and N,N′-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13) as electron-transport material. The light intensity is controlled by both the drain–source voltage VDS and the gate voltage VG. Moreover, the latter can be used to adjust the charge-carrier balance. The device structure serves as a model system for ambipolar light-emitting OFETs and demonstrates the general concept of adjusting electron and hole mobilities by coevaporation of two different organic semiconductors.

Patent
Nick Lindert1, Stephen M. Cea1
31 Mar 2004
TL;DR: In this paper, a tri-gate transistor with stained enhanced mobility and its method of fabrication is presented, where a gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and a gate electrode having a pair of laterally opposite sidewalls is formed around and around the gate dieslectric layers.
Abstract: A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a top surface on laterally opposite sidewalls. A semiconductor capping layer is formed on the top surface and on the sidewalls of the semiconductor body. A gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and is formed on the capping layer on the sidewalls of the semiconductor body. A gate electrode having a pair of laterally opposite sidewalls is formed on and around the gate dielectric layer. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Journal ArticleDOI
TL;DR: In this paper, the authors reported the fabrication of TFT backplanes by using jet printing as the only patterning method, and they used a regioregular polythiophene, poly[5,5′-bis(3-dodecyl-2-thienyl)-2,2′-bithiophene; (PQT-12) is deposited by inkjet printing and exhibits average TFT mobility of 0.06cm2∕Vs, on/off ratios of 106, and minimal bias stress.
Abstract: Thin-film transistor (TFT) backplanes fabricated by using jet printing as the only patterning method are reported. Additive and subtractive printing processes are combined to make 128×128 pixel active matrix arrays with 340μm pixel size. The semiconductor used, a regioregular polythiophene, poly[5,5′-bis(3-dodecyl-2-thienyl)-2,2′-bithiophene]; (PQT-12) is deposited by inkjet printing and exhibits average TFT mobility of 0.06cm2∕Vs, on/off ratios of 106, and minimal bias stress. The printed TFTs have high yield with a narrow performance distribution. The pixel design benefits from the registration accuracy of jet printing and it is shown that the electrical performance is suitable for addressing capacitive media displays.

Journal ArticleDOI
TL;DR: In this paper, a vertical field effect transistor (FET) with a vertical gate controlling the band-to-band tunneling width is presented, and the operation of the device is shown by means of both experimental results as well as two-dimensional computer simulations.
Abstract: The realization of a novel vertically grown tunnel field-effect transistor (FET) with several interesting properties is presented. The operation of the device is shown by means of both experimental results as well as two-dimensional computer simulations. This device consists of a MBE-grown, vertical p-i-n structure. A vertical gate controls the band-to-band tunneling width, and hence the tunneling current. Both n-channel and p-channel current behavior is observed. A perfect saturation in drain current-voltage (I/sub D/--V/sub DS/) characteristics in the reverse-biased condition for n-channel, an exponential and nearly temperature independent drain current-gate voltage (I/sub D/--V/sub GS/) relation for both subthreshold, as well as on-region, and source-drain off-currents several orders of magnitude lower then the conventional MOSFET are achieved. In the forward-biased condition, the device shows normal p-i-n diode characteristics.

Journal ArticleDOI
TL;DR: In this article, the authors demonstrate seamless direct integration of a semiconductor nanowire grown using a bottom-up approach to obtain a vertical field effect transistor (VFET).
Abstract: We demonstrate seamless direct integration of a semiconductor nanowire grown using a bottom-up approach to obtain a vertical field-effect transistor (VFET). We first synthesize single crystalline semiconductor indium oxide (In2O3) nanowires projecting vertically and uniformly on a nonconducting optical sapphire substrate. Direct electrical contact to the nanowires is uniquely provided by a self-assembled underlying In2O3 buffer layer formed in-situ during the nanowire growth. A controlled time-resolved growth study reveals dynamic simultaneous nucleation and epitaxial growth events, driven by two competitive growth mechanisms. Based on the nanowire-integrated platform, a depletion mode n-channel VFET with an In2O3 nanowire constituting the active channel is fabricated. Our unique vertical device architecture could potentially lead to tera-level ultrahigh-density nanoscale electronic, and optoelectronic devices.

Proceedings ArticleDOI
13 Dec 2004
TL;DR: A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented in this article.
Abstract: A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented. Transistor gate length is scaled down to 35nm while not scaling the gate oxide as a means to improve performance and reduce power. Increased NMOS and PMOS drive currents are achieved by enhanced channel strain and junction engineering. 193nm lithography along with APSM mask technology is used on critical layers to provide aggressive design rules and a 6-T SRAM cell size of 0.57/spl mu/m/sup 2/. Process yield, performance and reliability are demonstrated on a 70 Mbit SRAM test vehicle with >0.5 billion transistors.

Patent
30 Aug 2004
TL;DR: In this paper, structural, systems and methods for transistors having gates with variable work functions formed by atomic layer deposition are described. Butts are separated from the channel region by a gate insulator.
Abstract: Structures, systems and methods for transistors having gates with variable work functions formed by atomic layer deposition are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate includes a ternary metallic conductor formed by atomic layer deposition.

Journal ArticleDOI
TL;DR: In this paper, the cutoff frequency of carbon nanotube transistors is analyzed and the influence of quantum capacitance, kinetic inductance, and ballistic transport on the high-frequency properties of nanotubes is analyzed.
Abstract: We present phenomenological predictions for the cutoff frequency of carbon nanotube transistors. We also present predictions of the effects parasitic capacitances on AC nanotube transistor performance. The influence of quantum capacitance, kinetic inductance, and ballistic transport on the high-frequency properties of nanotube transistors is analyzed. We discuss the challenges of impedance matching for ac nano-electronics in general, and show how integrated nanosystems can solve this challenge. Our calculations show that carbon nano-electronics may be faster than conventional Si, SiGe, GaAs, or InP semiconductor technologies. We predict a cutoff frequency of 80 GHz/L, where L is the gate length in microns, opening up the possibility of a ballistic THz nanotube transistor.