Showing papers on "Transistor published in 2005"

Device Physics of Solution‐Processed Organic Field‐Effect Transistors

Abstract: Field-effect transistors based on solution-processible organic semiconductors have experienced impressive improvements in both performance and reliability in recent years, and printing-based manufacturing processes for integrated transistor circuits are being developed to realize low-cost, large-area electronic products on flexible substrates. This article reviews the materials, charge-transport, and device physics of solution-processed organic field-effect transistors, focusing in particular on the physics of the active semiconductor/dielectric interface. Issues such as the relationship between microstructure and charge transport, the critical role of the gate dielectric, the influence of polaronic relaxation and disorder effects on charge transport, charge-injection mechanisms, and the current understanding of mechanisms for charge trapping are reviewed. Many interesting questions on how the molecular and electronic structures and the presence of defects at organic/organic heterointerfaces influence the device performance and stability remain to be explored.

Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

Abstract: As technology scales, variability in transistor performance continues to increase, making transistors less and less reliable. This creates several challenges in building reliable systems, from the unpredictability of delay to increasing leakage current. Finding solutions to these challenges require a concerted effort on the part of all the players in a system design. This article discusses these effects and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.

Conformable, flexible, large-area networks of pressure and thermal sensors with organic transistor active matrixes

Abstract: Skin-like sensitivity, or the capability to recognize tactile information, will be an essential feature of future generations of robots, enabling them to operate in unstructured environments. Recently developed large-area pressure sensors made with organic transistors have been proposed for electronic artificial skin (E-skin) applications. These sensors are bendable down to a 2-mm radius, a size that is sufficiently small for the fabrication of human-sized robot fingers. Natural human skin, however, is far more complex than the transistor-based imitations demonstrated so far. It performs other functions, including thermal sensing. Furthermore, without conformability, the application of E-skin on three-dimensional surfaces is impossible. In this work, we have successfully developed conformable, flexible, large-area networks of thermal and pressure sensors based on an organic semiconductor. A plastic film with organic transistor-based electronic circuits is processed to form a net-shaped structure, which allows the E-skin films to be extended by 25%. The net-shaped pressure sensor matrix was attached to the surface of an egg, and pressure images were successfully obtained in this configuration. Then, a similar network of thermal sensors was developed with organic semiconductors. Next, the possible implementation of both pressure and thermal sensors on the surfaces is presented, and, by means of laminated sensor networks, the distributions of pressure and temperature are simultaneously obtained.

Field-effect transistor

Abstract: Provided is a field-effect transistor including an active layer and a gate insulating film, wherein the active layer includes an amorphous oxide layer containing an amorphous region and a crystalline region, and the crystalline region is in the vicinity of or in contact with an interface between the amorphous oxide layer and the gate insulating film

Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby

Abstract: A thin film transistor comprises a zinc-oxide-containing semiconductor material. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said material. Further disclosed is a process for fabricating a thin film transistor device, wherein the substrate temperature is no more than 300° C. during fabrication.

Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors

Abstract: This article reviews the history and current progress in high-mobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We start by providing a chronological overview of important milestones and discoveries that have allowed heterostructures grown on Si substrates to transition from purely academic research in the 1980’s and 1990’s to the commercial development that is taking place today. We next provide a topical review of the various types of strain-engineered MOSFETs that can be integrated onto relaxed Si1−xGex, including surface-channel strained Si n- and p-MOSFETs, as well as double-heterostructure MOSFETs which combine a strained Si surface channel with a Ge-rich buried channel. In all cases, we will focus on the connections between layer structure, band structure, and MOS mobility characteristics. Although the surface and starting substrate are composed of pure Si, the use of strained Si still creates new challenges, and we shall also review the litera...

High-performance solution-processed polymer ferroelectric field-effect transistors

Abstract: We demonstrate a rewritable, non-volatile memory device with flexible plastic active layers deposited from solution. The memory device is a ferroelectric field-effect transistor (FeFET) made with a ferroelectric fluoropolymer and a bisalkoxy-substituted poly(p-phenylene vinylene) semiconductor material. The on- and off-state drain currents differ by several orders of magnitude, and have a long retention time, a high programming cycle endurance and short programming time. The remanent semiconductor surface charge density in the on-state has a high value of 18 mC m−2, which explains the large on/off ratio. Application of a moderate gate field raises the surface charge to 26 mC m−2, which is of a magnitude that is very difficult to obtain with conventional FETs because they are limited by dielectric breakdown of the gate insulator. In this way, the present ferroelectric–semiconductor interface extends the attainable field-effect band bending in organic semiconductors.

Benchmarking nanotechnology for high-performance and low-power logic transistor applications

Abstract: Recently there has been tremendous progress made in the research of novel nanotechnology for future nanoelectronic applications. In particular, several emerging nanoelectronic devices such as carbon-nanotube field-effect transistors (FETs), Si nanowire FETs, and planar III-V compound semiconductor (e.g., InSb, InAs) FETs, all hold promise as potential device candidates to be integrated onto the silicon platform for enhancing circuit functionality and also for extending Moore's Law. For high-performance and low-power logic transistor applications, it is important that these research devices are frequently benchmarked against the existing Si logic transistor data in order to gauge the progress of research. In this paper, we use four key device metrics to compare these emerging nanoelectronic devices to the state-of-the-art planar and nonplanar Si logic transistors. These four metrics include: 1) CV/I or intrinsic gate delay versus physical gate length L/sub g/; 2) energy-delay product versus L/sub g/; 3) subthreshold slope versus L/sub g/; and 4) CV/I versus on-to-off-state current ratio I/sub ON//I/sub OFF/. The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome. We believe that benchmarking is a key element in accelerating the progress of nanotechnology research for logic transistor applications.

Electrostatic control of ions and molecules in nanofluidic transistors.

Abstract: We report a nanofluidic transistor based on a metal-oxide-solution (MOSol) system that is similar to a metal-oxide-semiconductor field-effect transistor (MOSFET). Using a combination of fluorescence and electrical measurements, we demonstrate that gate voltage modulates the concentration of ions and molecules in the channel and controls the ionic conductance. Our results illustrate the efficacy of field-effect control in nanofluidics, which could have broad implications on integrated nanofluidic circuits for manipulation of ions and biomolecules in sub-femtoliter volumes.

Semiconductor Detector Systems

Abstract: 0. Preface 1. Detector systems overview 2. Signal formation and acquisition 3. Electronic noise 4. Signal processing 5. Elements of digital electronics and signal processing 6. Transistors and amplifiers 7. Radiation effects 8. Detector systems 9. Why things don't work A. Semiconductor device technology B. Phasors and complex algebra in electrical circuits C. Equivalent circuits D. Feedback amplifiers E. The diode equation F. Electrical effects of impurities and defects G. Bipolar transistor equations

Transparent and flexible carbon nanotube transistors.

Abstract: We report the fabrication of transparent and flexible transistors where both the bottom gate and the conducting channel are carbon nanotube networks of different densities and Parylene N is the gate insulator. Device mobilities of 1 cm2 V -1 s -1 and on/off ratios of 100 are obtained, with the latter influenced by the properties of the insulating layer. Repetitive bending has minor influence on the characteristics, with full recovery after repeated bending. The operation is insensitive to visible light and the gating does not influence the transmission in the visible spectral range. The quest for flexible and transparent transistors has recently resulted in several noteworthy achievements. Transparent transistors have been fabricated using both polymers 1-3 and inorganic oxides. 4,5 These advances, notable in the emerging technology arena that is generally called “plastic electronics”, have received wide publicity. Both, nevertheless, have significant deficiencies. The former have low mobility and the latter do not have the desired flexibility and are not easily manufacturable. These factors severely limit the application potential of the devices. Our method introduces a transistor architecture that potentially includes only two materials: carbon nanotubes (NTs) and a polymeric gate insulator. This simplicity of structure would ensure a simple manufacturing process.

High-performance carbon nanotube field-effect transistor with tunable polarities

Abstract: State-of-the-art carbon nanotube field-effect transistors (CNFETs) behave as Schottky-barrier-modulated transistors. It is known that vertical scaling of the gate oxide significantly improves the performance of these devices. However, decreasing the oxide thickness also results in pronounced ambipolar transistor characteristics and increased drain leakage currents. Using a novel device concept, we have fabricated high-performance enhancement-mode CNFETs exhibiting n- or p-type unipolar behavior, tunable by electrostatic and/or chemical doping, with excellent OFF-state performance and a steep subthreshold swing (S=63 mV/dec). The device design allows for aggressive oxide thickness and gate-length scaling while maintaining the desired device characteristics.

Low-voltage organic field-effect transistors and inverters enabled by ultrathin cross-linked polymers as gate dielectrics

Abstract: The quest for high-performance organic thin-film transistor (OTFT) gate dielectrics is of intense current interest. Beyond having excellent insulating properties, such materials must meet other stringent requirements for optimum OTFT function: efficient low-temperature solution fabrication, mechanical flexibility, and compatibility with diverse gate materials and organic semiconductors. The OTFTs should function at low biases to minimize power consumption, hence the dielectric must exhibit large gate capacitance. We report the realization of new spin-coatable, ultrathin (<20 nm) cross-linked polymer blends exhibiting excellent insulating properties (leakage current densities approximately 10(-)(8) Acm(-)(2)), large capacitances (up to approximately 300 nF cm(-)(2)), and enabling low-voltage OTFT functions. These dielectrics exhibit good uniformity over areas approximately 150 cm(2), are insoluble in common solvents, can be patterned using standard microelectronic etching methodologies, and adhere to/are compatible with n(+)-Si, ITO, and Al gates, and with a wide range of p- and n-type semiconductors. Using these dielectrics, complementary invertors have been fabricated which function at 2 V.

Current drive circuit and display device using same, pixel circuit, and drive method

Abstract: A display device including a current drive circuit capable of stably and correctly supplying an intended current to a light emitting element of each pixel without being affected by variations in characteristics of an active element inside the pixel and as a result capable of displaying a high quality image, wherein each pixel comprises a receiving use transistor TFT 3 for fetching a signal current Iw from a data line DATA when a scanning line SCAN-A is selected, a conversion use transistor TFT 1 for once converting a current level of a fetched signal current Iw to a voltage level and holding the same, and a drive use transistor TFT 2 for passing a drive current having a current level in accordance with the held voltage level through a light emitting element OLED. The conversion use thin film transistor TFT 1 generates a converted voltage level at its own gate by passing the signal current Iw fetched by the TFT 3 through its own channel. A capacitor C holds the voltage level created at the gate of the TFT 1 . The TFT 2 passes the drive current having a current level in accordance with the held voltage level through the light emitting element OLED.

Analog circuits in ultra-deep-submicron CMOS

Abstract: Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena.

Radiation-induced edge effects in deep submicron CMOS transistors

Abstract: The study of the TID response of transistors and isolation test structures in a 130 nm commercial CMOS technology has demonstrated its increased radiation tolerance with respect to older technology nodes. While the thin gate oxide of the transistors is extremely tolerant to dose, charge trapping at the edge of the transistor still leads to leakage currents and, for the narrow channel transistors, to significant threshold voltage shift-an effect that we call Radiation Induced Narrow Channel Effect (RINCE).

Active matrix display devices

Abstract: An active matrix LED display has a light-dependent device for detecting the brightness of the display element and threshold voltage measurement circuitry for measuring a threshold voltage of a pixel the drive transistor. Compensation for ageing of the display element is thus provided by an optical feedback path, and compensation for drive transistor threshold variations is provided by measurement of the threshold voltage. This provides a reliable compensation scheme for the threshold voltage variations, whilst also providing ageing compensation.

The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance

Abstract: The rapid cadence of metal-oxide semiconductor field-effect transistor (MOSFET) scaling, as seen in the new 2003 International Technology Roadmap for Semiconductors ITRS), is accelerating introduction of new technologies to extend complementary MOS (CMOS) down to, and perhaps beyond, the 22-nm node This acceleration simultaneously requires the industry to intensify research on two highly challenging thrusts: one is scaling CMOS into an increasingly difficult manufacturing domain well below the 90-nm node for high performance (HP), low operating power (LOP), and low standby power (LSTP) applications, and the other is an exciting opportunity to invent fundamentally new approaches to information and signal processing to sustain functional scaling beyond the domain of CMOS This article is focused on scaling CMOS to its fundamental limits, determined by manufacturing, physics, and costs using new materials and nonclassical structures This paper provides a brief introduction to each of the new nonclassical CMOS structures This is followed by a presentation of one scenario for introduction of new structural changes to the MOSFET to scale CMOS to the end of the ITRS A brief review of electrostatic scaling of a MOSFET necessary to manage short channel effects (SCEs) at the most advanced technology nodes is also provided

A CMOS smart temperature sensor with a 3/spl sigma/ inaccuracy of /spl plusmn/0.1/spl deg/C from -55/spl deg/C to 125/spl deg/C

Abstract: A low-cost temperature sensor with on-chip sigma-delta ADC and digital bus interface was realized in a 0.5 /spl mu/m CMOS process. Substrate PNP transistors are used for temperature sensing and for generating the ADC's reference voltage. To obtain a high initial accuracy in the readout circuitry, chopper amplifiers and dynamic element matching are used. High linearity is obtained by using second-order curvature correction. With these measures, the sensor's temperature error is dominated by spread on the base-emitter voltage of the PNP transistors. This is trimmed after packaging by comparing the sensor's output with the die temperature measured using an extra on-chip calibration transistor. Compared to traditional calibration techniques, this procedure is much faster and therefore reduces production costs. The sensor is accurate to within /spl plusmn/0.5/spl deg/C (3/spl sigma/) from -50/spl deg/C to 120/spl deg/C.

Antimonide-based compound semiconductors for electronic devices: A review

Abstract: Several research groups have been actively pursuing antimonide-based electronic devices in recent years. The advantage of narrow-bandgap Sb-based devices over conventional GaAs- or InP-based devices is the attainment of high-frequency operation with much lower power consumption. This paper will review the progress on three antimonide-based electronic devices: high electron mobility transistors (HEMTs), resonant tunneling diodes (RTDs), and heterojunction bipolar transistors (HBTs). Progress on the HEMT includes the demonstration of Ka- and W-band low-noise amplifier circuits that operate at less than one-third the power of similar InP-based circuits. The RTDs exhibit excellent figures of merit but, like their InP- and GaAs-based counterparts, are waiting for a viable commercial application. Several approaches are being investigated for HBTs, with circuits reported using InAs and InGaAs bases.

Comparing carbon nanotube transistors - the ideal choice: a novel tunneling device design

Abstract: Three different carbon nanotube (CN) field-effect transistor (CNFET) designs are compared by simulation and experiment. While a C-CNFET with a doping profile similar to a "conventional" (referred to as C-CNFET in the following) p-or n-MOSFET in principle exhibits superior device characteristics when compared with a Schottky barrier CNFET, we find that aggressively scaled C-CNFET devices suffer from "charge pile-up" in the channel. This effect which is also known to occur in floating body silicon transistors deteriorates the C-CNFET off-state substantially and ultimately limits the achievable on/off-current ratio. In order to overcome this obstacle we explore the possibility of using CNs as gate-controlled tunneling devices (T-CNFETs). The T-CNFET benefits from a steep inverse subthreshold slope and a well controlled off-state while at the same time delivering high performance on-state characteristics. According to our simulation, the T-CNFET is the ideal transistor design for an ultrathin body three-terminal device like the CNFET.

High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability

Abstract: For the first time, we have successfully fabricated gate-all-around twin silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process With 10nm diameter nanowire, saturation currents through twin nanowires of 264 mA/mum, 111 mA/mum for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively No roll-off of threshold voltages, ~70 mV/dec of substhreshold swing (SS), and ~20 mV/V of drain induced barrier lowering(DIBL) down to 30 nm gate length are observed for both n-ch and p-ch TSNWFETs

Segmented channel MOS transistor

Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

Large gate modulation in the current of a room temperature single molecule transistor.

Abstract: We have demonstrated a single molecule field effect transistor (FET) which consists of a redox molecule (perylene tetracarboxylic diimide) covalently bonded to a source and drain electrode and an electrochemical gate. By adjusting the gate voltage, the energy levels of empty molecular states are shifted to the Fermi level of the source and drain electrodes. This results in a nearly 3 orders of magnitude increase in the source-drain current, in the fashion of an n-type FET. The large current increase is attributed to an electron transport mediated by the lowest empty molecular energy level when it lines up with the Fermi level.

Impact ionization MOS (I-MOS)-Part I: device and circuit simulations

Abstract: One of the fundamental problems in the continued scaling of transistors is the 60 mV/dec room temperature limit in the subthreshold slope. In part I this work, a novel transistor based on the field-effect control of impact-ionization (I-MOS) is explored through detailed device and circuit simulations. The I-MOS uses gated-modulation of the breakdown voltage of a p-i-n diode to switch from the OFF state to the ON state and vice-versa. Device simulations using MEDICI show that the I-MOS has a subthreshold slope of 5 mV/dec or lower and I/sub ON/>1 mA//spl mu/m at 400 K. Simulations were used to further explore the characteristics of the I-MOS including the transients of the turn-on mechanism, the short-channel effect, scalability, and other important device attributes. Circuit mode simulations were also used to explore circuit design using I-MOS devices and the design of an I-MOS inverter. These simulations indicated that the I-MOS has the potential to replace CMOS in high performance and low power digital applications. Part II of this work focuses on I-MOS experimental results with emphasis on hot carrier effects, germanium p-i-n data and breakdown in recessed structure devices.

σ-π molecular dielectric multilayers for low-voltage organic thin-film transistors

Abstract: Very thin (2.3-5.5 nm) self-assembled organic dielectric multilayers have been integrated into organic thin-film transistor structures to achieve sub-1-V operating characteristics. These new dielectrics are fabricated by means of layer-by-layer solution phase deposition of molecular silicon precursors, resulting in smooth, nanostructurally well defined, strongly adherent, thermally stable, virtually pinhole-free, organosiloxane thin films having exceptionally large electrical capacitances (up to ≈2,500 nF·cm-2), excellent insulating properties (leakage current densities as low as 10-9 A·cm-2), and single-layer dielectric constant (k)of ≈16. These 3D self-assembled multilayers enable organic thin-film transistor function at very low source-drain, gate, and threshold voltages (<1 V) and are compatible with a broad variety of vapor- or solution-deposited p- and n-channel organic semiconductors. gate insulator molecular multilayer organic dielectric self-assembly

Low-voltage operation of a pentacene field-effect transistor with a polymer electrolyte gate dielectric

Abstract: Large operating voltages are often required to switch organic field-effect transistors (OFETs) on and off because commonly used gate dielectric layers provide low capacitive coupling between the gate electrode and the semiconductor. We present here a pentacene OFET gated by a solution-deposited polymer electrolyte film in which the current was modulated over four orders of magnitude using gate voltages less than 2V. A subthreshold slope of 180mV per decade of current was observed during transistor turn on at a source-drain bias of −1V; the estimated dielectric layer specific capacitance was 5μF∕cm2. Sweep rate-dependent hysteresis may be attributed to a combination of ion migration and charge carrier trapping effects. Strategies to improve switching speeds for polymer electrolyte-gated OFETs are also discussed.

Self-aligned self assembly of multi-nanowire silicon field effect transistors

Abstract: We demonstrate the efficacy of diblock copolymer self assembly for solving key fabrication challenges of aggressively scaled silicon field effect transistors. These materials spontaneously form nanometer-scale patterns that self-align to larger-scale lithography, enabling construction of sub-lithographic semiconducting transistor channels composed of arrays of parallel nanowires with critical dimensions (15 nm width, 40 nm pitch) defined by self assembly. The number of nanowires in the arrays is readily adjusted, greatly reducing the complexity associated with width-scaling of nanowire transistors. We measured Schottky source/drain multi-nanowire n-channel devices comprised of 6, 8, 10, and 16 nanowires, with current drives of ∼5μA∕wire and current on/off ratios of ∼105.

Light emitting display and driving method thereof

Abstract: A light emitting display including data lines for applying data voltages corresponding to video signals, scan lines for transmitting select signals, and pixel circuits. Each pixel circuit includes a light emitting element for emitting light, and a transistor including first to third electrodes, for controlling a current output to the third electrode according to a voltage between the first and second electrodes. Each pixel circuit also includes a first switch for diode-connecting the transistor, a capacitor having a first electrode coupled to the first electrode of the transistor, a second switch for applying a corresponding said data voltage to the second electrode of the capacitor in response to a corresponding said select signal from a corresponding said scan line, and a third switch for substantially electrically decoupling the second electrode of the capacitor from a power supply voltage source.