Showing papers on "Transistor published in 2006"

Liquid-crystalline semiconducting polymers with high charge-carrier mobility.

Abstract: Organic semiconductors that can be fabricated by simple processing techniques and possess excellent electrical performance, are key requirements in the progress of organic electronics. Both high semiconductor charge-carrier mobility, optimized through understanding and control of the semiconductor microstructure, and stability of the semiconductor to ambient electrochemical oxidative processes are required. We report on new semiconducting liquid-crystalline thieno[3,2-b ]thiophene polymers, the enhancement in charge-carrier mobility achieved through highly organized morphology from processing in the mesophase, and the effects of exposure to both ambient and low-humidity air on the performance of transistor devices. Relatively large crystalline domain sizes on the length scale of lithographically accessible channel lengths (∼200 nm) were exhibited in thin films, thus offering the potential for fabrication of single-crystal polymer transistors. Good transistor stability under static storage and operation in a low-humidity air environment was demonstrated, with charge-carrier field-effect mobilities of 0.2–0.6 cm2 V−1 s−1 achieved under nitrogen.

Ge/Si nanowire heterostructures as high-performance field-effect transistors

Abstract: Field-effect transistors (FETs) based on semi-conductor nanowires could one day replace standard silicon MOSFETs in miniature electronic circuits. MOSFETs, or metal-oxide semiconductor field-effect transistors, are a type of transistor used for high-speed switching and in a computer's integrated circuits. A specially designed nanowire with a germanium shell and silicon core has shown promise as a nanometre-scale field-effect transistor: it has a near-perfect channel for electronic conduction. Now, in transistor configuration, this germanium/silicon nanowire is shown to have properties including high conductance and short switching time delay that are better than state-of-the-art silicon MOSFETs. In a transistor configuration, a new germanium/silicon nanowire has characteristics such as conductance, on-current and switching time delay that are better than those of state-of-the-art silicon metal-oxide-semiconductor field-effect transitors. Semiconducting carbon nanotubes1,2 and nanowires3 are potential alternatives to planar metal-oxide-semiconductor field-effect transistors (MOSFETs)4 owing, for example, to their unique electronic structure and reduced carrier scattering caused by one-dimensional quantum confinement effects1,5. Studies have demonstrated long carrier mean free paths at room temperature in both carbon nanotubes1,6 and Ge/Si core/shell nanowires7. In the case of carbon nanotube FETs, devices have been fabricated that work close to the ballistic limit8. Applications of high-performance carbon nanotube FETs have been hindered, however, by difficulties in producing uniform semiconducting nanotubes, a factor not limiting nanowires, which have been prepared with reproducible electronic properties in high yield as required for large-scale integrated systems3,9,10. Yet whether nanowire field-effect transistors (NWFETs) can indeed outperform their planar counterparts is still unclear4. Here we report studies on Ge/Si core/shell nanowire heterostructures configured as FETs using high-κ dielectrics in a top-gate geometry. The clean one-dimensional hole-gas in the Ge/Si nanowire heterostructures7 and enhanced gate coupling with high-κ dielectrics give high-performance FETs values of the scaled transconductance (3.3 mS µm-1) and on-current (2.1 mA µm-1) that are three to four times greater than state-of-the-art MOSFETs and are the highest obtained on NWFETs. Furthermore, comparison of the intrinsic switching delay, τ = CV/I, which represents a key metric for device applications4,11, shows that the performance of Ge/Si NWFETs is comparable to similar length carbon nanotube FETs and substantially exceeds the length-dependent scaling of planar silicon MOSFETs.

High-mobility thin-film transistor with amorphous InGaZnO4 channel fabricated by room temperature rf-magnetron sputtering

Abstract: Thin-film transistors (TFTs) were fabricated using amorphous indium gallium zinc oxide (a-IGZO) channels by rf-magnetron sputtering at room temperature. The conductivity of the a-IGZO films was controlled from ∼10−3to10−6Scm−1 by varying the mixing ratio of sputtering gases, O2∕(O2+Ar), from ∼3.1% to 3.7%. The top-gate-type TFTs operated in n-type enhancement mode with a field-effect mobility of 12cm2V−1s−1, an on-off current ratio of ∼108, and a subthreshold gate voltage swing of 0.2Vdecade−1. It is demonstrated that a-IGZO is an appropriate semiconductor material to produce high-mobility TFTs at low temperatures applicable to flexible substrates by a production-compatible means.

Field-effect transistor including transparent oxide and light-shielding member, and display utilizing the transistor

Abstract: A field-effect transistor includes a substrate, a source electrode, a drain electrode, a gate electrode, a gate-insulating film, and an active layer. The active layer contains an oxide having a transmittance of 70% or more in the wavelength range of 400 to 800 nm. A light-shielding member is provided as a light-shielding structure for the active layer, for example, on the bottom face of the substrate.

Low voltage flexible organic/transparent transistor for selective gas sensing, photodetecting and CMOS device applications

Abstract: A thin film transistor (TFT) includes a source electrode, a drain electrode, and a gate electrode. A gate insulator is coupled to the source electrode, drain electrode, and gate electrode. The gate insulator includes room temperature deposited high-K materials so as to allow said thin film transistor to operate at low operating voltage.

Fused nanocrystal thin film semiconductor and method

Abstract: A thin film semiconductor and a method of its fabrication use induced crystallization and aggregation of a nanocrystal seed layer to form a merged-domain layer. The nanocrystal seed layer is deposited onto a substrate surface within a defined boundary. A reaction temperature below a boiling point of a reaction solution is employed. A thin film metal-oxide transistor and a method of its production employ the thin film semiconductor as a channel of the transistor. The merged-domain layer exhibits high carrier mobility.

Patterning organic single-crystal transistor arrays.

Abstract: Organic flexible electronics are being developed for computer displays, radio frequency identification tags, sensors and devices that have not been dreamt of yet. Practical applications so far are few, as their electrical performance is poor compared with conventional electronics. In terms of charge carrier mobility, however, field-effect transistors made of organic single crystals have a very high performance. The obstacle to the use of single-crystal devices is that they have to be individually hand-made. The report of a method of fabricating large arrays of high performance transistor devices by direct patterning of single crystals onto clean silicon surfaces or flexible plastics may help to change that. The new method retains the high performance of field-effect transistors even after significant bending. Field-effect transistors made of organic single crystals are ideal for studying the charge transport characteristics of organic semiconductor materials1. Their outstanding device performance2,3,4,5,6,7,8, relative to that of transistors made of organic thin films, makes them also attractive candidates for electronic applications such as active matrix displays and sensor arrays. These applications require minimal cross-talk between neighbouring devices. In the case of thin film systems, simple patterning of the active semiconductor layer9,10 minimizes cross-talk. But when using organic single crystals, the only approach currently available for creating arrays of separate devices is manual selection and placing of individual crystals—a process prohibitive for producing devices at high density and with reasonable throughput. In contrast, inorganic crystals have been grown in extended arrays11,12,13, and efficient and large-area fabrication of silicon crystalline islands with high mobilities for electronic applications has been reported14,15. Here we describe a method for effectively fabricating large arrays of single crystals of a wide range of organic semiconductor materials directly onto transistor source–drain electrodes. We find that film domains of octadecyltriethoxysilane microcontact-printed onto either clean Si/SiO2 surfaces or flexible plastic provide control over the nucleation of vapour-grown organic single crystals. This allows us to fabricate large arrays of high-performance organic single-crystal field-effect transistors with mobilities as high as 2.4 cm2 V-1 s-1 and on/off ratios greater than 107, and devices on flexible substrates that retain their performance after significant bending. These results suggest that our fabrication approach constitutes a promising step that might ultimately allow us to utilize high-performance organic single-crystal field-effect transistors for large-area electronics applications.

Silicon Vertically Integrated Nanowire Field Effect Transistors

Abstract: Silicon nanowires have received considerable attention as transistor components because they represent a facile route toward sub-100-nm single-crystalline Si features. Herein we demonstrate the direct vertical integration of Si nanowire arrays into surrounding gate field effect transistors without the need for postgrowth nanowire assembly processes. The device fabrication allows Si nanowire channel diameters to be readily reduced to the 5-nm regime. These first-generation vertically integrated nanowire field effect transistors (VINFETs) exhibit electronic properties that are comparable to other horizontal nanowire field effect transistors (FETs) and may, with further optimization, compete with advanced solid-state nanoelectronic devices.

Heat Generation and Transport in Nanometer-Scale Transistors

Abstract: As transistor gate lengths are scaled towards the 10-nm range, thermal device design is becoming an important part of microprocessor engineering. Decreasing dimensions lead to nanometer-scale hot spots in the transistor drain region, which may increase the drain series and source injection electrical resistances. Such trends are accelerated by the introduction of novel materials and nontraditional transistor geometries, including ultrathin body, FinFET, or nanowire devices, which impede heat conduction. Thermal analysis is complicated by subcontinuum phenomena including ballistic electron transport, which reshapes the heat generation region compared with classical diffusion theory predictions. Ballistic phonon transport from the hot spot and between material boundaries impedes conduction cooling. The increased surface to volume ratio of novel transistor designs also leads to a larger contribution from material boundary thermal resistance. This paper surveys trends in transistor geometries and materials, from bulk silicon to carbon nanotubes, along with their implications for the thermal design of electronic systems

Sub-threshold Design for Ultra Low-Power Systems

Abstract: Origins of Weak Inversion (or Sub-threshold) Circuit Design.- Survey of Low-voltage Implementations.- Minimizing Energy Consumption.- EKV Model of the MOS Transistor.- Digital Logic.- Sub-threshold Memories.- Analog Circuits in Weak Inversion.- System Examples.

Spatial control of the recombination zone in an ambipolar light-emitting organic transistor

Abstract: Spatial control of the recombination zone in an ambipolar light-emitting organic transistor

Negative differential thermal resistance and thermal transistor

Abstract: We report on the first model of a thermal transistor to control heat flow. Like its electronic counterpart, our thermal transistor is a three-terminal device with the important feature that the current through the two terminals can be controlled by small changes in the temperature or in the current through the third terminal. This control feature allows us to switch the device between “off” (insulating) and “on” (conducting) states or to amplify a small current. The thermal transistor model is possible because of the negative differential thermal resistance.

A 13.56-MHz RFID System Based on Organic Transponders

Abstract: RFID tags based on organic transistors are described, discussing in detail the IC blocks used to build the logic and the radio. Tags energized and read out at 13.56 MHz, de facto standard frequency for item-level identification, have been tested and enabled for the first time multiple-object identification, using different 6-bit codes. A complete 64-bit transponder, the most complex organic RFID tag reported to date, operates at 125 kHz and employs 1938 transistors

Analytical loss model of power MOSFET

Abstract: An accurate analytical model is proposed in this paper to calculate the power loss of a metal-oxide semiconductor field-effect transistor. The nonlinearity of the capacitors of the devices and the parasitic inductance in the circuit, such as the source inductor shared by the power stage and driver loop, the drain inductor, etc., are considered in the model. In addition, the ringing is always observed in the switching power supply, which is ignored in the traditional loss model. In this paper, the ringing loss is analyzed in a simple way with a clear physical meaning. Based on this model, the circuit power loss could be accurately predicted. Experimental results are provided to verify the model. The simulation results match the experimental results very well, even at 2-MHz switching frequency.

Realization of a silicon nanowire vertical surround-gate field-effect transistor.

Abstract: Semiconducting nanowires have recently attracted considerable attention. With their unique electrical and optical properties, they offer interesting perspectives for basic research as well as for technology. A variety of technical applications, such as nanowires as parts of sensors, and electronic and photonic devices have already been demonstrated. In particular, electronic applications come more and more into focus, as the ongoing miniaturization in microelectronics demands new innovative solutions. Semiconducting nanowires, in particular epitaxially grown silicon (Si) nanowires, are considered as promising candidates for post-CMOS (CMOS: complementary metal–oxide semiconductor) logic elements owing to their potential compatibility with existing CMOS technology. One major advantage of vapor–liquid– solid(VLS-) grown nanowires compared to top-down fabricated devices is that they have well-defined surfaces. This reduces surface scattering, an issue which becomes important for devices on the nanoscale. Moreover, epitaxially grown nanowires circumvent the problem of handling and positioning nanometer-sized objects that arises in the conventional pick-and-place approach, where devices are fabricated by manipulating horizontally lying VLS-grown nanowires. The first step towards a technical realization of a nanowire logic element is the design and manufacturing of a nanowire transistor. The epitaxial growth of vertical nanowires offers advantages over other approaches: For example, the transistor gate can be wrapped around the vertically oriented nanowire. Such a wrapped-around gate allows better electrostatic gate control of the conducting channel and offers the potential to drive more current per device area than is possible in a conventional planar architecture. In this Communication, a generic process for fabricating a vertical surround-gate field-effect transistor (VS-FET) based on epitaxially grown nanowires is described. Exemplarily, we used Si nanowires and present a first electrical characterization proving the feasibility of the process developed and the basic functionality of this device. Figure 1a shows a schematic cross section through a conventional p-type MOSFET. In such a device, an inversion channel can be created close to the gate by applying a negative gate voltage. This forms a conducting channel that connects the p-doped regions between the source and drain contacts electrically. Using this concept, a silicon nanowire VS-FET would ideally require a nanowire that is n-doped in the region of the gate and p-doped elsewhere. Unfortunately, such a p-n-p structure with abrupt transitions appears difficult to realize if the nanowires are grown by means of the vapor–liquid–solid mechanism using gold as a catalyst. The difficulty here is that the dopant atoms, which are dissolved in the catalyst droplet, might act as a reservoir, thus creating a graded transition when switching to another dopant. Therefore, we used a structure consisting of an n-doped silicon nanowire grown on a p-type substrate (see Figure 1b). If the gate–drain and gate–source distances are not too long, it is electrostatically still possible to create an inversion channel along the length of the entire wire. In the proposed configuration, the p–n junction at the source contact (Figure 1a) is replaced by a Au/n-Si Schottky contact at the nanowire tip. In order to investigate the influence of the Au/n-Si Schottky contact on the nanowire (current–voltage) I–V characteristics, an array of n-doped nanowires vertically grown on an n-type (111)-oriented substrate was imbedded in a spin-coated SiO2 matrix. After removing the thin SiO2 coverage from the Au tips by a short reactive ion etching, contacts 0.6 mm in size were defined by evaporating aluminum onto the sample, such that approximately 10 nanowires were contacted in parallel. The temperature-dependent measurements (shown in Figure 2) were performed by applying a voltage to the Si substrate, while the Al top contact was held at a constant potential. The measurements reveal a strong rectifying behavior with a thermally activated current possessing an activation energy of 0.6 eV. This can be explained by the Au/n-Si Schottky contact dominating the I–V behavior. The fact that the Schottky contact is forward-biased for negative voltages furthermore proves that, as expected, electrons act as majority charge carries. Figure 1. Schematics of a) a conventional p-channel MOSFET and b) a silicon nanowire vertical surround-gate field-effect transistor.

Solution-processed silicon films and transistors.

Abstract: The manufacture of silicon semiconductor devices involves complicated photolithography and expensive machinery, so many researchers are seeking alternative semiconductor materials that can be handled by simple processes such as spin-coating or printing. Organic semiconductors are the most promising candidates but they still lack performance and reliability. Shimoda et al. have taken a different approach, printing a silicon transistor itself, not a substitute. They successfully fabricated polycrystalline silicon transistors by spin-coating a novel liquid precursor. This solution-based approach can also be adapted for ‘ink-jet’ printing of transistors. The development of a process whereby silicon can be prepared from a liquid allows the printing of semiconductor devices directly from solution. The use of solution processes—as opposed to conventional vacuum processes and vapour-phase deposition—for the fabrication of electronic devices has received considerable attention for a wide range of applications1,2,3,4,5,6,7, with a view to reducing processing costs. In particular, the ability to print semiconductor devices using liquid-phase materials could prove essential for some envisaged applications, such as large-area flexible displays. Recent research in this area has largely been focused on organic semiconductors8,9,10,11, some of which have mobilities comparable to that of amorphous silicon11 (a-Si); but issues of reliability remain. Solution processing of metal chalcogenide semiconductors to fabricate stable and high-performance transistors has also been reported12,13. This class of materials is being explored as a possible substitute for silicon, given the complex and expensive manufacturing processes required to fabricate devices from the latter. However, if high-quality silicon films could be prepared by a solution process, this situation might change drastically. Here we demonstrate the solution processing of silicon thin-film transistors (TFTs) using a silane-based liquid precursor. Using this precursor, we have prepared polycrystalline silicon (poly-Si) films by both spin-coating and ink-jet printing, from which we fabricate TFTs with mobilities of 108 cm2 V-1 s-1 and 6.5 cm2 V-1 s-1, respectively. Although the processing conditions have yet to be optimized, these mobilities are already greater than those that have been achieved in solution-processed organic TFTs, and they exceed those of a-Si TFTs (≤ 1 cm2 V-1 s-1).

Vertical high-mobility wrap-gated InAs nanowire transistor

Abstract: In this letter, the authors demonstrate a vertical wrap-gated field-effect transistor based on InAs nanowires [Proc. DRC, 2005, p. 157]. The nanowires have a diameter of 80 nm and are grown using selective epitaxy; a matrix of typically 10 /spl times/ 10 vertically standing wires is used as channel in the transistor. The authors measure current saturation at V/sub ds/=0.15 V (V/sub g/=0 V), and a high mobility, compared to the previous nanowire transistors, is deduced.

High-performance transparent inorganic–organic hybrid thin-film n-type transistors

Abstract: High-performance thin-film transistors (TFTs) that can be fabricated at low temperature and are mechanically flexible, optically transparent and compatible with diverse substrate materials are of great current interest. To function at low biases to minimize power consumption, such devices must also contain a high-mobility semiconductor and/or a high-capacitance gate dielectric. Here we report transparent inorganic-organic hybrid n-type TFTs fabricated at room temperature by combining In2O3 thin films grown by ion-assisted deposition, with nanoscale organic dielectrics self-assembled in a solution-phase process. Such TFTs combine the advantages of a high-mobility transparent inorganic semiconductor with an ultrathin high-capacitance/low-leakage organic gate dielectric. The resulting, completely transparent TFTs exhibit excellent operating characteristics near 1.0 V with large field-effect mobilities of >120 cm2 V(-1) s(-1), drain-source current on/off modulation ratio (I(on)/I(off)) approximately 10(5), near-zero threshold voltages and sub-threshold gate voltage swings of 90 mV per decade. The results suggest new strategies for achieving 'invisible' optoelectronics.

Semiconductor image sensor module and method of manufacturing the same

Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.

Charge-Based MOS Transistor Modeling - The EKV Model for Low-Power and RF IC Design

Abstract: Foreword. Preface. List of Symbols. 1. Introduction. 1.1 The Importance of Device Modeling for IC Design. 1.2 A Short History of the EKV MOST Model. 1.3 The Book Structure. PART I: THE BASIC LONG-CHANNELINTRINSIC CHARGE-BASED MODEL. 2. Introduction. 2.1 The N-channel Transistor Structure. 2.2 Definition of charges, current, potential and electric fields. 2.3 Transistor symbol and P-channel transistor. 3. The Basic Charge Model. 3.1 Poisson's Equation and Gradual Channel Approximation. 3.2 Surface potential as a Function of Gate Voltage. 3.3 Gate Capacitance. 3.4 Charge Sheet Approximation. 3.5 Density of Mobile Inverted Charge. 3.6 Charge-Potential Linearization. 4. Static Drain Current. 4.1 Drain Current Expression. 4.2 Forward and Reverse Current Components. 4.3 Modes of Operation. 4.4 Model of Drain Current Based on Charge Linearization. 4.5 Fundamental Property: Validity and Application. 4.6 Channel Length Modulation. 5. The Small-Signal Model. 5.1 The Static Small-Signal Model. 5.2 A General Non-Quasi-Static Small-Signal Model. 5.3 The Quasi-Static Dynamic Small-Signal Model. 6. The Noise Model. 6.1 Noise Calculation Methods. 6.2 Low-Frequency Channel Thermal Noise. 6.3 Flicker Noise. 6.4 Appendices. Appendix : The Nyquist and Bode Theorems. Appendix : General Noise Expression. 7. Temperature Effects and Matching. 7.1 Introduction. 7.2 Temperature Effects. PART II: THE EXTENDED CHARGE-BASED MODEL. 8. Non-Ideal Effects Related to the Vertical Dimension. 8.1 Introduction. 8.2 Mobility Reduction Due to the Vertical Field. 8.3 Non-Uniform Vertical Doping. 8.4 Polysilicon Depletion. 8.4.1 Definition of the Effect. 8.5 Band Gap Widening. 8.6 Gate Leakage Current. 9. Short-Channel Effects. 9.1 Velocity Saturation. 9.2 Channel Length Modulation. 9.3 Drain Induced Barrier Lowering. 9.4 Short-Channel Thermal Noise Model. 10. The Extrinsic Model. 10.1 Extrinsic Part of the Device. 10.2 Access Resistances. 10.3 Overlap Regions. 10.4 Source and Drain Junctions. 10.5 Extrinsic Noise Sources. PART III: THE HIGH-FREQUENCY MODEL. 11. Equivalent Circuit at RF. 11.1 RF MOS Transistor Structure and Layout. 11.2 What Changes at RF?. 11.3 Transistor Figures of Merit. 11.4 Equivalent Circuit at RF. 12. The Small-Signal Model at RF. 12.1 The Equivalent Small-Signal Circuit at RF. 12.2 Y-Parameters Analysis. 12.3 The Large-Signal Model at RF. 13. The Noise Model at RF. 13.1 The HF Noise Parameters. 13.2 The High-Frequency Thermal Noise Model. 13.3 HF Noise Parameters of a Common-Source Amplifier. References. Index.

High‐Performance Organic Single‐Crystal Transistors on Flexible Substrates

Abstract: The electronic properties of organic single crystals have been intensely studied for well over 40 years. Until recently, organic single-crystal field-effect transistors have generated results that are comparable to and sometimes better in performance than hydrogenated amorphous silicon. Organic thin-film transistors are being actively pursued for a broad area of electronic applications, but their charge-carrier mobilities are limited by structural imperfections (i.e., grain boundaries) and impurities. Organic single crystals, on the other hand, have been limited to charge-transport studies mainly because the fabrication of single-crystal transistors poses a technological challenge. Novel methods for fabricating single-crystal devices include the flip-crystal technique, elastomeric stamp platforms, and freestanding devices, where the source–drain electrodes, dielectric, and gate are all fabricated onto the crystal surface. For the most part, a relatively thick and rigid single crystal is employed (5–500 lm thick). Because the fragility makes them difficult to handle, their use has been restricted to simple and basic devices and wide-ranging applications in sensors or plastic transistors for flexible electronics have not yet been possible. Thus, there is a strong need for the development of mechanically flexible, nondestructive, single-crystal devices with prospective applications in organic electronics while maintaining the intrinsic properties and characteristics of organic single crystals. We demonstrate field-effect transistors fabricated from thin and conformable organic single crystals. We report on proofof-concept “flexible” organic single-crystal field-effect transistors with performance exceeding those of previously reported organic thin-film flexible devices. Rubrene single-crystal devices constructed on low-cost flexible substrates (Fig. 1b) yielded mobilities as high as 4.6 cm V s and on/off ratios of approximately 10.

Germanium-source tunnel field effect transistors with record high I ON /I OFF

Abstract: Tunnel field effect transistors (TFETs) with record high I ON /I OFF ratio (≫106) for low-voltage (0.5V) operation are achieved by using germanium in the source region to achieve a small tunnel bandgap. The measured data are well explained by the theoretical band-to-band tunneling current model. Using the calibrated analytical model, the energy-delay performance of TFET-based technology is compared against that of conventional CMOS technology, at the 65nm node. The TFET is projected to provide dramatic improvement in energy efficiency for performance in the range up to ∼0.5GHz.

Display Device and Electronic Apparatus

Abstract: A display device in which variations in luminance due to variations in characteristics of transistors are reduced, and image quality degradation due to variations in resistance values is prevented The invention comprises a transistor whose channel portion is formed of an amorphous semiconductor or an organic semiconductor, a connecting wiring connected to a source electrode or a drain electrode of the transistor, a light emitting element having a laminated structure which includes a pixel electrode, an electro luminescent layer, and a counter electrode, an insulating layer surrounding an end portion of the pixel electrode, and an auxiliary wiring formed in the same layer as a gate electrode of the transistor, a connecting wiring, or the pixel electrode Further, the connecting wiring is connected to the pixel electrode, and the auxiliary wiring is connected to the counter electrode via an opening portion provided in the insulating layer

High performance n-channel organic field-effect transistors and ring oscillators based on C60 fullerene films

Abstract: We report on organic n-channel field-effect transistors and circuits based on C60 films grown by hot wall epitaxy. Electron mobility is found to be dependent strongly on the substrate temperature during film growth and on the type of the gate dielectric employed. Top-contact transistors employing LiF∕Al electrodes and a polymer dielectric exhibit maximum electron mobility of 6cm2∕Vs. When the same films are employed in bottom-contact transistors, using SiO2 as gate dielectric, mobility is reduced to 0.2cm2∕Vs. By integrating several transistors we are able to fabricate high performance unipolar (n-channel) ring oscillators with stage delay of 2.3μs.

Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering

Abstract: We have combined the benefits of the fully depleted tri-gate transistor architecture with high-k gate dielectrics, metal gate electrodes and strain engineering. High performance NMOS and PMOS trigate transistors are demonstrated with IDSAT=1.4 mA/mum and 1.1 mA/mum respectively (IOFF=100nA/mum, VCC =1.1V and LG=40nm) with excellent short channel effects (SCE)-DIBL and subthreshold swing, DeltaS. The contributions of strain, the lang100rang vs. lang110rang substrate orientations, high-k gate dielectrics, and low channel doping are investigated for a variety of channel dimensions and FIN profiles. We observe no evidence of early parasitic corner transistor turn-on in the current devices which can potentially degrade ION-IOFF and DeltaS

Backplanes for display applications, and components for use therein

Abstract: A thin-film transistor includes a gate electrode having a first gate electrode edge and a second gate electrode edge opposite the first gate electrode edge. The TFT also includes a drain electrode having a first drain electrode edge that overlaps the first gate electrode edge, and a second drain electrode edge that overlaps the second gate electrode edge. A method for fabricating a diode array for use in a display includes deposition of a conductive layer adjacent to a substrate, deposition of a doped semiconductor layer adjacent to the substrate, and deposition of an undoped semiconductor layer adjacent to the substrate. A display pixel unit provides reduced capacitative coupling between a pixel electrode and a source line. The unit includes a transistor, the pixel electrode, and the source line. The source line includes an extension that provides a source for the transistor. A patterned conductive portion is disposed adjacent to the source line. Another display pixel unit provides reduced pixel electrode voltage shifts. The unit includes a transistor, a pixel electrode, a source line and a balance line. The invention also provides a driver for driving a display provided with such a balance line.