Showing papers on "Transistor published in 2007"

Substrate-induced bandgap opening in epitaxial graphene

Abstract: Graphene has shown great application potential as the hostmaterial for next-generation electronic devices. However, despite itsintriguing properties, one of the biggest hurdles for graphene to beuseful as an electronic material is the lack of an energy gap in itselectronic spectra. This, for example, prevents the use of graphene inmaking transistors. Although several proposals have been made to open agap in graphene's electronic spectra, they all require complexengineering of the graphene layer. Here, we show that when graphene isepitaxially grown on SiC substrate, a gap of ~;0.26 eV is produced. Thisgap decreases as the sample thickness increases and eventually approacheszero when the number of layers exceeds four. We propose that the originof this gap is the breaking of sublattice symmetry owing to thegraphene-substrate interaction. We believe that our results highlight apromising direction for band gap engineering of graphene.

Substrate-induced band gap opening in epitaxial graphene

Abstract: Graphene has shown great application potentials as the host material for next generation electronic devices. However, despite its intriguing properties, one of the biggest hurdles for graphene to be useful as an electronic material is its lacking of an energy gap in the electronic spectra. This, for example, prevents the use of graphene in making transistors. Although several proposals have been made to open a gap in graphene's electronic spectra, they all require complex engineering of the graphene layer. Here we show that when graphene is epitaxially grown on the SiC substrate, a gap of ~ 0.26 is produced. This gap decreases as the sample thickness increases and eventually approaches zero when the number of layers exceeds four. We propose that the origin of this gap is the breaking of sublattice symmetry owing to the graphene-substrate interaction. We believe our results highlight a promising direction for band gap engineering of graphene.

Ultralow-power organic complementary circuits

Abstract: Organic transistors and circuits show great promise for the realization of futuristic roll-up displays, adaptive sensors for humanoid robots and ubiquitous radio-frequency identification tags. But today's organic circuits require operating voltages of 15 to 30 volts (10 to 20 batteries' worth), and they draw enough power to drain those batteries in a day. To overcome this major hurdle, Hagen Klauk et al. have developed a method of fabricating organic circuits that run on a single 1.5-volt battery for several years. The key to the method is the use of a layer of an insulating organic material just one molecule thick; although the layer is very thin, it leaks only a small amount of current, while it provides for a large capacitance. Two different types of organic semiconductors are used to fabricate transistors, logic gates and ring oscillators. A report of the development of organic electronic circuits, which require only a single 1.5V battery and last for several years. The main ingredient is the use of a single layer of an insulating organic material. Although the layer is very thin, it leaks only small amount of current, while providing for a large capacitance. The prospect of using low-temperature processable organic semiconductors to implement transistors, circuits, displays and sensors on arbitrary substrates, such as glass or plastics, offers enormous potential for a wide range of electronic products1. Of particular interest are portable devices that can be powered by small batteries or by near-field radio-frequency coupling. The main problem with existing approaches is the large power consumption of conventional organic circuits, which makes battery-powered applications problematic, if not impossible. Here we demonstrate an organic circuit with very low power consumption that uses a self-assembled monolayer gate dielectric and two different air-stable molecular semiconductors (pentacene and hexadecafluorocopperphthalocyanine, F16CuPc). The monolayer dielectric is grown on patterned metal gates at room temperature and is optimized to provide a large gate capacitance and low gate leakage currents. By combining low-voltage p-channel and n-channel organic thin-film transistors in a complementary circuit design, the static currents are reduced to below 100 pA per logic gate. We have fabricated complementary inverters, NAND gates, and ring oscillators that operate with supply voltages between 1.5 and 3 V and have a static power consumption of less than 1 nW per logic gate. These organic circuits are thus well suited for battery-powered systems such as portable display devices2 and large-surface sensor networks3 as well as for radio-frequency identification tags with extended operating range4.

A single-photon transistor using nanoscale surface plasmons

Abstract: Photons rarely interact—which makes it challenging to build all-optical devices in which one light signal controls another. Even in nonlinear optical media, in which two beams can interact because of their influence on the medium’s refractive index, this interaction is weak at low light levels. Here, we propose a novel approach to realizing strong nonlinear interactions at the single-photon level, by exploiting the strong coupling between individual optical emitters and propagating surface plasmons confined to a conducting nanowire. We show that this system can act as a nonlinear two-photon switch for incident photons propagating along the nanowire, which can be coherently controlled using conventional quantum-optical techniques. Furthermore, we discuss how the interaction can be tailored to create a single-photon transistor, where the presence (or absence) of a single incident photon in a ‘gate’ field is sufficient to allow (or prevent) the propagation of subsequent ‘signal’ photons along the wire.

Structure with transistor

Abstract: A structure with a transistor is disclosed comprising a substrate, a gas barrier layer on the substrate, and a transistor on the gas barrier layer. The transistor can include an oxide semiconductor layer. The oxide semiconductor layers can comprise In—Ga—Zn—O. A display, such as a liquid crystal display, can have such a structure.

Gate Injection Transistor (GIT)—A Normally-Off AlGaN/GaN Power Transistor Using Conductivity Modulation

Abstract: We have developed a normally-off GaN-based transistor using conductivity modulation, which we call a gate injection transistor (GIT). This new device principle utilizes hole-injection from the p-AlGaN to the AlGaN/GaN heterojunction, which simultaneously increases the electron density in the channel, resulting in a dramatic increase of the drain current owing to the conductivity modulation. The fabricated GIT exhibits a threshold voltage of 1.0 V with a maximum drain current of 200 mA/mm, in which a forward gate voltage of up to 6 V can be applied. The obtained specific ON-state resistance (RON . A) and the OFF-state breakdown voltage (BV ds) are 2.6 mOmega . cm2 and 800 V, respectively. The developed GIT is advantageous for power switching applications.

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS

Abstract: A 275mm2 network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz. The 15-F04 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. The 65nm 100M transistor die is designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.

Very high-mobility organic single-crystal transistors with in-crystal conduction channels

Abstract: Very high-mobility organic transistors are fabricated with purified rubrene single crystals and high-density organosilane self-assembled monolayers. The interface with minimized surface levels allows carriers to distribute deep into the crystals by more than a few molecular layers under weak gate electric fields, so that the inner channel plays a significant part in the transfer performance. With the in-crystal carriers less affected by scattering mechanisms at the interface, the maximum transistor mobility reaches 18cm2∕Vs and the contact-free intrinsic mobility turned out to be 40cm2∕Vs as the result of four-terminal measurement. These are the highest values ever reported for organic transistors.

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking

Abstract: This paper presents a complete circuit-compatible compact model for single-walled carbon-nanotube field-effect transistors (CNFETs) as an extension to Part 1 of this two-part paper. For the first time, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE. In addition to the nonidealities included in the companion paper, this paper includes the elastic scattering in the channel region, the resistive source/drain (S/D), the Schottky-barrier resistance, and the parasitic gate capacitances. More than one nanotube per device can be modeled. Compared to silicon technology, the CNFETs show much better device performance based on the intrinsic gate-delay metric (six times for nFET and 14 times for pFET) than the MOSFET device at the 32-nm node, even with device nonidealities. This large speed improvement is significantly degraded (by a factor of five to eight) by interconnect capacitance in a real circuit environment. We performed circuit-performance comparison with all the standard digital library cells between CMOS random logic and CNFET random logic with HSPICE simulation. Compared to CMOS circuits, the CNFET circuits with one to ten carbon nanotubes per device is about two to ten times faster, the energy consumption per cycle is about seven to two times lower, and the energy-delay product is about 15-20 times lower, considering the realistic layout pattern and the interconnect wiring capacitance.

Semiconductor apparatus and method of manufacturing the same

Abstract: It is an object of the present invention to provide a technology of controlling a threshold voltage of a thin film transistor in which an amorphous oxide film is applied to a channel layer. There is provided a semiconductor apparatus including a plurality of kinds of transistors, each of the plurality of kinds of transistors including a channel layer made of an amorphous oxide containing a plurality of kinds of metal elements; and threshold voltages of the plurality of kinds of transistors are different from one another by changing an element ratio of the amorphous oxide.

Fabrication of fully transparent nanowire transistors for transparent and flexible electronics

Abstract: The development of optically transparent and mechanically flexible electronic circuitry is an essential step in the effort to develop next-generation display technologies, including 'see-through' and conformable products. Nanowire transistors (NWTs) are of particular interest for future display devices because of their high carrier mobilities compared with bulk or thin-film transistors made from the same materials, the prospect of processing at low temperatures compatible with plastic substrates, as well as their optical transparency and inherent mechanical flexibility. Here we report fully transparent In(2)O(3) and ZnO NWTs fabricated on both glass and flexible plastic substrates, exhibiting high-performance n-type transistor characteristics with approximately 82% optical transparency. These NWTs should be attractive as pixel-switching and driving transistors in active-matrix organic light-emitting diode (AMOLED) displays. The transparency of the entire pixel area should significantly enhance aperture ratio efficiency in active-matrix arrays and thus substantially decrease power consumption.

Downscaling of self-aligned, all-printed polymer thin-film transistors

Abstract: Printing is an emerging approach for low-cost, large-area manufacturing of electronic circuits, but it has the disadvantages of poor resolution, large overlap capacitances, and film thickness limitations, resulting in slow circuit speeds and high operating voltages. Here, we demonstrate a self-aligned printing approach that allows downscaling of printed organic thin-film transistors to channel lengths of 100–400 nm. The use of a crosslinkable polymer gate dielectric with 30–50 nm thickness ensures that basic scaling requirements are fulfilled and that operating voltages are below 5 V. The device architecture minimizes contact resistance effects, enabling clean scaling of transistor current with channel length. A self-aligned gate configuration minimizes parasitic overlap capacitance to values as low as 0.2–0.6 pF mm−1, and allows transition frequencies of fT = 1.6 MHz to be reached. Our self-aligned process provides a way to improve the performance of printed organic transistor circuits by downscaling, while remaining compatible with the requirements of large-area, flexible electronics manufacturing.

Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio

Abstract: Sixty-gigahertz power (PA) and low-noise (LNA) amplifiers have been implemented, based on algorithmic design methodologies for mm-wave CMOS amplifiers, in a 90-nm RF-CMOS process with thick 9-metal-layer Cu backend and transistor fT/fMAX of 120 GHz/200 GHz. The PA, fabricated for the first time in CMOS at 60 GHz, operates from a 1.5-V supply with 5.2 dB power gain, a 3-dB bandwidth >13 GHz, a P 1dB of +6.4 dBm with 7% PAE and a saturated output power of +9.3 dBm at 60 GHz. The LNA represents the first 90-nm CMOS implementation at 60 GHz and demonstrates improvements in noise, gain and power dissipation compared to earlier 60-GHz LNAs in 160-GHz SiGe HBT and 0.13-mum CMOS technologies. It features 14.6 dB gain, an IIP 3 of -6.8 dBm, and a noise figure lower than 5.5 dB, while drawing 16 mA from a 1.5-V supply. The use of spiral inductors for on-chip matching results in highly compact layouts, with the total PA and LNA die areas with pads measuring 0.35times0.43 mm2 and 0.35times0.40 mm2, respectively

A large-area wireless power-transmission sheet using printed organic transistors and plastic MEMS switches

Abstract: A large-area wireless power-transmission sheet using printed organic transistors and plastic MEMS switches

A dielectric-modulated field-effect transistor for biosensing

Abstract: Interest in biosensors based on field-effect transistors (FETs), where an electrically operated gate controls the flow of charge through a semiconducting channel, is driven by the prospect of integrating biodetection capabilities into existing semiconductor technology. In a number of proposed FET biosensors, surface interactions with biomolecules in solution affect the operation of the gate or the channel. However, these devices often have limited sensitivity. We show here that a FET biosensor with a vertical gap is sensitive to the specific binding of streptavidin to biotin. The binding of the streptavidin changes the dielectric constant (and capacitance) of the gate, resulting in a large shift in the threshold voltage for operating the FET. The vertical gap is fabricated using simple thin-film deposition and wet-etching techniques. This may be an advantage over planar nanogap FETs, which require lithographic processing. We believe that the dielectric-modulated FET (DMFET) provides a useful approach towards biomolecular detection that could be extended to a number of other systems.

Tunnel field-effect transistor without gate-drain overlap

Abstract: Tunnel field-effect transistors are promising successors of metal-oxide-semiconductor field-effect transistors because of the absence of short-channel effects and of a subthreshold-slope limit. However, the tunnel devices are ambipolar and, depending on device material properties, they may have low on-currents resulting in low switching speed. The authors have generalized the tunnel field-effect transistor configuration by allowing a shorter gate structure. The proposed device is especially attractive for vertical nanowire-based transistors. As illustrated with device simulations, the authors’ more flexible configuration allows of the reduction of ambipolar behavior, the increase of switching speed, and the decrease of processing complexity.

Integrated nanoelectronics for the future

Abstract: Integrated electronics has come a long way since the invention of the transistor in 1947 and the fabrication of the first integrated circuit in 1958. Given feature sizes as small as a few nanometres, what will the future hold for integrated electronics?

Nano/CMOS architectures using a field-programmable nanowire interconnect

Abstract: A field-programmable nanowire interconnect (FPNI) enables a family of hybrid nano/CMOS circuit architectures that generalizes the CMOL (CMOS/molecular hybrid) approach proposed by Strukov and Likharev, allowing for simpler fabrication, more conservative process parameters, and greater flexibility in the choice of nanoscale devices. The FPNI improves on a field-programmable gate array (FPGA) architecture by lifting the configuration bit and associated components out of the semiconductor plane and replacing them in the interconnect with nonvolatile switches, which decreases both the area and power consumption of the circuit. This is an example of a more comprehensive strategy for improving the efficiency of existing semiconductor technology: placing a level of intelligence and configurability in the interconnect can have a profound effect on integrated circuit performance, and can be used to significantly extend Moore's law without having to shrink the transistors. Compilation of standard benchmark circuits onto FPNI chip models shows reduced area (8 × to 25 ×), reduced power, slightly lower clock speeds, and high defect tolerance—an FPNI chip with 20% defective junctions and 20% broken nanowires has an effective yield of 75% with no significant slowdown along the critical path, compared to a defect-free chip. Simulations show that the density and power improvements continue as both CMOS and nano fabrication parameters scale down, although the maximum clock rate decreases due to the high resistance of very small (<10 nm) metallic nanowires.

Low-Temperature, Solution-Processed, High-Mobility Polymer Semiconductors for Thin-Film Transistors

Abstract: Poly(4,8-dialkyl-2,6-bis(3-alkylthiophen-2-yl)benzo[1,2-b:4,5-b‘]dithiophene) 1 represents a new class of polymer semiconductors which self-assemble into higher structural orders without thermal annealing and provide excellent field-effect transistor performance with mobility up to 0.25 cm2 V-1 s-1 when used as a solution-processed thin-film semiconductor in thin-film transistors.

Light sensitive display

Abstract: A liquid crystal device includes a front electrode layer, a rear electrode layer, and a liquid crystal material located between the front electrode layer and the rear electrode layer. A first and second transistor each includes three terminals. The first transistor is a photo transistor. The first terminal of the first transistor electrically interconnected to a conductive electrode free from additional electrical elements therebetween. The second terminal of the first transistor is electrically interconnected to the conductive electrode free from additional electrical elements therebetween and the second terminal of the first transistor is maintained at the same potential as the conductive electrode. The first terminal of the first transistor and the second terminal of the first transistor electrically interconnected to one another free from additional electrical elements therebetween and the first terminal of the first transistor and the second terminal of the first transistor are maintained at the same potential. The second terminal of the first transistor is a gate of the first transistor. The third terminal of the first transistor electrically interconnected to the first terminal of the second transistor free from additional electrical elements therebetween and maintained at the same potential. The second transistor provides a readout function for the circuit. The second terminal of the second transistor electrically connected to one of the select electrodes. The second terminal of the second transistor is a gate of the second transistor. The third terminal of the second transistor is electrically interconnected to a readout system. The second transistor is substantially inhibited from receiving ambient light thereon. The first transistor is not substantially inhibited from receiving ambient light thereon. The first transistor and the second transistor being together with the rear electrode layer. The readout system determines a region of the device that experiences a change in the light level impinging on the device.

Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications

Abstract: Design strategy and efficiency optimization of ultrahigh-frequency (UHF) micro-power rectifiers using diode-connected MOS transistors with very low threshold voltage is presented. The analysis takes into account the conduction angle, leakage current, and body effect in deriving the output voltage. Appropriate approximations allow analytical expressions for the output voltage, power consumption, and efficiency to be derived. A design procedure to maximize efficiency is presented. A superposition method is proposed to optimize the performance of multiple-output rectifiers. Constant-power scaling and area-efficient design are discussed. Using a 0.18-mum CMOS process with zero-threshold transistors, 900-MHz rectifiers with different conversion ratios were designed, and extensive HSPICE simulations show good agreement with the analysis. A 24-stage triple-output rectifier was designed and fabricated, and measurement results verified the validity of the analysis

Fully transparent thin-film transistor devices based on SnO2 nanowires.

Abstract: We report on studies of field-effect transistor (FET) and transparent thin-film transistor (TFT) devices based on lightly Ta-doped SnO2 nano-wires. The nanowire-based devices exhibit uniform characteristics with average field-effect mobilities exceeding 100 cm2/V x s. Prototype nano-wire-based TFT (NW-TFT) devices on glass substrates showed excellent optical transparency and transistor performance in terms of transconductance, bias voltage range, and on/off ratio. High on-currents and field-effect mobilities were obtained from the NW-TFT devices even at low nanowire coverage. The SnO2 nanowire-based TFT approach offers a number of desirable properties such as low growth cost, high electron mobility, and optical transparency and low operation voltage, and may lead to large-scale applications of transparent electronics on diverse substrates.

Shift register circuit and image display apparatus containing the same

Abstract: A shift register circuit comprises a first transistor between a gate line output terminal and a clock terminal, a second transistor between the gate line output terminal and a first power supply terminal, a third transistor between a carry signal output terminal and the clock terminal and a fourth transistor between the carry signal output terminal and the first power supply terminal. Gates of the second and fourth transistors are connected to each other. A fifth transistor connected between a gate of the first transistor and a second power supply terminal and a sixth transistor connected between a gate of the third transistor and the second power supply terminal have gates both of which are connected to an input terminal. With this constitution, it is possible to suppress an influence between two synchronous output signals outputted from the shift register circuit.

Fabrication of Field-Effect Transistors from Hexathiapentacene Single-Crystal Nanowires

Abstract: This paper describes a simple, solution-phase route to the synthesis of bulk quantities of hexathiapentacene (HTP) single-crystal nanowires. These nanowires have also been successfully incorporated as the semiconducting material in field-effect transistors (FETs). For devices based on single nanowires, the carrier mobilities and current on/off ratios could be as high as 0.27 cm2/Vs and >103, respectively. For transistors fabricated from a network of nanowires, the mobilities and current on/off ratios could reach 0.057 cm2/Vs and >104, respectively. We have further demonstrated the use of nanowire networks in fabricating transistors on mechanically flexible substrates. Preliminary results show that these devices could withstand mechanical strain and still remain functional. The results from this study demonstrate the potential of utilizing solution-dispersible, nanostructured organic materials for use in low-cost, flexible electronic applications.

A Low-Temperature-Grown Oxide Diode as a New Switch Element for High-Density, Nonvolatile Memories†

Abstract: A one-bit cell of a general nonvolatile memory consists of a memory element and a switch element. Several memory elements have been tried given that any bistable states, that is, two charging states, two spin states, or two resistance states, can be used for a memory element. On the other hand, silicon-based transistors have been the most popularly used switch element. However, silicon-based transistors do not conform to high-density, nonvolatile memories with three-dimensional (3D) stack structures due to their high processing temperatures and the difficulty of growing high-quality epitaxial silicon over metals. Here, we show a low-temperaturegrown oxide diode, Pt/p-NiOx/n-TiOx/Pt, applied as a switch element for high-density, nonvolatile memories. The diode exhibits good rectifying characteristics at room temperature: a rectifying ratio of 10 at ± 3 V, a forward current density of up to ∼ 5×10 A cm, an ideality factor of 4.3, and a turn-on voltage of 2 V. Furthermore, we verify its ability to allow and deny access to the Pt/NiO/Pt memory element with two stable resistance states. Under the forward-bias condition, we could access the memory element and change the resistance state, although access was denied under the reverse bias condition. This one-diode/one-resistor (1D/1R) structure could be a promising building block for high-density, nonvolatile random-access memories with 3D stack structures. A p–n diode, like a transistor, is a fundamental circuit element for thin-film electronics. Until now, epitaxial silicon was most frequently used to fabricate p–n diodes in electronic devices with planar structures. However, to increase device density further, we require p–n diodes that are applicable to devices with 3D stack structures. Epitaxial silicon-based p–n diodes cannot be fabricated with stack structures as it is difficult to grow on a metal layer and high processing temperatures are required. On the other hand, although amorphous silicon allows for lower processing temperatures, it does not provide the required semiconducting performance. Therefore, to realize high-density electronic devices with 3D stack structures, we need new p–n diodes composed of semiconducting materials with low processing temperatures and high performance. In particular, new p–n diodes with low processing temperatures and high performance are indispensable to high-density, nonvolatile random-access memory devices. By replacing a transistor with a simpler diode as a switch element, there exists the possibility of producing memory cells with cross-point structures composed of bit lines and word lines perpendicular to each other, with a memory element lying between them. Theoretically, by utilizing this cross-point structure, the cell size can be scaled down to 4F (F: feature size used for patterning the cell), which is the smallest cell size attainable in nonvolatile memories with planar structures. Furthermore, by fabricating 3D stacks of the cross-point structure, the effective cell size can be scaled down to 2F, 1F, and so on. A common issue in realizing a cross-point structure is the availability of a thin-film diode with the high rectifying ratio and current density required for the switch element to access the memory element. Oxide based p–n diodes are good candidates to provide solutions to the issues associated with Si-based diodes. Most oxides, such as TiO2, [4] ZrO2, [5] ZnO, and indium tin oxide (ITO), are well-known n-type semiconductors that are characterized by the electron-transport properties of oxygen vacancies. As NiOx is a well-known p-type semiconductor beC O M M U N IC A IO N

New Generation of Z-RAM

Abstract: A new generation of the single transistor floating body DRAM is introduced for the first time. The new memory is largely based on the bipolar transistor existing in the MOS structure. The memory's main features are high margin, low-power consumption, and scalability.

Pixel circuit, active matrix apparatus and display apparatus

Abstract: A pixel circuit having a function of compensating for characteristic variation of an electro-optical element and threshold voltage variation of a transistor is formed from a reduced number of component elements. An input signal is sampled from a signal line so as to be held in a holding capacitor. The threshold voltage of the drive transistor is imparted to the holding capacitor in order to cancel an influence of the threshold voltage.

PEALD Deposition of a Silicon-Based Material

Abstract: A process for depositing a silicon-based material on a substrate uses the technology of plasma-enhanced atomic layer deposition. The process is carried out over several cycles, wherein each cycle includes: exposing the substrate to a first precursor, which is an organometallic silicon precursor; and applying a plasma of at least a second precursor, different from the first precursor. Semiconductor products such as 3D capacitors, vertical transistor gate spacers, and conformal transistor stressors are made from the process.