Showing papers on "Transistor published in 2022"

Vertical MoS2 transistors with sub-1-nm gate lengths

Abstract: Ultra-scaled transistors are of interest in the development of next-generation electronic devices1-3. Although atomically thin molybdenum disulfide (MoS2) transistors have been reported4, the fabrication of devices with gate lengths below 1 nm has been challenging5. Here we demonstrate side-wall MoS2 transistors with an atomically thin channel and a physical gate length of sub-1 nm using the edge of a graphene layer as the gate electrode. The approach uses large-area graphene and MoS2 films grown by chemical vapour deposition for the fabrication of side-wall transistors on a 2-inch wafer. These devices have On/Off ratios up to 1.02 × 105 and subthreshold swing values down to 117 mV dec-1. Simulation results indicate that the MoS2 side-wall effective channel length approaches 0.34 nm in the On state and 4.54 nm in the Off state. This work can promote Moore's law of the scaling down of transistors for next-generation electronics.

Advances in flexible organic field-effect transistors and their applications for flexible electronics

Abstract: Abstract Flexible electronics have suggested tremendous potential to shape human lives for more convenience and pleasure. Strenuous efforts have been devoted to developing flexible organic field-effect transistor (FOFET) technologies for rollable displays, bendable smart cards, flexible sensors and artificial skins. However, these applications are still in a nascent stage for lack of standard high-performance material stacks as well as mature manufacturing technologies. In this review, the material choice and device design for FOFET devices and circuits, as well as the demonstrated applications are summarized in detail. Moreover, the technical challenges and potential applications of FOFETs in the future are discussed.

High-performance inorganic metal halide perovskite transistors

Abstract: Abstract The p-type characteristic of solution-processed metal halide perovskite transistors means that they could be used in combination with their n-type counterparts, such as indium–gallium–zinc-oxide transistors, to create complementary metal–oxide–semiconductor-like circuits. However, the performance and stability of perovskite-based transistors do not yet match their n-type counterparts, which limit their broader application. Here we report high-performance p-channel perovskite thin-film transistors based on inorganic caesium tin triiodide semiconducting layers that have moderate hole concentrations and high Hall mobilities. The perovskite channels are formed by engineering the film composition and crystallization process using a tin-fluoride-modified caesium-iodide-rich precursor with lead substitution. The optimized transistors exhibit field-effect hole mobilities of over 50 cm 2 V −1 s −1 and on/off current ratios exceeding 10 8 , as well as high operational stability and reproducibility.

Long-Lived Organic Room-Temperature Phosphorescence from Amorphous Polymer Systems.

Abstract: ConspectusLong-lived organic room-temperature phosphorescence (RTP) materials have recently drawn extensive attention because of their promising applications in information security, biological imaging, optoelectronic devices, and intelligent sensors. In contrast to conventional fluorescence, the RTP phenomenon originates from the slow radiative transition of triplet excitons. Thus, enhancing the intersystem crossing (ISC) rate from the lowest excited singlet state (S1) to the excited triplet state and suppressing the nonradiative relaxation channels of the lowest excited triplet state (T1) are reasonable methods for realizing highly efficient RTP in purely organic materials. Over the past few decades, many strategies have been designed on the basis of the above two crucial factors. The introduction of heavy atoms, aromatic carbonyl groups, and other heteroatoms with abundant lone-pair electrons has been demonstrated to strengthen the spin-orbit coupling, thereby successfully facilitating the ISC process. Furthermore, the rigid environment is commonly constructed through crystal engineering to restrict intramolecular motions and intermolecular collisions to decrease excited-state energy dissipation. However, most crystal-based organic RTP materials suffer from poor processability, flexibility, and reproducibility, becoming a thorny obstacle to their practical application.Amorphous organic polymers with long-lived RTP characteristics are more competitive in materials science. The intertwined structures and long chains of polymers not only ensure the rigid environment with multiple interactions but also protect triplet excitons from the surroundings, which are conducive to realizing ultralong and bright RTP emission. Exploring the fabrication strategies, intrinsic mechanisms, and practical applications of organic long-lived RTP polymers is highly desirable but remains a formidable challenge. In particular, intelligent organic RTP polymer systems that are capable of dynamically responding to external stimuli (e.g., light, temperature, oxygen, and humidity) have been rarely reported. To develop multifunctional RTP materials and expand their potential applications, a great amount of effort has been expended.This Account gives a summary of the significant advances in amorphous organic RTP polymer systems, especially smart stimulus-responsive ones, focusing on the construction of a rigid environment to suppress nonradiative deactivation by abundant inter/intramolecular interactions. The typical interactions in RTP polymer systems mainly include hydrogen bonding, ionic bonding, and covalent bonding, which can change the molecular electronic structures and affect the energy dissipation channels of the excited states. An in-depth understanding of intrinsic mechanisms and an extensive exploration of potential applications for excitation-dependent color-tunable, ultraviolet (UV) irradiation-activated, temperature-dependent, water-responsive, and circularly polarized RTP polymer systems are distinctly illustrated in this Account. Furthermore, we propose some detailed perspectives in terms of materials design, mechanism exploration, and promising application potential with the hope to provide helpful guidance for the future development of amorphous organic RTP polymers.

Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors

Abstract: With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage1. This led to a fundamental change in the gate stack in 2008, the incorporation of high-dielectric-constant HfO2 (ref. 2), which remains the material of choice to date. Here we report HfO2-ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal-oxide-semiconductor capacitors is equivalent to an effective SiO2 thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-dielectric-constant gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current3. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO2-ZrO2 multilayers, stabilized with competing ferroelectric-antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO2-based high-dielectric-constant materials.

Scaled indium oxide transistors fabricated using atomic layer deposition

Abstract: In order to continue to improve integrated circuit performance and functionality, scaled transistors with short channel lengths and low thickness are needed. But the further scaling of silicon-based devices and the development of alternative semiconductor channel materials that are compatible with current fabrication processes is challenging. Here we report atomic-layer-deposited indium oxide transistors with channel lengths down to 8 nm, channel thicknesses down to 0.5 nm and equivalent dielectric oxide thickness down to 0.84 nm. Due to the scaled device dimensions and low contact resistance, the devices exhibit high on-state currents of 3.1 A/mm at a drain voltage of 0.5 V and a transconductance of 1.5 S/mm at a drain voltage 1 V. Our devices are a promising alternative channel material for scaled transistors with back-end-of-line processing compatibility.

Fully Printed Optoelectronic Synaptic Transistors Based on Quantum Dot-Metal Oxide Semiconductor Heterojunctions.

Abstract: Optoelectronic synaptic transistors with hybrid heterostructure channels have been extensively developed to construct artificial visual systems, inspired by the human visual system. However, optoelectronic transistors taking full advantages of superior optoelectronic synaptic behaviors, low-cost processes, low-power consumption, and environmental benignity remained a challenge. Herein, we report a fully printed, high-performance optoelectronic synaptic transistor based on hybrid heterostructures of heavy-metal-free InP/ZnSe core/shell quantum dots (QDs) and n-type SnO2 amorphous oxide semiconductors (AOSs). The elaborately designed heterojunction improves the separation efficiency of photoexcited charges, leading to high photoresponsivity and tunable synaptic weight changes. Under the coordinated modulation of electrical and optical modes, important biological synaptic behaviors, including excitatory postsynaptic current, short/long-term plasticity, and paired-pulse facilitation, were demonstrated with a low power consumption (∼5.6 pJ per event). The InP/ZnSe QD/SnO2 based artificial vision system illustrated a significantly improved accuracy of 91% in image recognition, compared to that of bare SnO2 based counterparts (58%). Combining the outstanding synaptic characteristics of both AOS materials and heterojunction structures, this work provides a printable, low-cost, and high-efficiency strategy to achieve advanced optoelectronic synapses for neuromorphic electronics and artificial intelligence.

Printed synaptic transistor-based electronic skin for robots to feel and learn

Abstract: An electronic skin (e-skin) for the next generation of robots is expected to have biological skin-like multimodal sensing, signal encoding, and preprocessing. To this end, it is imperative to have high-quality, uniformly responding electronic devices distributed over large areas and capable of delivering synaptic behavior with long- and short-term memory. Here, we present an approach to realize synaptic transistors (12-by-14 array) using ZnO nanowires printed on flexible substrate with 100% yield and high uniformity. The presented devices show synaptic behavior under pulse stimuli, exhibiting excitatory (inhibitory) post-synaptic current, spiking rate-dependent plasticity, and short-term to long-term memory transition. The as-realized transistors demonstrate excellent bio-like synaptic behavior and show great potential for in-hardware learning. This is demonstrated through a prototype computational e-skin, comprising event-driven sensors, synaptic transistors, and spiking neurons that bestow biological skin-like haptic sensations to a robotic hand. With associative learning, the presented computational e-skin could gradually acquire a human body-like pain reflex. The learnt behavior could be strengthened through practice. Such a peripheral nervous system-like localized learning could substantially reduce the data latency and decrease the cognitive load on the robotic platform.

High-mobility hydrogenated polycrystalline In2O3 (In2O3:H) thin-film transistors

Abstract: Oxide semiconductors have been extensively studied as active channel layers of thin-film transistors (TFTs) for electronic applications. However, the field-effect mobility (μFE) of oxide TFTs is not sufficiently high to compete with that of low-temperature-processed polycrystalline-Si TFTs (50-100 cm2V-1s-1). Here, we propose a simple process to obtain high-performance TFTs, namely hydrogenated polycrystalline In2O3 (In2O3:H) TFTs grown via the low-temperature solid-phase crystallization (SPC) process. In2O3:H TFTs fabricated at 300 °C exhibit superior switching properties with µFE = 139.2 cm2V-1s-1, a subthreshold swing of 0.19 Vdec-1, and a threshold voltage of 0.2 V. The hydrogen introduced during sputter deposition plays an important role in enlarging the grain size and decreasing the subgap defects in SPC-prepared In2O3:H. The proposed method does not require any additional expensive equipment and/or change in the conventional oxide TFT fabrication process. We believe these SPC-grown In2O3:H TFTs have a great potential for use in future transparent or flexible electronics applications.

High-mobility hydrogenated polycrystalline In2O3 (In2O3:H) thin-film transistors

Abstract: Oxide semiconductors have been extensively studied as active channel layers of thin-film transistors (TFTs) for electronic applications. However, the field-effect mobility (μFE) of oxide TFTs is not sufficiently high to compete with that of low-temperature-processed polycrystalline-Si TFTs (50-100 cm2V-1s-1). Here, we propose a simple process to obtain high-performance TFTs, namely hydrogenated polycrystalline In2O3 (In2O3:H) TFTs grown via the low-temperature solid-phase crystallization (SPC) process. In2O3:H TFTs fabricated at 300 °C exhibit superior switching properties with µFE = 139.2 cm2V-1s-1, a subthreshold swing of 0.19 Vdec-1, and a threshold voltage of 0.2 V. The hydrogen introduced during sputter deposition plays an important role in enlarging the grain size and decreasing the subgap defects in SPC-prepared In2O3:H. The proposed method does not require any additional expensive equipment and/or change in the conventional oxide TFT fabrication process. We believe these SPC-grown In2O3:H TFTs have a great potential for use in future transparent or flexible electronics applications.

Van der Waals integration of high-κ perovskite oxides and two-dimensional semiconductors

Abstract: Abstract Two-dimensional semiconductors can be used to build next-generation electronic devices with ultrascaled channel lengths. However, semiconductors need to be integrated with high-quality dielectrics—which are challenging to deposit. Here we show that single-crystal strontium titanate—a high- κ perovskite oxide—can be integrated with two-dimensional semiconductors using van der Waals forces. Strontium titanate thin films are grown on a sacrificial layer, lifted off and then transferred onto molybdenum disulfide and tungsten diselenide to make n-type and p-type transistors, respectively. The molybdenum disulfide transistors exhibit an on/off current ratio of 10 8 at a supply voltage of 1 V and a minimum subthreshold swing of 66 mV dec −1 . We also show that the devices can be used to create low-power complementary metal–oxide–semiconductor inverter circuits.

How to report and benchmark emerging field-effect transistors

Abstract: Emerging low-dimensional nanomaterials have been studied for decades in device applications as field-effect transistors (FETs). However, properly reporting and comparing device performance has been challenging due to the involvement and interlinking of multiple device parameters. More importantly, the interdisciplinarity of this research community results in a lack of consistent reporting and benchmarking guidelines. Here we report a consensus among the authors regarding guidelines for reporting and benchmarking important FET parameters and performance metrics. We provide an example of this reporting and benchmarking process for a two-dimensional (2D) semiconductor FET. Our consensus will help promote an improved approach for assessing device performance in emerging FETs, thus aiding the field to progress more consistently and meaningfully.

A Highly Conducting Polymer for Self‐Healable, Printable, and Stretchable Organic Electrochemical Transistor Arrays and Near Hysteresis‐Free Soft Tactile Sensors

Abstract: A stretchable and self‐healable conductive material with high conductivity is critical to high‐performance wearable electronics and integrated devices for applications where large mechanical deformation is involved. While there has been great progress in developing stretchable and self‐healable conducting materials, it remains challenging to concurrently maintain and recover such functionalities before and after healing. Here, a highly stretchable and autonomic self‐healable conducting film consisting of a conducting polymer (poly(3,4‐ethylenedioxythiophene):poly(styrenesulfonate), PEDOT:PSS) and a soft‐polymer (poly(2‐acrylamido‐2‐methyl‐1‐propanesulfonic acid), PAAMPSA) is reported. The optimal film exhibits outstanding stretchability as high as 630% and high electrical conductivity of 320 S cm−1, while possessing the ability to repair both mechanical and electrical breakdowns when undergoing severe damage at ambient conditions. This polymer composite film is further utilized in a tactile sensor, which exhibits good pressure sensitivity of 164.5 kPa−1, near hysteresis‐free, an ultrafast response time of 19 ms, and excellent endurance over 1500 consecutive presses. Additionally, an integrated 5 × 4 stretchable and self‐healable organic electrochemical transistor (OECT) array with great device performance is successfully demonstrated. The developed stretchable and autonomic self‐healable conducting film significantly increases the practicality and shelf life of wearable electronics, which in turn, reduces maintenance costs and build‐up of electronic waste.

A Fully Solution‐Printed Photosynaptic Transistor Array with Ultralow Energy Consumption for Artificial‐Vision Neural Networks

Abstract: Photosynaptic organic field‐effect transistors (OFETs) represent a viable pathway to develop bionic optoelectronics. However, the high operating voltage and current of traditional photosynaptic OFETs lead to huge energy consumption greater than that of the real biological synapses, hindering their further development in new‐generation visual prosthetics and artificial perception systems. Here, a fully solution‐printed photosynaptic OFET (FSP‐OFET) with substantial energy consumption reduction is reported, where a source Schottky barrier is introduced to regulate charge‐carrier injection, and which operates with a fundamentally different mechanism from traditional devices. The FSP‐OFET not only significantly lowers the working voltage and current but also provides extraordinary neuromorphic light‐perception capabilities. Consequently, the FSP‐OFET successfully emulates visual nervous responses to external light stimuli with ultralow energy consumption of 0.07–34 fJ per spike in short‐term plasticity and 0.41–19.87 fJ per spike in long‐term plasticity, both approaching the energy efficiency of biological synapses (1–100 fJ). Moreover, an artificial optic‐neural network made from an 8 × 8 FSP‐OFET array on a flexible substrate shows excellent image recognition and reinforcement abilities at a low energy cost. The designed FSP‐OFET offers an opportunity to realize photonic neuromorphic functionality with extremely low energy consumption dissipation.

A Reconfigurable Two‐WSe2‐Transistor Synaptic Cell for Reinforcement Learning

Abstract: Reward‐modulated spike‐timing‐dependent plasticity (R‐STDP) is a brain‐inspired reinforcement learning (RL) rule, exhibiting potential for decision‐making tasks and artificial general intelligence. However, the hardware implementation of the reward‐modulation process in R‐STDP usually requires complicated Si complementary metal–oxide–semiconductor (CMOS) circuit design that causes high power consumption and large footprint. Here, a design with two synaptic transistors (2T) connected in a parallel structure is experimentally demonstrated. The 2T unit based on WSe2 ferroelectric transistors exhibits reconfigurable polarity behavior, where one channel can be tuned as n‐type and the other as p‐type due to nonvolatile ferroelectric polarization. In this way, opposite synaptic weight update behaviors with multilevel (>6 bit) conductance states, ultralow nonlinearity (0.56/−1.23), and large Gmax/Gmin ratio of 30 are realized. By applying positive/negative reward to (anti‐)STDP component of 2T cell, R‐STDP learning rules are realized for training the spiking neural network and demonstrated to solve the classical cart–pole problem, exhibiting a way for realizing low‐power (32 pJ per forward process) and highly area‐efficient (100 µm2) hardware chip for reinforcement learning.

Light‐Stimulated Synaptic Transistor with High PPF Feature for Artificial Visual Perception System Application

Abstract: Optoelectronic synaptic devices, which combine the functions of photosensitivity and information processing, are essential for the development of artificial visual perception systems. Nevertheless, improving the paired pulse facilitation (PPF) index of optoelectronic synaptic devices, which is an urgent problem in the construction of high‐precision artificial visual perception systems, has received less attention so far. Herein, a light‐stimulated synaptic transistor (LSST) device with an ultra‐high PPF index (≈196%) is presented by introducing an ultra‐thin carrier regulator layer hexagonal boron nitride (h‐BN) into a classic graphene‐based hybrid transistor frame (graphene/CsPbBr3 quantum dots). Crucially, analysis of the rate‐limiting effect of h‐BN on photogenerated carriers reveals the mechanism behind the LSST ultra‐high PPF index. Furthermore, a two‐layer artificial neural network connected by LSST devices demonstrate ≈91.5% recognition accuracy of handwritten digits. This work provides an effective method for constructing artificial visual perception systems using a hybrid transistor frame in the future.

MXene based saturation organic vertical photoelectric transistors with low subthreshold swing

Abstract: Vertical transistors have attracted enormous attention in the next-generation electronic devices due to their high working frequency, low operation voltage and large current density, while a major scientific and technological challenge for high performance vertical transistor is to find suitable source electrode. Herein, an MXene material, Ti3C2Tx, is introduced as source electrode of organic vertical transistors. The porous MXene films take the advantage of both partially shielding effect of graphene and the direct modulation of the Schottky barrier at the mesh electrode, which significantly enhances the ability of gate modulation and reduces the subthreshold swing to 73 mV/dec. More importantly, the saturation of output current which is essential for all transistor-based applications but remains a great challenge for vertical transistors, is easily achieved in our device due to the ultra-thin thickness and native oxidation of MXene, as verified by finite-element simulations. Finally, our device also possesses great potential for being used as wide-spectrum photodetector with fast response speed without complex material and structure design. This work demonstrates that MXene as source electrode offers plenty of opportunities for high performance vertical transistors and photoelectric devices.

4.4 kV β-Ga2O3 MESFETs with power figure of merit exceeding 100 MW cm−2

Abstract: β-Ga2O3 metal–semiconductor field-effect transistors are realized with superior reverse breakdown voltages (V BR) and ON currents (I DMAX). A sandwiched SiN x dielectric field plate design is utilized that prevents etching-related damage in the active region and a deep mesa-etching was used to reduce reverse leakage. The device with L GD = 34.5 μm exhibits an I DMAX of 56 mA mm−1, a high I ON/I OFF ratio >108 and a very low reverse leakage until catastrophic breakdown at ∼4.4 kV. A power figure of merit (PFOM) of 132 MW cm−2 was calculated for a V BR of ∼4.4 kV. The reported results are the first >4 kV class Ga2O3 transistors to surpass the theoretical unipolar FOM of silicon.

Artificial Vision Adaption Mimicked by an Optoelectrical In2O3 Transistor Array.

Abstract: Simulation of biological visual perception has gained considerable attention. In this paper, an optoelectrical In2O3 transistor array with a negative photoconductivity behavior is designed using a side-gate structure and a screen-printed ion-gel as the gate insulator. This paper is the first to observe a negative photoconductivity in electrolyte-gated oxide devices. Furthermore, an artificial visual perception system capable of self-adapting to environmental lightness is mimicked using the proposed device array. The transistor device array shows a self-adaptive behavior of light under different levels of light intensity, successfully demonstrating the visual adaption with an adjustable threshold range to the external environment. This study provides a new way to create an environmentally adaptive artificial visual perception system and has far-reaching significance for the future of neuromorphic electronics.

High-performance hysteresis-free perovskite transistors through anion engineering

Abstract: Abstract Despite the impressive development of metal halide perovskites in diverse optoelectronics, progress on high-performance transistors employing state-of-the-art perovskite channels has been limited due to ion migration and large organic spacer isolation. Herein, we report high-performance hysteresis-free p-channel perovskite thin-film transistors (TFTs) based on methylammonium tin iodide (MASnI 3 ) and rationalise the effects of halide (I/Br/Cl) anion engineering on film quality improvement and tin/iodine vacancy suppression, realising high hole mobilities of 20 cm 2 V −1 s −1 , current on/off ratios exceeding 10 7 , and threshold voltages of 0 V along with high operational stabilities and reproducibilities. We reveal ion migration has a negligible contribution to the hysteresis of Sn-based perovskite TFTs; instead, minority carrier trapping is the primary cause. Finally, we integrate the perovskite TFTs with commercialised n-channel indium gallium zinc oxide TFTs on a single chip to construct high-gain complementary inverters, facilitating the development of halide perovskite semiconductors for printable electronics and circuits.

Dual-Ferroelectric-Coupling-Engineered Two-Dimensional Transistors for Multifunctional In-Memory Computing.

Abstract: In-memory computing featuring a radical departure from the von Neumann architecture is promising to substantially reduce the energy and time consumption for data-intensive computation. With the increasing challenges facing silicon complementary metal-oxide-semiconductor (CMOS) technology, developing in-memory computing hardware would require a different platform to deliver significantly enhanced functionalities at the material and device level. Here, we explore a dual-gate two-dimensional ferroelectric field-effect transistor (2D FeFET) as a basic device to form both nonvolatile logic gates and artificial synapses, addressing in-memory computing simultaneously in digital and analog spaces. Through diversifying the electrostatic behaviors in 2D transistors with the dual-ferroelectric-coupling effect, rich logic functionalities including linear (AND, OR) and nonlinear (XNOR) gates were obtained in unipolar (MoS2) and ambipolar (MoTe2) FeFETs. Combining both types of 2D FeFETs in a heterogeneous platform, an important computation circuit, i.e., a half-adder, was successfully constructed with an area-efficient two-transistor structure. Furthermore, with the same device structure, several key synaptic functions are shown at the device level, and an artificial neural network is simulated at the system level, manifesting its potential for neuromorphic computing. These findings highlight the prospects of dual-gate 2D FeFETs for the development of multifunctional in-memory computing hardware capable of both digital and analog computation.

Large-Area Interfaces for Single-Molecule Label-free Bioelectronic Detection.

Abstract: Bioelectronic transducing surfaces that are nanometric in size have been the main route to detect single molecules. Though enabling the study of rarer events, such methodologies are not suited to assay at concentrations below the nanomolar level. Bioelectronic field-effect-transistors with a wide (μm2-mm2) transducing interface are also assumed to be not suited, because the molecule to be detected is orders of magnitude smaller than the transducing surface. Indeed, it is like seeing changes on the surface of a one-kilometer-wide pond when a droplet of water falls on it. However, it is a fact that a number of large-area transistors have been shown to detect at a limit of detection lower than femtomolar; they are also fast and hence innately suitable for point-of-care applications. This review critically discusses key elements, such as sensing materials, FET-structures, and target molecules that can be selectively assayed. The amplification effects enabling extremely sensitive large-area bioelectronic sensing are also addressed.

A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins

Abstract: This paper explores a low standby power 10T (LP10T) SRAM cell with high read stability and write-ability (RSNM/WSNM/WM). The proposed LP10T SRAM cell uses a strong cross-coupled structure consisting standard inverter with a stacked transistor and Schmitt-trigger inverter with a double-length pull-up transistor. This along with the read path separated from true internal storage nodes eliminates the read-disturbance. Furthermore, it performs its write operation in pseudo differential form through write bitline and control signal with a write-assist technique. To estimate the proposed LP10T SRAM cell’s performance, it is compared with some state-of-the-art SRAM cells using HSPICE in 16-nm CMOS predictive technology model at 0.7 V supply voltage under harsh manufacturing process, voltage, and temperature variations. The proposed SRAM cell offers 4.65X/1.57X/1.46X improvement in RSNM/WSNM/WM and 4.40X/1.69X narrower spread in RSNM/WM compared to the conventional 6T SRAM cell. Furthermore, it shows 1.26X/1.08X/1.01X higher RSNM/WSNM/WM and 1.71X/1.25X tighter/wider spread in RSNM/WM compared to the best studied SRAM cells. The proposed SRAM cell indicates 74.48%/1.41% higher/lower read/write delay compared to the 6T SRAM cell. Moreover, it exhibits the third-(second-) best read (write) dynamic power, consuming 29.69% (26.87%) lower than the 6T SRAM cell. The leakage power is minimized by the proposed design, which is 37.35% and 12.08% lower than that of the 6T and best studied cells, respectively. Nonetheless, the proposed LP10T SRAM cell occupies 1.313X higher area compared to the 6T SRAM cell.

Fermi‐Level Pinning‐Free WSe2 Transistors via 2D Van der Waals Metal Contacts and Their Circuits

Abstract: Precise control over the polarity of transistors is a key necessity for the construction of complementary metal–oxide–semiconductor circuits. However, the polarity control of 2D transistors remains a challenge because of the lack of a high‐work‐function electrode that completely eliminates Fermi‐level pinning at metal–semiconductor interfaces. Here, a creation of clean van der Waals contacts is demonstrated, wherein a metallic 2D material, chlorine‐doped SnSe2 (Cl–SnSe2), is used as the high‐work‐function contact, providing an interface that is free of defects and Fermi‐level pinning. Such clean contacts made from Cl–SnSe2 can pose nearly ideal Schottky barrier heights, following the Schottky–Mott limit and thus permitting polarity‐controllable transistors. With the integration of Cl–SnSe2 as contacts, WSe2 transistors exhibit pronounced p‐type characteristics, which are distinctly different from those of the devices with evaporated metal contacts, where n‐type transport is observed. Finally, this ability to control the polarity enables the fabrication of functional logic gates and circuits, including inverter, NAND, and NOR.