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Transistor

About: Transistor is a research topic. Over the lifetime, 138090 publications have been published within this topic receiving 1455233 citations.


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Journal ArticleDOI
TL;DR: In this paper, a charge-based model of the intrinsic part of the MOS transistor is presented, which is based on the forward and reverse charges q/sub f/ defined as the mobile charge densities, evaluated at the source and at the drain.
Abstract: This paper presents an overview of MOS transistor modeling for RF integrated circuit design. It starts with the description of a physical equivalent circuit that can easily be implemented as a SPICE subcircuit. The MOS transistor is divided into an intrinsic part, representing mainly the active part of the device, and an extrinsic part responsible for most of the parasitic elements. A complete charge-based model of the intrinsic part is presented. The main advantage of this new charge-based model is to provide a simple and coherent description of the DC, AC, nonquasi-static (NQS), and noise behavior of the intrinsic MOS that is valid in all regions of operation. It is based on the forward and reverse charges q/sub f/ and q/sub r/ defined as the mobile charge densities, evaluated at the source and at the drain. This intrinsic model also includes a new simplified NQS model that uses a bias and frequency normalization allowing one to describe the high-order frequency behavior with only two simple functions. The extrinsic model includes all the terminal access series resistances, and particularly the gate resistance, the overlap, and junction capacitances as well as a substrate network. The latter is required to account for the signal coupling occurring at RF from the drain to the source and the bulk, through the junction capacitances. The noise model is then presented, including the effect of the substrate resistances on the RF noise parameters. All the aspects of the model are validated for a 0.25-/spl mu/m CMOS process.

194 citations

Patent
28 Sep 2018
TL;DR: In this article, a display panel comprises a plurality of light-emitting units, each light emitting unit comprises a light emitting device and a corresponding pixel circuit, and each pixel circuit is connected to the first power line, the second power line and the initialization signal line.
Abstract: The embodiment of the invention discloses a display panel and a display device. The display panel comprises a plurality of light-emitting units, each light-emitting unit comprises a light-emitting device and a corresponding pixel circuit, and the display panel comprises a first power line, a second power line and an initialization signal line; each pixel circuit is connected to the first power line, the second power line and the initialization signal line; each pixel circuit comprises a driving transistor, and the driving transistor and the light-emitting device are sequentially connected between the first power line and the second power line; in the screen-off display mode, the voltage transmitted to the first pole of the driving transistor in the pixel circuit by the first power line isequal to the absolute value of the voltage on the initialization signal line, and the voltage transmitted to the second pole of the light emitting device corresponding to the pixel circuit by the second power line is greater than the voltage of the light emitting device in the non-screen-off display mode. According to the technical scheme, the power consumption of the screen-off display mode of the display device is reduced, so the standby time of the display device is prolonged, and the user experience is improved.

194 citations

Patent
05 Dec 1995
TL;DR: In this article, an imaging device is formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal dioxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate and a charge coupled device section formed on the substrate adjacent the photogated having a sensing node connected to the output transistor and at least one
Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

194 citations

Journal ArticleDOI
TL;DR: Integrated iono-electronic system are obtained by the outgrowth of neuronal networks on the surface of the silicon chip, by implementing electrical circuits in the chip and by two-way interfacing of the neuronal and the electronic components.
Abstract: The electrical interfacing of individual nerve cells and silicon microstructures is considered, as well as the assembly of elementary hybrid systems made of neuronal networks and semiconductor microelectronics. Without electrochemical processes, coupling of the electron-conducting semiconductor and the ion-conducting neurons relies on a close contact of cell membrane and oxidised silicon with a high resistance of the junction and a high conductance of the attached membrane. Neuronal excitation can be elicited and recorded from the chip by capacitive contacts and by field-effect transistors with an open gate. Integrated iono-electronic system are obtained by the outgrowth of neuronal networks on the surface of the silicon chip, by implementing electrical circuits in the chip and by two-way interfacing of the neuronal and the electronic components.

194 citations

Proceedings ArticleDOI
05 Dec 2005
TL;DR: Reference NANOLAB-CONF-2005-019View record in Web of Science Record created on 2007-05-16, modified on 2017-05/10 as discussed by the authors.
Abstract: Reference NANOLAB-CONF-2005-019View record in Web of Science Record created on 2007-05-16, modified on 2017-05-10

194 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20231,850
20224,013
20211,802
20203,677
20194,203
20184,241