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Transistor

About: Transistor is a research topic. Over the lifetime, 138090 publications have been published within this topic receiving 1455233 citations.


Papers
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Journal ArticleDOI
TL;DR: In this paper, the authors reported the characteristics of vertical GaN-based trench metal-oxide-semiconductor field effect transistors on a free-standing GaN substrate with a blocking voltage of 16 kV.
Abstract: This paper reports the characteristics of vertical GaN-based trench metal–oxide–semiconductor field-effect transistors on a free-standing GaN substrate with a blocking voltage of 16 kV The high blocking voltage was obtained by using field plate edge termination around the isolation mesa of the transistor To our knowledge, the blocking voltage is the highest ever reported for vertical GaN-based transistors on free-standing GaN substrates Normally off operation with a threshold voltage of 7 V is also demonstrated

164 citations

Journal ArticleDOI
TL;DR: In this paper, the response of diodes and transistors to ionizing radiation is derived from the continuity and diffusion equations and, in the case of the transistor, the charge control model.
Abstract: Mathematical models describing the response of diodes and transistors to ionizing radiation are derived from the continuity and diffusion equations and, in the case of the transistor, the charge control model. Solutions are obtained for both steady-state and transient radiation environments. In addition to being of use in understanding device behavior, these solutions also indicate those device parameters which must be optimized to reduce transient response and therefore provide criteria for the design and/or selection of devices with minimum response. A model is also presented which describes the nonlinear effect of collector multiplication upon the collector photocurrent of a transistor. This model is used as a basis for explaining and predicting the nonlinear relation between the peak photo-response and the radiation dose which has been observed in some devices.

164 citations

Patent
21 Dec 1995
TL;DR: In this paper, a novel transistor with a low resistance ultra shallow tip region (214) and its method of fabrication was presented, which has a source/drain extension or tip region comprising an ultra shallow region, which extends beneath the gate electrode and a raised region.
Abstract: A novel transistor (200) with a low resistance ultra shallow tip region (214) and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip region (210) comprising an ultra shallow region (214) which extends beneath the gate electrode and a raised region (216).

164 citations

Patent
01 Jul 2003
TL;DR: In this paper, a method of fabricating an ultra shallow junction of a field effect transistor is described, which includes the steps of etching a substrate near a gate structure to define a source region and a drain region of the transistor, forming a spacer/protective film having poor step coverage to protect frontal surfaces of the source and drain regions, laterally etching sidewalls of the regions beneath a gate dielectric, and removing the protective film.
Abstract: A method of fabricating an ultra shallow junction of a field effect transistor is provided. The method includes the steps of etching a substrate near a gate structure to define a source region and a drain region of the transistor, forming a spacer/protective film having poor step coverage to protect frontal surfaces of the source and drain regions, laterally etching sidewalls of the regions beneath a gate dielectric to define a channel region, and removing the protective film.

163 citations

Patent
20 May 2002
TL;DR: In this article, a structural and method for flash memory with ultra-thin vertical body transistors is presented, which includes an array of memory cells including floating gate transistors, and each floating gate transistor includes a pillar extending outwardly from a semiconductor substrate.
Abstract: Structures and method for Flash memory with ultra thin vertical body transistors are provided. The Flash memory includes an array of memory cells including floating gate transistors. Each floating gate transistor includes a pillar extending outwardly from a semiconductor substrate. The pillar includes a single crystalline first contact layer and a second contact layer vertically separated by an oxide layer. A single crystalline vertical transistor is formed along side of the pillar. The single crystalline vertical transistor includes an ultra thin single crystalline vertical body region which separates an ultra thin single crystalline vertical first source/drain region and an ultra thin single crystalline vertical second source/drain region. A floating gate opposes the ultra thin single crystalline vertical body region, and a control gate separated from the floating gate by an insulator layer.

163 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20231,850
20224,013
20211,802
20203,677
20194,203
20184,241