Transistor

About: Transistor is a research topic. Over the lifetime, 138090 publications have been published within this topic receiving 1455233 citations.

Accurate small-signal modeling of HFET's for millimeter-wave applications

Abstract: In this paper we discuss the small-signal modeling of HFET's at millimeter-wave frequencies. A new and iterative method is used to extract the parasitic components. This method allows calculation of a /spl pi/-network to model the heterojunction field-effect transistor (HFET) pads, thus extending the validity of the model to higher frequencies. Formulas are derived to translate this /spl pi/-network into a transmission line. A new and general cold field-effect transistor (FET) equivalent circuit, including a Schottky series resistance, is used to extract the parasitic resistances and inductances. Finally, a new and compact set of analytical equations for calculation of the intrinsic parameters is presented. The real part of Y/sub 12/ is accounted for in these equations and its modeling is discussed. The accounting of Re(Y/sub 12/) improves the S-parameter modeling. Model parameters are extracted for an InAlAs/InGaAs/InP HFET from measured S-parameters up to 50 GHz, and the validity of the model is evaluated by comparison with measured data at 75-110 GHz.

Nanoscale organic transistors that use source/drain electrodes supported by high resolution rubber stamps

Abstract: Soft contact lamination and metal-coated elastomeric stamps provide the basis for a convenient and noninvasive approach to establishing high resolution electrical contacts to electroactive organic materials. The features of relief on the stamps define, with nanometer resolution, the geometry and separation of electrically independent electrodes that are formed by uniform, blanket evaporation of a thin metal film onto the stamp. Placing this coated stamp on a flat substrate leads to “wetting” and atomic scale contact that establishes efficient electrical connections. When the substrate supports an organic semiconductor, a gate dielectric and a gate, this soft lamination process yields high performance top contact transistors with source/drain electrodes on the stamp. We use this approach to investigate charge transport through pentacene in transistor structures with channel lengths that span more than three decades: from 250 μm to ∼150 nm. We also report some preliminary measurements on charge transport through organic monolayers using the same laminated transistor structures.

Modeling line edge roughness effects in sub 100 nanometer gate length devices

Abstract: A fast method to estimate the effects of line edge roughness is proposed. This method is based upon the use of multiple 2D device "slices" sandwiched together to form a MOS transistor of a given width. This method was verified to yield an accurate representation of rough edge MOS transistors through comparisons to full three dimensional simulations. A subsequent statistical study shows how the variation in line edge roughness affects the values and variances of several key device parameters.

Method of making a high-voltage transistor with multiple lateral conduction layers

Abstract: A method for making a high voltage insulated gate field-effect transistor having an insulated gate field-effect device structure with a source and a drain comprises the steps of forming the drain (19) with an extended well region (17) having one or more buried layers (18) of opposite conduction type sandwiched therein. The one or more buried layers (18) create an associated plurality of parallel JFET conduction channels (25) in the extended portion of the well region. A minimal number of processing steps are required to form the parallel JFET conduction channels which provide the HVFET with a low on-state resistance.

Graphene-based transistor

Abstract: A graphene layer is formed on a surface of a silicon carbide substrate. A dummy gate structure is formed over the fin, in the trench, or on a portion of the planar graphene layer to implant dopants into source and drain regions. The dummy gate structure is thereafter removed to provide an opening over the channel of the transistor. Threshold voltage adjustment implantation may be performed to form a threshold voltage implant region directly beneath the channel, which comprises the graphene layer. A gate dielectric is deposited over a channel portion of the graphene layer. After an optional spacer formation, a gate conductor is formed by deposition and planarization. The resulting graphene-based field effect transistor has a high carrier mobility due to the graphene layer in the channel, low contact resistance to the source and drain region, and optimized threshold voltage and leakage due to the threshold voltage implant region.