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Transistor

About: Transistor is a research topic. Over the lifetime, 138090 publications have been published within this topic receiving 1455233 citations.


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Journal ArticleDOI
07 Apr 2014-ACS Nano
TL;DR: In this paper, a GaTe nanosheet FET with on/off ratio of ∼105, off-state current of ∼10−12 A, and negligible gate hysteresis is successfully demonstrated.
Abstract: We report a high-performance field-effect transistor (FET) and phototransistor based on back-gated multilayer GaTe nanosheets. Through both electrical transport measurements at variable temperatures and first-principles calculations, we find Ga ion vacancy is the critical factor that causes high off-state current, low on/off ratio, and large hysteresis of GaTe FET at room temperature. By suppressing thermally activated Ga vacancy defects at liquid nitrogen temperature, a GaTe nanosheet FET with on/off ratio of ∼105, off-state current of ∼10–12 A, and negligible gate hysteresis is successfully demonstrated. Furthermore, a GaTe phototransistor with high photogain above 2000 and high responsivity over 800 AW–1 is achieved, as well. Our findings are of scientific importance to understand the physical nature of intrinsic GaTe transistor performance degradation and also technical significance to unlock the hurdle for practical applications of GaTe transistors in the future.

157 citations

Patent
06 Nov 2001
TL;DR: In this article, complementary metal oxide transistors are formed on a silicon substrate so that current flows in the channels of the transistors were parallel to the direction, and longitudinal tensile stress is applied to the channels.
Abstract: Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the direction. Additionally, longitudinal tensile stress is applied to the channels.

157 citations

Journal ArticleDOI
TL;DR: In this article, an equivalent circuit model of a three-terminal switching device describing the perturbations in the average terminal voltages and current is obtained, and the analysis of pulsewidth modulated and quasiresonant converters becomes analogous to transistor circuit analysis where the transistor is replaced by its equivalent circuit.
Abstract: The nonlinear switching mechanism in pulsewidth-modulated (PWM) and quasi-resonant converters is that of a three-terminal switching device which consists only of an active and a passive switch. An equivalent circuit model of this switching device describing the perturbations in the average terminal voltages and current is obtained. Through the use of this circuit model the analysis of pulsewidth modulated and quasiresonant converters becomes analogous to transistor circuit analysis where the transistor is replaced by its equivalent circuit model. The conversion ratio characteristics of various resonant converters and their relationship to a single function, called the quasi-resonant function, is easily obtained using the circuit model for the three-terminal switching device. The small-signal response of quasi-resonant converters to perturbations in the switching frequency and input voltage is determined by replacing the three-terminal switching device by its small-signal equivalent circuit model. >

157 citations

Patent
29 Jun 2004
TL;DR: A memory cell for a memory array in a folded bit line configuration was proposed in this paper, where an access transistor formed in a pillar of single crystal semiconductor material was used for memory access.
Abstract: A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal semiconductor material. The access transistor has first and second source/drain regions and a body region that are vertically aligned. The access transistor further includes a gate coupled to a wordline disposed adjacent to the body region. The memory cell also includes a passing wordline that is separated from the gate by an insulator for coupling to other memory cells adjacent to the memory cell. The memory cell also includes a trench capacitor. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor. The trench capacitor also includes a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide.

157 citations

Journal ArticleDOI
TL;DR: The proposed architecture offers several advantages including better immunity to short channel effects, reduction of device-to-device variability, and nanometer gate length patterning without the need for high-resolution lithography, important in the large-scale manufacture of low-power transistors and memory devices.
Abstract: Nanowire-based field-effect transistors are among the most promising means of overcoming the limits of today's planar silicon electronic devices, in part because of their suitability for gate-all-around architectures, which provide perfect electrostatic control and facilitate further reductions in “ultimate” transistor size while maintaining low leakage currents. However, an architecture combining a scalable and reproducible structure with good electrical performance has yet to be demonstrated. Here, we report a high performance field-effect transistor implemented on massively parallel dense vertical nanowire arrays with silicided source/drain contacts and scaled metallic gate length fabricated using a simple process. The proposed architecture offers several advantages including better immunity to short channel effects, reduction of device-to-device variability, and nanometer gate length patterning without the need for high-resolution lithography. These benefits are important in the large-scale manufacture of low-power transistors and memory devices.

157 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20231,850
20224,013
20211,802
20203,677
20194,203
20184,241