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Transistor
About: Transistor is a research topic. Over the lifetime, 138090 publications have been published within this topic receiving 1455233 citations.
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TL;DR: In this paper, a characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data and the physical causes of mismatch are discussed in detail for both p- and n-channel devices.
Abstract: A characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data. The physical causes of mismatch are discussed in detail for both p- and n-channel devices. Statistical methods are used to develop analytical models that relate the mismatch to the device dimensions. It is shown that these models are valid for small-geometry devices only. Extensive experimental data from a 3-/spl mu/m CMOS process are used to verify the models. The application of the transistor matching studies to the design of a high-performance digital-to-analog converter (DAC) is discussed. A circuit design methodology is presented that highlights the close interaction between the circuit yield and the matching accuracy of devices. It has been possible to achieve a circuit yield of greater than 97% as a result of the knowledge generated regarding the matching behavior of transistors and due to the systematic design approach.
707 citations
TL;DR: Surrounding-gate transistors using core–multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability.
Abstract: The fabrication of transistors using vertical, six-sided core–multishell indium gallium arsenide nanowires with an all-surrounding gate on a silicon substrate combines the advantages of a three-dimensional gate architecture with the high electron mobility of the III–V nanowires, drastically enhancing the on-state current and transconductance. In the continuing drive to improve and miniaturize transistors, the microelectronics industry has recently adopted three-dimensional electronic gate structures. Another way of improving transistors is to use semiconductor materials with higher electron mobility than silicon, although this presents significant fabrication challenges. Katsuhiro Tomioka et al. combine the two approaches; they grow, with high precision, vertical, six-sided core–multishell indium gallium arsenide nanowires with an all-surrounding gate on a silicon substrate. The resulting devices demonstrate superior transistor performance with excellent on/off switching behaviour and fast operation. Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years’ time1,2,3,4. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III–V materials, specifically InGaAs, are being explored as alternative fast channels on silicon5,6,7,8,9 because of their high electron mobility and high-quality interface with gate dielectrics10. The idea of surrounding-gate transistors11, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated12,13 because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core–multishell nanowires as channels. Surrounding-gate transistors using core–multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.
704 citations
TL;DR: The fabrication of high-performance thin-film transistors and integrated circuits on flexible and transparent substrates using floating-catalyst chemical vapour deposition followed by a simple gas-phase filtration and transfer process has a well-controlled density and a unique morphology.
Abstract: Carbon nanotube thin-film transistors are expected to enable the fabrication of high-performance, flexible and transparent devices using relatively simple techniques. However, as-grown nanotube networks usually contain both metallic and semiconducting nanotubes, which leads to a trade-off between charge-carrier mobility (which increases with greater metallic tube content) and on/off ratio (which decreases). Many approaches to separating metallic nanotubes from semiconducting nanotubes have been investigated, but most lead to contamination and shortening of the nanotubes, thus reducing performance. Here, we report the fabrication of high-performance thin-film transistors and integrated circuits on flexible and transparent substrates using floating-catalyst chemical vapour deposition followed by a simple gas-phase filtration and transfer process. The resulting nanotube network has a well-controlled density and a unique morphology, consisting of long (~10 µm) nanotubes connected by low-resistance Y-shaped junctions. The transistors simultaneously demonstrate a mobility of 35 cm(2) V(-1) s(-1) and an on/off ratio of 6 × 10(6). We also demonstrate flexible integrated circuits, including a 21-stage ring oscillator and master-slave delay flip-flops that are capable of sequential logic. Our fabrication procedure should prove to be scalable, for example, by using high-throughput printing techniques.
695 citations
TL;DR: It is demonstrated that the density of magnons flowing from the transistor’s source to its drain can be decreased three orders of magnitude by the injection of Magnon–magnon interactions into the transistor's gate.
Abstract: An attractive direction in next-generation information processing is the development of systems employing particles or quasiparticles other than electrons--ideally with low dissipation--as information carriers. One such candidate is the magnon: the quasiparticle associated with the eigen-excitations of magnetic materials known as spin waves. The realization of single-chip all-magnon information systems demands the development of circuits in which magnon currents can be manipulated by magnons themselves. Using a magnonic crystal--an artificial magnetic material--to enhance nonlinear magnon-magnon interactions, we have succeeded in the realization of magnon-by-magnon control, and the development of a magnon transistor. We present a proof of concept three-terminal device fabricated from an electrically insulating magnetic material. We demonstrate that the density of magnons flowing from the transistor's source to its drain can be decreased three orders of magnitude by the injection of magnons into the transistor's gate.
694 citations
Patent•
15 May 2000
TL;DR: In this article, a nonvolatile semiconductor memory device is provided to reduce current consumed at a sense amplifier when amplifying a small signal induced to a bit line by that a cell capacitor and bit line capacitor hold an electric charge in common by precharging the bit line in a semiconductor device using a ferroelectric capacitor to a half of the level of a power voltage and increase amplifying function by decreasing the coupling effect by a gate capacitance.
Abstract: PURPOSE: A nonvolatile semiconductor memory device is provided to reduce current consumed at a sense amplifier when amplifying a small signal induced to a bit line by that a cell capacitor and a bit line capacitor hold an electric charge in common by precharging a bit line in a semiconductor device using a ferroelectric capacitor to a half of the level of a power voltage and increase amplifying function by decreasing the coupling effect by a gate capacitance of a sense amplifier CONSTITUTION: The memory device includes a sense amplifier(S1), a memory cell(M1), a plate driver(F1), a reference voltage generating portion(R1), a half power voltage generating device and a precharging circuit(P1) The sense amplifier senses a difference of a voltage between a bit line(BL) and a bit line bar(BLB) and amplifies the difference The memory cell, in which a switching transistor and a ferroelectric capacitor are in series connected, stores a data The plate driver is connected to the ferroelectric capacitor and drives a plate line applying a voltage to the ferroelectric capacitor The reference voltage generating portion generates a reference voltage necessary for sensing and amplifying The half power voltage generating device, to which a level of a power voltage is inputted, outputs a level of a half power voltage The precharging circuit supplies the half power voltage inputted from the half power voltage generating device to the bit line and bit line bar in response to a signal for controlling a bit line
693 citations