Topic
Transistor
About: Transistor is a research topic. Over the lifetime, 138090 publications have been published within this topic receiving 1455233 citations.
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24 Oct 2006
TL;DR: The EKV Model of the MOS Transistor is used as a model for low-voltage circuit design and analog Circuits in Weak Inversion are studied.
Abstract: Origins of Weak Inversion (or Sub-threshold) Circuit Design.- Survey of Low-voltage Implementations.- Minimizing Energy Consumption.- EKV Model of the MOS Transistor.- Digital Logic.- Sub-threshold Memories.- Analog Circuits in Weak Inversion.- System Examples.
543 citations
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TL;DR: In this paper, an electric double layer transistor (EDLT) was found to exhibit very high transconductance and an ultrahigh carrier density in a fast, reversible, and reproducible manner.
Abstract: Very recently, electric-field-induced superconductivity in an insulator was realized by tuning charge carrier to a high density level (1 × 1014 cm−2). To increase the maximum attainable carrier density for electrostatic tuning of electronic states in semiconductor field-effect transistors is a hot issue but a big challenge. Here, ultrahigh density carrier accumulation is reported, in particular at low temperature, in a ZnO field-effect transistor gated by electric double layers of ionic liquid (IL). This transistor, called an electric double layer transistor (EDLT), is found to exhibit very high transconductance and an ultrahigh carrier density in a fast, reversible, and reproducible manner. The room temperature capacitance of EDLTs is found to be as large as 34 µF cm−2, deduced from Hall-effect measurements, and is mainly responsible for the carrier density modulation in a very wide range. Importantly, the IL dielectric, with a supercooling property, is found to have charge-accumulation capability even at low temperatures, reaching an ultrahigh carrier density of 8×1014 cm−2 at 220 K and maintaining a density of 5.5×1014 cm−2 at 1.8 K. This high carrier density of EDLTs is of great importance not only in practical device applications but also in fundamental research; for example, in the search for novel electronic phenomena, such as superconductivity, in oxide systems.
543 citations
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01 Jan 2003TL;DR: A new transistor sizing algorithm, which couples synchronous timing analysis with convex optimization techniques, is presented, which shows that any point found to be locally optimal is certain to be globally optimal.
Abstract: A new transistor sizing algorithm, which couples synchronous timing analysis with convex optimization techniques, is presented. Let A be the sum of transistor sizes, T the longest delay through the circuit, and K a positive constant. Using a distributed RC model, each of the following three programs is shown to be convex: 1) Minimize A subject to T < K. 2) Minimize T subject to A < K. 3) Minimize AT K . The convex equations describing T are a particular class of functions called posynomials. Convex programs have many pleasant properties, and chief among these is the fact that any point found to be locally optimal is certain to be globally optimal TILOS (Timed Logic Synthesizer) is a program that sizes transistors in CMOS circuits. Preliminary results of TILOS’s transistor sizing algorithm are presented.
542 citations
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TL;DR: In this paper, the integration of all-polymer field effect transistors in fully functional integrated circuits with operating frequencies of several kHz was demonstrated by a 15 bit code generator circuit using several hundreds of devices.
Abstract: In this letter, we demonstrate the integration of all-polymer field-effect transistors in fully functional integrated circuits with operating frequencies of several kHz. One of the key items is an approach to incorporate low-Ohmic vertical interconnects compatible with an all-polymer approach. Inverters, NAND gates, and ring oscillators with transistor channel lengths down to 1 μm have been constructed. Inverters show voltage amplification at moderate biases and pentacene seven-stage ring oscillators show switching frequencies of a few kHz. The potential to realize large integrated circuits is demonstrated by a 15 bit code generator circuit using several hundreds of devices. The proposed concept was evaluated for three solution-processable organic semiconductors.
538 citations
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TL;DR: In this paper, the physics of charge control, source velocity saturation due to thermal injection, and scattering in ultrasmall MOSFETs are examined. And the results show that the essential physics of nanoscale MOSFLETs can be understood in terms of a conceptually simple scattering model.
Abstract: The device physics of nanoscale MOSFETs is explored by numerical simulations of a model transistor. The physics of charge control, source velocity saturation due to thermal injection, and scattering in ultrasmall devices are examined. The results show that the essential physics of nanoscale MOSFETs can be understood in terms of a conceptually simple scattering model.
536 citations