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Transistor

About: Transistor is a research topic. Over the lifetime, 138090 publications have been published within this topic receiving 1455233 citations.


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Journal ArticleDOI
Joerg Appenzeller1, Yu-Ming Lin1, Joachim Knoch, Zhihong Chen1, Phaedon Avouris1 
TL;DR: In this article, three different carbon nanotube (CN) field effect transistor (CNFET) designs are compared by simulation and experiment, and the authors explore the possibility of using CNs as gate-controlled tunneling devices.
Abstract: Three different carbon nanotube (CN) field-effect transistor (CNFET) designs are compared by simulation and experiment. While a C-CNFET with a doping profile similar to a "conventional" (referred to as C-CNFET in the following) p-or n-MOSFET in principle exhibits superior device characteristics when compared with a Schottky barrier CNFET, we find that aggressively scaled C-CNFET devices suffer from "charge pile-up" in the channel. This effect which is also known to occur in floating body silicon transistors deteriorates the C-CNFET off-state substantially and ultimately limits the achievable on/off-current ratio. In order to overcome this obstacle we explore the possibility of using CNs as gate-controlled tunneling devices (T-CNFETs). The T-CNFET benefits from a steep inverse subthreshold slope and a well controlled off-state while at the same time delivering high performance on-state characteristics. According to our simulation, the T-CNFET is the ideal transistor design for an ultrathin body three-terminal device like the CNFET.

320 citations

Journal ArticleDOI
TL;DR: In this article, a gate voltage modulation of the source-to-drain tunnel current is demonstrated for the 30 nm gate length device with a record subthreshold slop of 350 mV/decade and a cutoff frequency of 20 kHz.
Abstract: We made nanometer-scale (gate length of 30 nm) organic thin-film transistors using a self-assembled monolayer (2 nm thick) as a gate insulator. The fabrication steps combine electron-beam lithography and lift-off techniques for the deposition of both metal electrodes and organic semiconductors with a chemical approach (self-assembly of organic molecules) to fabricate the gate insulator. Good performances of these transistors (with a record subthreshold slop of 350 mV/decade and a cutoff frequency of 20 kHz) and low-voltage operation (<2 V) are demonstrated down to a gate length of 200 nm. A gate voltage modulation of the source-to-drain tunnel current is demonstrated for the 30 nm gate length device.

320 citations

Journal ArticleDOI
G.L. Patton1, Subramanian S. Iyer1, S. L. Delage1, Sandip Tiwari1, Johannes M. C. Stork1 
TL;DR: In this paper, the collector current of a 1000-AA base device containing 12% germanium was measured at room temperature, while a 1000 times increase was observed to 90 K. This was consistent with a bandgap shrinkage in the base of 50 meV.
Abstract: The devices were fabricated using molecular-beam epitaxy (MBE), low-temperature processing, and germanium concentrations of 0, 6%, and 12%. The transistors demonstrate current gain, and show the expected increase in collector current as a result of reduced bandgap due to Ge incorporation in the base. For a 1000-AA base device containing 12% Ge, a six-times increase in collector current was measured at room temperature, while a 1000-times increase was observed to 90 K. The temperature dependence of the collector current of the Si/sub 0.88/Ge/sub 0.12/ base transistor is consistent with a bandgap shrinkage in the base of 50 meV. For the homojunction transistors, base widths as thin as 800 AA were grown, corresponding to a neutral base width of no more than 400 AA. >

320 citations

Journal ArticleDOI
TL;DR: Devices available in digital oriented CMOS processes are reviewed, with emphasis on the various modes of operation of a standard transistor and their respective merits, and on additional specifications required to apply devices in analog circuits.
Abstract: Devices available in digital oriented CMOS processes are reviewed, with emphasis on the various modes of operation of a standard transistor and their respective merits, and on additional specifications required to apply devices in analog circuits. Some basic compatible analog circuit techniques and their related tradeoffs are then surveyed by means of typical examples. The noisy environment due to cohabitation on the chip with digital circuits is briefly evoked.

319 citations

Journal ArticleDOI
Shilei Dai1, Yiwei Zhao1, Yan Wang1, Junyao Zhang1, Lu Fang1, Shu Jin1, Yinlin Shao1, Jia Huang1 
TL;DR: A review of recent advances in transistor‐based artificial synapses is presented to give a guideline for future implementation of synaptic functions with transistors and the main challenges and research directions of transistor‐ based artificial synapse are presented.

318 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20231,850
20224,013
20211,802
20203,677
20194,203
20184,241