Transistor

About: Transistor is a research topic. Over the lifetime, 138090 publications have been published within this topic receiving 1455233 citations.

Ambipolar light-emitting organic field-effect transistor

Abstract: We demonstrate a light-emitting organic field-effect transistor (OFET) with pronounced ambipolar current characteristics. The ambipolar transport layer is a coevaporated thin film of α-quinquethiophene (α-5T) as hole-transport material and N,N′-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13) as electron-transport material. The light intensity is controlled by both the drain–source voltage VDS and the gate voltage VG. Moreover, the latter can be used to adjust the charge-carrier balance. The device structure serves as a model system for ambipolar light-emitting OFETs and demonstrates the general concept of adjusting electron and hole mobilities by coevaporation of two different organic semiconductors.

MOS transistor modeling for RF IC design

Abstract: This paper presents the basis of the modeling of the MOS transistor for circuit simulation at RF. A physical equivalent circuit that can easily be implemented as a Spice subcircuit is first derived. The subcircuit includes a substrate network that accounts for the signal coupling occurring at HF from the drain to the source and the bulk. It is shown that the latter mainly affects the output admittance Y22. The bias and geometry dependence of the subcircuit components, leading to a scalable model, are then discussed with emphasis on the substrate resistances. Analytical expressions of the Y parameters are established and compared to measurements made on a 0.25-/spl mu/m CMOS process. The Y parameters and transit frequency simulated with this scalable model versus frequency, geometry, and bias are in good agreement with measured data. The nonquasi-static effects and their practical implementation in the Spice subcircuit are then briefly discussed. Finally, a new thermal noise model is introduced. The parameters used to characterize the noise at HF are then presented and the scalable model is favorably compared to measurements made on the same devices used for the S-parameter measurement.

Ionic/electronic hybrid materials integrated in a synaptic transistor with signal processing and learning functions

Abstract: 2010 WILEY-VCH Verlag Gmb Signal processing, memory, and learning functions are established in the human brain by modifying ionic fluxes in neurons and synapses. Through a synapse, a potential spike signal in a presynaptic neuron can trigger an ionic excitatory postsynaptic current (EPSC) or inhibitory postsynaptic current (IPSC) that temporally lasts for 1–10ms in a postsynaptic neuron. This enables the postsynaptic neuron to collectively process the EPSC or IPSC through 10–10 synapses to establish spatial and temporal correlated functions. The synaptic transmission efficacy can be modified by temporally correlated preand post-synaptic spikes via spike-timing-dependent plasticity (STDP). For example, if a postsynaptic spike is triggered momentarily after a presynaptic spike by a few milliseconds, the synaptic efficacy will be increased, resulting in long-term potentiation (LTP), but if the temporal order is reversed, the synaptic efficacy will be decreased, resulting in long-term depression (LTD). The synaptic efficacy can also be modified with reversed polarities in STDP in different types of synapses. STDP is essential to modify synapses in a neural network for learning and memory functions of the brain. Electronic materials, devices, and circuits have been explored extensively to emulate synapses, but to date they have not been able to match the synaptic functions in the brain. Synaptic transistors with nonvolatile analog memory were fabricated by integrating a charge-storage or ferroelectric materials onto the gate structure of Si metal-oxide-semiconductor (MOS) transistors, but these devices cannot emulate the essential synaptic dynamic functions such as EPSC/IPSC or STDP. Electronic neuromorphic circuits have been designed and fabricated to supply EPSC/IPSC and STDP, but these nonlinear dynamic analog circuits require many transistors and several capacitors to emulate a single synapse. The large capacitor size, complex architecture, and energy consumption of these synaptic circuits limited the number of synapses that could be integrated onto a single chip to about 10–10. The lack of a small, cheap device with the essential synaptic dynamic properties for signal processing, learning, and memory prohibits the circuits from approaching the scale and functions of the human brain that contains 10 synapses. We have designed and fabricated a synaptic transistor based on ionic/electronic hybrid materials by integrating a layer of ionic conductor and a layer of ion-doped conjugated polymer, onto the gate of a Si-based transistor. In analogy to the synapse, a potential spike can trigger ionic fluxes with a temporal lapse of a few milliseconds in the polymer, which in turn spontaneously generates EPSC in the Si layer. Temporally correlated preand post-synaptic spikes can modify ions stored in the polymer, resulting in a nonvolatile strengthening or weakening of the device transmission efficacy with STDP. A single hybrid transistor can replace presently utilized complex and energyconsuming electronic circuits to emulate the synapse for spike signal processing, learning, and memory, which could provide a new pathway to construct neuromorphic circuits approaching the scale and functions of the brain. The synaptic transistor has a Si n-p-n source-channel-drain structure of a conventional MOS transistor, with the Si channel covered by a 3-nm-thick SiO2 insulating layer (Fig. 1a). A 70-nm-thick conjugated polymer layer of poly[2-methoxy-5(20-ethylhexyloxy)-p-phenylene vinylene] (MEH-PPV) and a 70-nm-thick ionic conductive layer of RbAg4I5 were sandwiched between the gate SiO2 insulator and an Al/Ti electrode. To emulate synaptic functions, presynaptic spikes were applied to the transistor gate, and postsynaptic currents, I, were measured from the source. Postsynaptic spikes were also applied to the source. A spike was composed of a 1ms-wide positive voltage pulse with an amplitude Vþ1⁄4 3–5V immediately followed by a 1 ms-wide negative voltage pulse with an amplitude V 1⁄4 3 to 5V (Fig. 1a, Inset). After the spike, the transistor was operated at its rest state under a subthreshold condition by setting the gate voltage Vg1⁄4 0 V. A drain voltage Vd1⁄4 0.1 V was applied continuously. When a presynaptic spike with amplitudes of Vþ/V 1⁄4 4V/ 5V was applied to the transistor gate, the typical I is

Reduced electric field in junctionless transistors

Abstract: The electric field perpendicular to the current flow is found to be significantly lower in junctionless transistors than in regular inversion-mode or accumulation-mode field-effect transistors. Since inversion channel mobility in metal-oxide-semionductor transistors is reduced by this electric field, the low field in junctionless transistor may give them an advantage in terms of current drive for nanometer-scale complementary metal-oxide semiconductor applications. This observation still applies when quantum confinement is present.

Bistable dmd addressing circuit and method

Abstract: Bidirectional operation of the bistable DMD is preferred over unidirectional operation because it eliminates contrast degradation caused by duty-factor effects and permits lower voltage operation. However, bidirectional addressing requires either two drain lines and two transistors per pixel or one drain line and three transistors per pixel. An addressing scheme for bidirectional operation is disclosed that requires only a single drain line and one transistor per pixel. For megapixel DMDs used for high-definition television applications, this addressing scheme dramatically lowers the transistor count, with expected improvements in chip yield and cost.