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Transistor

About: Transistor is a research topic. Over the lifetime, 138090 publications have been published within this topic receiving 1455233 citations.


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Patent
Nick Lindert1, Stephen M. Cea1
31 Mar 2004
TL;DR: In this paper, a tri-gate transistor with stained enhanced mobility and its method of fabrication is presented, where a gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and a gate electrode having a pair of laterally opposite sidewalls is formed around and around the gate dieslectric layers.
Abstract: A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a top surface on laterally opposite sidewalls. A semiconductor capping layer is formed on the top surface and on the sidewalls of the semiconductor body. A gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and is formed on the capping layer on the sidewalls of the semiconductor body. A gate electrode having a pair of laterally opposite sidewalls is formed on and around the gate dielectric layer. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

284 citations

Journal ArticleDOI
TL;DR: The ability to simulate temperature, dispersion, and soft-breakdown effects as well as a new /spl alpha/ dependence was added to the Chalmers nonlinear model for high electron mobility transistor (HEMT) and metal semiconductor field effect transistor (MESFET's) in this paper.
Abstract: The ability to simulate temperature, dispersion, and soft-breakdown effects as well as a new /spl alpha/ dependence was added to the Chalmers nonlinear model for high electron mobility transistor (HEMT's) and metal semiconductor field-effect transistor (MESFET's). DC, pulsed dc, low frequency (10 Hz-10 MHz), RF, and small signal S-parameter measurements (1-18 GHz) have been made on a large number of commercial HEMT and MESFET devices from different manufacturers in the temperature range 17-400 K in order to evaluate the validity of the model extensions.

284 citations

Proceedings Article
01 Jun 2006
TL;DR: Tunnel field effect transistors (TFETs) with record high I ON /I OFF ratio (≫106) for lowvoltage (0.5V) operation are achieved by using germanium in the source region to achieve a small tunnel bandgap.
Abstract: Tunnel field effect transistors (TFETs) with record high I ON /I OFF ratio (≫106) for low-voltage (0.5V) operation are achieved by using germanium in the source region to achieve a small tunnel bandgap. The measured data are well explained by the theoretical band-to-band tunneling current model. Using the calibrated analytical model, the energy-delay performance of TFET-based technology is compared against that of conventional CMOS technology, at the 65nm node. The TFET is projected to provide dramatic improvement in energy efficiency for performance in the range up to ∼0.5GHz.

283 citations

Journal ArticleDOI
TL;DR: In this paper, the integration of a 4μm thick sensor layer onto a flexible amorphous silicon thin-film transistor backplane gave an image sensor array with 35% external quantum efficiency and noise equivalent power of 30pW∕cm2 at reverse bias voltage of −4V.
Abstract: Thick organic bulk heterojunction photodiodes with low dark current 1V∕μm is sufficient to achieve >75% charge collection in films of poly[2-methoxy-5-(2-ethylhexyloxy)-1,4-phenylene-vinylene] and [6,6]-phenyl-C61-butyric acid methyl ester blends up to 4μm thick, and the rate of photocurrent decay is reduced at saturation fields. The integration of a 4μm thick sensor layer onto a flexible amorphous silicon thin-film transistor backplane gave an image sensor array with 35% external quantum efficiency and noise equivalent power of 30pW∕cm2 at reverse bias voltage of −4V.

283 citations

Journal ArticleDOI
03 Apr 2014-ACS Nano
TL;DR: In this work, the operation of n- and p-type field-effect transistors (FETs) on the same WSe2 flake is realized, and a complementary logic inverter is demonstrated.
Abstract: In this work, the operation of n- and p-type field-effect transistors (FETs) on the same WSe2 flake is realized,and a complementary logic inverter is demonstrated. The p-FET is fabricated by contacting WSe2 with a high work function metal, Pt, which facilities hole injection at the source contact. The n-FET is realized by utilizing selective surface charge transfer doping with potassium to form degenerately doped n+ contacts for electron injection. An ON/OFF current ratio of >104 is achieved for both n- and p-FETs with similar ON current densities. A dc voltage gain of >12 is measured for the complementary WSe2 inverter. This work presents an important advance toward realization of complementary logic devices based on layered chalcogenide semiconductors for electronic applications.

281 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20231,850
20224,013
20211,802
20203,677
20194,203
20184,241