Transistor

About: Transistor is a research topic. Over the lifetime, 138090 publications have been published within this topic receiving 1455233 citations.

σ-π molecular dielectric multilayers for low-voltage organic thin-film transistors

Abstract: Very thin (2.3-5.5 nm) self-assembled organic dielectric multilayers have been integrated into organic thin-film transistor structures to achieve sub-1-V operating characteristics. These new dielectrics are fabricated by means of layer-by-layer solution phase deposition of molecular silicon precursors, resulting in smooth, nanostructurally well defined, strongly adherent, thermally stable, virtually pinhole-free, organosiloxane thin films having exceptionally large electrical capacitances (up to ≈2,500 nF·cm-2), excellent insulating properties (leakage current densities as low as 10-9 A·cm-2), and single-layer dielectric constant (k)of ≈16. These 3D self-assembled multilayers enable organic thin-film transistor function at very low source-drain, gate, and threshold voltages (<1 V) and are compatible with a broad variety of vapor- or solution-deposited p- and n-channel organic semiconductors. gate insulator molecular multilayer organic dielectric self-assembly

Carrier transport and density of state distributions in pentacene transistors

Abstract: We present a density of state model for the transport properties of pentacene field effect transistors. Using a one-dimensional transistor model we study the effect of different localized trap distributions on the current-voltage characteristics of such devices. We find that a distributed trap model with a steep exponential band tail of donors and a shallower exponential tail of acceptors inside the band gap can describe consistently our experimental data obtained from bottom-gate polycrystalline pentacene transistors for different gate dielectrics and under various external conditions.

Direct integration of metal oxide nanowire in vertical field-effect transistor

Abstract: We demonstrate seamless direct integration of a semiconductor nanowire grown using a bottom-up approach to obtain a vertical field-effect transistor (VFET). We first synthesize single crystalline semiconductor indium oxide (In2O3) nanowires projecting vertically and uniformly on a nonconducting optical sapphire substrate. Direct electrical contact to the nanowires is uniquely provided by a self-assembled underlying In2O3 buffer layer formed in-situ during the nanowire growth. A controlled time-resolved growth study reveals dynamic simultaneous nucleation and epitaxial growth events, driven by two competitive growth mechanisms. Based on the nanowire-integrated platform, a depletion mode n-channel VFET with an In2O3 nanowire constituting the active channel is fabricated. Our unique vertical device architecture could potentially lead to tera-level ultrahigh-density nanoscale electronic, and optoelectronic devices.

The Simulation of MOS Integrated Circuits Using SPICE2

Abstract: : This report is addressed to all SPICE2 users involved in the design of MOS (Metal Oxide Semiconductor) IC's (Integrated circuits). The material contained herein serves as an addition to the SPICE2.G User's Guide. The device and model parameters documented refer to the SPICE2.G release versions from the University of California, Berkeley and obsolete the information contained in the SPICE2 MOS Modeling Handbook which is valid for the SPICE2.D release versions. The impact of MOS IC s in both analog and digital applications as well as the decreasing dimensions of the single transistors enabled by advances in processing have made it necessary to refine the models and to provide more information about each device as it appears on the circuit layout. Associated with each MOSFET is a drain and source-junction sidewall capacitance (which has a different voltage dependence than the bottom of the diffusion) and a parasitic series resistance. These are unique to a certain geometry. At the model level there are effects which become important as the channel length and width go below 10um. A thorough description of all parameters appearing on the element (device) card and model card is contained in Sec. 2. In SPICE2.G there are three different MOS models available to the user. The Level 1 model is the simple Shichman-Hodges model implemented according to Nagel s SPICE2: A Computer Program to Simulate Semiconductor Circuits. This first order model has been found necessary for checking out the correctness of hand calculations when understanding or developing new circuits. The Level 2 model is an analytical one-dimensional model which incorporates most of the second-order effects of small-size devices. The Level 3 model is a semi-empirical model described by a set of parameters which are defined by curve-fitting rather than physical background.

High-voltage field effect transistors with wide-bandgap β-Ga2O3 nanomembranes

Abstract: Nanoscale semiconductor materials have been extensively investigated as the channel materials of transistors for energy-efficient low-power logic switches to enable scaling to smaller dimensions. On the opposite end of transistor applications is power electronics for which transistors capable of switching very high voltages are necessary. Miniaturization of energy-efficient power switches can enable the integration with various electronic systems and lead to substantial boosts in energy efficiency. Nanotechnology is yet to have an impact in this arena. In this work, it is demonstrated that nanomembranes of the wide-bandgap semiconductor gallium oxide can be used as channels of transistors capable of switching high voltages, and at the same time can be integrated on any platform. The findings mark a step towards using lessons learnt in nanomaterials and nanotechnology to address a challenge that yet remains untouched by the field.