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Transistor

About: Transistor is a research topic. Over the lifetime, 138090 publications have been published within this topic receiving 1455233 citations.


Papers
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Journal ArticleDOI
TL;DR: A new methodology for designing and implementing high-efficiency broadband Class-E power amplifiers (PAs) using high-order low-pass filter-prototype is proposed, which provides optimized fundamental and harmonic impedances within an octave bandwidth (L-band).
Abstract: A new methodology for designing and implementing high-efficiency broadband Class-E power amplifiers (PAs) using high-order low-pass filter-prototype is proposed in this paper. A GaN transistor is used in this work, which is carefully modeled and characterized to prescribe the optimal output impedance for the broadband Class-E operation. A sixth-order low-pass filter-matching network is designed and implemented for the output matching, which provides optimized fundamental and harmonic impedances within an octave bandwidth (L-band). Simulation and experimental results show that an optimal Class-E PA is realized from 1.2 to 2 GHz (50%) with a measured efficiency of 80%-89%, which is the highest reported today for such a bandwidth. An overall PA bandwidth of 0.9-2.2 GHz (84%) is measured with 10-20-W output power, 10-13-dB gain, and 63%-89% efficiency throughout the band. Furthermore, the Class-E PA is characterized through measurements using constant-envelop global system for mobile communications signals, indicating a favorable adjacent channel power ratio from -40 to -50 dBc within the entire bandwidth.

242 citations

Patent
23 Apr 1998
TL;DR: In this article, a pixel structure (200, 300, 400, 600, 700) that reduces current nonuformities and threshold voltage variations in a 'drive transistor' of the pixel structure is disclosed.
Abstract: A LED pixel structure (200, 300, 400, 600, 700) that reduces current nonuformities and threshold voltage variations in a 'drive transistor' of the pixel structure is disclosed. The LED pixel structure incorporates a current source for loading data into the pixel via a data line. Alternatively, an auto zero voltage is determined for the drive transistor prior to the loading of data.

242 citations

Proceedings ArticleDOI
20 Jan 2001
TL;DR: An integrated architectural and circuit level approach to reducing leakage energy in instruction caches (i-caches) using gated-V/sub dd/, a mechanism that effectively turns of the supply voltage to, and eliminates leakage in, the SRAM cells in a DRI i-cache's unused sections.
Abstract: Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately, reducing the transistor threshold voltage. Lowering the threshold voltage increases leakage energy dissipation due to subthreshold leakage current even when the transistor is for switching. Estimates suggest a five-fold increase in leakage energy in every future generation. In modern microarchirectures, much of the leakage energy is dissipated in large on-chip cache memory structures with high transistor densities. While cache utilization varies both within and across applications, modern cache designs are fixed in size resulting in transistor leakage inefficiencies. This paper explores an integrated architectural and circuit level approach to reducing leakage energy in instruction caches (i-caches). At the architectural level, we propose the Dynamically Resizable i-cache (DRI i-cache), a novel i-cache design that dynamically resizes and adapts to an application's required size. At the circuit-level, we use gated-V/sub dd/, a mechanism that effectively turns of the supply voltage to, and eliminates leakage in, the SRAM cells in a DRI i-cache's unused sections. Architectural and circuit-level simulation results indicate that a DRI i-cache successfully and robust exploits the cache size variability both within and across applications. Compared to a conventional i-cache using an aggressively-scaled threshold voltage a 64K DRI i-cache reduces on average both the leakage energy-delay product and cache size 62%, with less than 4% impact on execution time.

241 citations

Patent
27 Nov 1998
TL;DR: In this paper, a technique involving localized irradiation of the film with one or several pulses of a beam of laser radiation, locally to melt the film through its entire thickness, is described.
Abstract: Semiconductor integrated devices such as transistors are formed in a film of semiconductor material formed on a substrate. For improved device characteristics, the semiconductor material has regular, quasi-regular or single-crystal structure. Such a structure is made by a technique involving localized irradiation of the film with one or several pulses of a beam of laser radiation, locally to melt the film through its entire thickness. The molten material then solidifies laterally from a seed area of the film. The semiconductor devices can be included as pixel controllers and drivers in liquid-crystal display devices, and in image sensors, static random-access memories (SRAM), silicon-on-insulator (SOI) devices, and three-dimensional integrated circuit devices.

240 citations

Proceedings ArticleDOI
Y. Takayama1
14 Jun 1976
TL;DR: In this paper, a novel method for microwave power transistor load-pull characterization is presented, where both input and output ports of a test transistor are simultaneously driven by external signals at the same specified frequency.
Abstract: A novel method for microwave power transistor load-pull characterization is presented. The method provides an equivalent load-pull measurement technique without using an output impedance tuner. In this method, both input and output ports of a test transistor are simultaneously driven by external signals at the same specified frequency. Results of its application to a medium-power GaAs FET are given.

240 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20231,850
20224,013
20211,802
20203,677
20194,203
20184,241