Showing papers on "Transmission delay published in 1987"

On Packet Switches with Infinite Storage

Abstract: Most prior work on congestion in datagram systems focuses on buffer management. We find it illuminating to consider the case of a packet switch with infinite storage. Such a packet switch can never run out of buffers. It can, however, still become congested. The meaning of congestion in an infinite-storage system is explored. We demonstrate the unexpected result that a datagram network with infinite storage, first-in, first-out queueing, at least two packet switches, and a finite packet lifetime will, under overload, drop all packets. By attacking the problem of congestion for the infinite-storage case, we discover new solutions applicable to switches with finite storage.

Packet switching system arranged for congestion control

Abstract: A method for controlling congestion in a packet switching network uses a packet dropping algorithm to determine when to drop a marked packet wherever the network is congested at any point along the path being traversed by the marked packet.

Packet switching system arranged for congestion control through bandwidth management

Abstract: In a packet switching network, packet monitoring and marking algorithms are used for determining which data packets, received from a customer by an access node, are being transmitted at an excessive transmission rate and accordingly are marked. Additionally every packet from a special customer can be marked. Along in the network, marked packets are dropped where the network is congested along the path being traversed by the data packets.

Slotted Random Access Spread-Spectrum Networks: An Analytical Framework

Abstract: An analytic framework is proposed for the study of singlehop spread-spectrum networks using random access and packet switching under various network topologies and channel conditions. The key feature of the theory is the identification of a set of probabilistic parameters, which, based on a symmetry argument, serve to efficiently summarize the effect on performance of various network considerations such as transmitter-receiver configuration, spreadspectrum code allocation, error correction and detection mechanisms, spreading format, jamming conditions, etc. Examples investigating capture effects, coding tradeoffs, and scheduling optimizations are presented. Various previously known results are shown to be special cases of the framework that we describe.

Arrangement for testing packet switching networks

Abstract: A packet network test arrangement where a test packet is transmitted from a test source (10) to a test destination (31) via successive notes (11, 20, 28) of the packet network. Any node that fails to receive acknowledgment within a predetermined time of transmitting the test packet to a subsequent node responds by transmitting information to the test source concerning the failure and particularly defining the involved nodes. Accordingly, a single test can be used advantageously both to detect faults and to localize such faults between two network nodes. The test arrangement also provides for the loop-around of test packets received at the test destination thus enabling the test source to verify successful packet communications.

Packet switched interconnection protocols for a star configured optical lan

Abstract: The present invention relates to packet switched interconnection protocols for use in high-speed optical Star-configured Local Area Networks (LANs). In the present Star LAN, a plurality of N+1 wavelength division multiplexed (WDM) channels are provided for use by M transceivers connected to the Star coupler, where preferably M>N. N of the N+1 WDM channels are used for transmission of data packets, and the remaining WDM channel is used by all transceivers for transmitting control packets only. In the present protocols, a transmitter in an active transceiver first send a control packet over the control channel using a first protocol such as, for example, ALOHA or CSMA. The control packet includes (1) the transmitter's unique address, (2) the destined receiver's address, and (3) the address of the data channel to be used in transmitting the associated data packet. Immediately after the control packet is sent, the associated data packet is transmitted over the chosen one of the N data channels using a second protocol such as, for example, ALOHA, CSMA or N-Server Switch. In the Star network, the transceivers receive their own transmissions and detect if a collision or not has occurred, and if a collision is detected the transmission procedure is repeated until successful.

Distributed voice-data switching on multi-stage interconnection networks

Abstract: A method of switching synchronous and asynchronous data packets through a multi-stage interconnection network (MIN), so as to insure that packets with the highest assignable priority level will never be blocked at any stage of the network. More specifically, this invention relates to a method of switching voice and data packets over the MIN wherein each of the address bits in each packet determine the connection to be established at each particular stage in the network and wherein each packet has therein a priority level. In each time slot of a frame, the priority level of the packets stored in a particular originating adapter are compared and the packet with the highest priority level in each adapter is forwarded through the MIN and routed through the MIN as described above. Also, at each subswitch at each stage of the MIN, if two or more packets request the same subswitch output, only the packet with the higher priority is forwarded to the subswitch output. A packet will be assigned the highest priority only if a corresponding packet for a given circuit connection with second highest priority level was successfully transmitted through the MIN.

Time stamping for packet-system nodes.

Abstract: Delay that a packet experiences in a network node is measured by employing a single local time signal in the node, and by separating a time stamp update function into a network node entry stamp function and a network node exit time stamp function. The node entry time stamp function is to generate a packet originate time value referenced to the local time signal value upon the packet entering the node. This packet originate time value is inserted into a packet header time stamp field to be transported through the node. The node exit time stamp function is to generate an updated time stamp value from the packet originate time value from the header time stamp field and the local time signal value upon the packet exiting the node. The undated time stamp value is inserted into the packet header time stamp field in place of the packet originate time value.

A Method for the Delay Analysis of Random Multiple-Access Algorithms Whose Delay Process is Regenerative

Abstract: Random multiple-access algorithms are used to control the accessing of a common communication channel by a large population of bursty channel users. For such algorithms, the induced transmission delay is a key performance measure. A systematic method for finding the delay characteristics of random multiple-access algorithms, whose delay process is regenerative, is presented. The method uses a powerful result from the theory of regenerative processes, in effect, to reduce the problem of determining the delay moments to the problem of solving denumerable dimensional systems of linear equations. Techniques for finding tight bounds on the solutions of such systems are presented. The "0.487" algorithm is used to exemplify the method.

Time stamp and packet virtual sequence numbering for reconstructing information signals from packets

Abstract: Unwanted distortion in signals being reconstructed from packets is substantially eliminated by employing a virtual sequence packet numbering scheme in conjunction with a time stamp value. A virtual sequence number which accompanies the packet identifies the location of the packet in an information spurt. If the packet is the initial packet in the information spurt, the time stamp value is used to "build out" the delay experienced by the packet to a fixed overall value. Subsequent packets in the information spurt are concatenated to the information spurt. A packet following one or more lost packets is also identified by the packet virual sequence number and is also treated as an initial packet.

A New Performance Measurement for Voice Transmission in Burst and Packet Switching

Abstract: Voice transmission in burst switching is characterized by the process of talkspurt clipping, while in packet switching, it is characterized by the process of packet delay. In most analyses, the talkspurt clipping has been measured by the clipping probability averaged over all bits, and the packet delay has been measured by the delay performance averaged over all packets. The resulting measures overlook the duration of clipping in a talkspurt and the significant difference of delay in packets arriving at different times. Because of the nature of voice, different effects of these may result in substantially different degrees of voice distortion. This paper studies the worst case performance of both processes. The voice traffic is modeled as a process alternating between overload and underload periods. Statistically, more clipping and delay will be incurred while in the overload period. By worst case we mean that, in burst switching, we measure the worst case of talkspurt clipping duration in an overload period, while in packet switching, we measure the worst case of packet delay in an overload period. Furthermore, a simple closed form equation is derived which gives a very good approximation of the worst case mean packet delay performance. This equation can be more generally applied when the packet service time is to be geometrically distributed or when voice and data are to be integrated. The voice performances in burst switching and packet switching are also compared.

Variable length packet switching system

Abstract: A packet switching system is disclosed for transmitting variable length packets between system ports. Each byte of each packet has a special one-bit field for indicating whether the byte is the last byte of a packet. A "1" in this field specifies that the byte is the last byte of a packet and activates port control circuitry that changes the potential on a system control conductor to indicate that the system data bus is now idle and free for use by other ports.

Performance of a Service Independent Switching Network with Distributed Control

Abstract: This paper describes a switching network which is service independent and able to transport services of any bit rate, based on the fast packet switching concept. The control of the switching network is completely distributed; the path select is not centrally controlled, but gradually performed as the control packet is passing through the switching network. The switching network is a multistage network constructed with independent switching elements. The self-routing principle is applied. The load control of the different links between the switching elements in the network is provided by a static load control mechanism, applied to the logical connections granted on these links. Logical connections are accepted or rejected according to the already present load on each link. Possible overload caused by bursty traffic is solved by buffers within the switching elements. Simulation results are discussed, both for the static and dynamic behavior of the exchange. For both simulations, a large mix of different services is evaluated and conclusions are described.

Enhanced efficiency Batcher-Banyan packet switch

Abstract: A mechanism is disclosed for resolving conflicts between input ports of a Batcher-Banyan Packet switching network that wish to transmit data packets to the same output port during a particular packet switch cycle. The input ports of the Batcher-Banyon network are connected in a serial ring. Bit positions on the ring represent output ports. Each input port having a data packet to transmit to a particular output port may reserve that output port before the start of the next Batcher-Banyan packet switch cycle by writing a "1" in the ring bit position corresponding to the output port to which the data packet is addressed. If the particular output port has already been reserved by another input port, the data packet is buffered.

Data framing system for time division multiplexing transmission

Abstract: A central station and a plurality of local stations are coupled through a signal transmission path. Data signals addressed to local stations, to which terminal devices such as telephone sets are coupled, are transmitted over the signal transmission path on a time-division multiplexing basis. Each local station sends the data signal onto the signal transmission path at a timing depending on a measured transmission delay time of a signal on the signal transmission path between itself and the central station. One transmission frame consists of subframes of data signals addressed to the local stations and a window frame for transmission delay time measurement. A maximum network length depends on the time duration of the window frame. In order to extend the time duration of the window frame and to increase the maximum network length, data signals for the same terminal device coupled to a local station are multiplexed in one time slot of a subframe.

Packet flow control method

Abstract: A packet flow control method where delay data are added into an initial packet as it traverses a packet switching network, and where the receiver of the initial packet, rather than the sender, establishes a window size based on such delay data to be used for the duration of a packet connection through the network The delay data allow for the calculation of an average rather than an instantaneous network delay such that the flow control mechanism is not dependent on the magnitude of network congestion that happens to be present when the connection is first established Since the receiver determines the window size, the flow control mechanism is put in place as an integral part of the initial packet exchange used to establish the two-way packet connection rather than requiring an additional packet communication to the receiver after a window size calculation by the sender

Batcher-banyan packet switch with output conflict resolution scheme

Abstract: A mechanism for resolving conflicts between input ports of a Batcher-Banyan network that wish to transmit data packets to the same output port during a particular packet switching cycle. In the present invention, each Batcher-Banyan packet switch cycle is divided into three phases. The first phase is an arbitration phase in which output port conflicts are resolved. In the second phase, the results of the arbitration are communicated to the winning input ports. The third phase is a data packet transmission phase in which data packets from the winning input ports are actually transmitted through the Batcher-Banyan network.

Packet switch network protocol

Abstract: A first of a plurality of nodes in a multiprocessor system transmits a data packet to a second of the plurality of nodes over a data channel when the first node detects a predetermined sequence of bits on a control channel connected therebetween. The data packet is preceded on the data channel by a header which includes a plurality of fields informing the second node of the beginning of the data packet, the length of the data packet and the sequence number assigned to the packet. The data packet is followed by a field which enables the second node to determine whether the data packet was received correctly. If the second node determines that the data packet was received correctly, the data packet is stored in the node and an acknowledgement sequence is transmitted to the first node over the control channel. However, if an error occurs during the transmission of the data packet, the protocol enters an error state by removing all signal information from the data and control channels. Thereafter, a recovery processor, which is associated with each of the plurality of nodes, analyzes the state of the nodes at the time of the error in order to determine which corrective action needed to recover the respective node. The data link protocol also facilitates the transmission of a data packet from a first node through an intermediate node to a final node without storing the data packet in the intermediate node.

Control information communication arrangement for a distributed control switching system

Abstract: A switching system (10) including a number of switching modules (1000, 1020, 1050) each having a plurality of access ports (P1, P2, P9, P5). Incoming and outgoing packet channels (81, 82) are extended between each switching module and an inter-module packet switch (2012). Each of the switching modules includes both a packet switching unit (1400) and a circuit switching unit (1011) for switching information to and from the access ports. Each switching module further includes a control unit (1017) that controls the switching units and that generates inter-module conyrol packets, and a communication interface (1900) that transmits inter-module control packets generated by the control unit on the incoming packet channel to the inter-module packet switch. The communication interface also transmits inter-module control packets received on the outgoing packet channel from the inter-module packet switch to the control unit. The inter-module packet switch concurrently packet switches inter-module control packets received on a number of the incoming packet channels, via multiple independent paths (2001, 2002, 2003) to a number of the outgoing packet channels.

An interface circuit for interconnecting circuit switched and packet switched systems

Abstract: An interface circuit 14 is described for interconnecting a packet switched system 13 to a circuit switched system 12 which enables a uniform dialing plan to be utilized to establish intra-system or inter-system connections. This is accomplished by assigning each terminal of the packet switched system a unique terminal address similar to the extension number used for terminals of the circuit switched system. The interface also distinguishes data call set-up requests from other control commands received from the packet switched system.

Packet-switched communications network for efficiently switching non-burst signals

Abstract: In a packet-switched communications network, each of a plurality of node stations is responsive to a request for a circuit-switched call from a source user terminal and transmits a control packet and a message packet in succession to the other node stations. The control packet contains a source address, a destination address, a unique address and a time slot number identifying the time slot in which the circuit-switched call is to be carried. The message packet contains the same unique address as that sent with the preceding control packet and a plurality of time slots identified by the time slot numbers containing in various control packets. On receiving a message packet having the same unique address as that sent with a previous control packet, a destination station extracts an information signal from the message packet using the time slot number contained in the previous control packet and supplies the extracted signal to a user terminal identified by the destination address.

A novel deadlock free and starvation free packet switching communication processor

Abstract: Deadlock and starvation are highly undesirable in packet switching networks. The communication processor presented in this paper was designed such that these phenomena can be proved not to occur. Deadlock is avoided using a new method called class climbing; fair usage of the classes and administration of the temporal order of arrival of the packets guarantee that no starvation can occur. The design is generally applicable in all types of networks, independent of topology or size. A planned VLSI implementation is briefly discussed.

Non-blocking, self-routing packet switch

Abstract: A full access, non-blocking, self-routing packet switch based on a Batcher sorting network is disclosed. Fake place holding packets are utilized along with a conflict resolution scheme to insure that during each packet switch cycle a packet is routed from each input port to each output port. The use of fake place holding packets insures that real packets which contain user data can be routed to the outputs having the addresses contained in their packet headers.

High-Speed Packet Switching Systems for Multimedia Communications

Abstract: High-speed packet switching (HPS) systems can Provide flexible, economical, high-quaiity services for integrated voice, video, and data communications. To realize such HPS systems, methods have been developed to bring about high-speed protocol processing as well as a system architecture for facilitating high-throughput switching. Adopting the parallel processing algorithm into protocol processing allows us to achieve high-speed packet protocol processing of about 100 times faster than conventional processing. Furthermore, a fully distributed system architecture in addition to hierarchical interconnection networks can achieve high-capacity packet switching systems. The proposed HPS system is thus capable of accommodating lines of up to 10-50 Mbits/s, of providing high-throughput switching capability of 1 000 000 packets/s, and of having an average delay of less than 2 ms. Furthermore, an evaluation of network delay performances of video conferencing and voice communications indicate that HPS systems are quite suitable for handling such multimedia communications.

Switching element for self-routing multistage packet-switching interconnection networks

Abstract: The switching element for self-routing multistage packet-switching interconnection networks comprises: an input unit, composed of as many sections (IMA, IMB) as the element inputs are, each section comprising a FIFO memory (FIFA, FIFB) for packet buffering; a switch (SW) associated with a control unit (SCU) which, for each packet to be forwarded, sets up the connection requested for that packet between one input and one or more outputs of the element (ECP), on the ground of a routing tag associated with each packet and comprising a first and a second portion relative to normal routing and to broadcasting in the different stages of the network (RC), and solves possible routing conflicts between packets simultaneously arriving at different inputs; and an output unit, composed of as many sections (RU0, RU1) as the element outputs are and performing the whole of the functions necessary for the correct packet forwarding towards a destination. The control unit (SCU) of the switch (SW) is arranged to handle broadcasting of a packet independently of all other elements (EDP) in the same stage, so as to allow broadcasting also to a number of destinations different from a power of 2 (for an element with two inputs and two outputs) and cooperates with the memory (FIF) storing the packet to be broadcast in such a way that broadcasting does not give rise to internal blocking in the network (RC). Said control unit (SCU) moreover solves routing conflicts so as to set an upper bound to packet permanence time within the network (FIG. 2).

Analysis and Applications of a Multiqueue Cyclic Service System with Feedback

Abstract: In token passing protocols of local area networks, we assume that a user transmits a message which is divided into several packets, and that each packet is transmitted in a round of the circulating token. This transmission from a certain station is interleaved with possible transmissions from other stations. In this paper, a new queueing model is provided to evaluate the mean message delay in contrast to the mean packet delay given by the past studies. The same model is also used to evaluate the mean packet delay in error-prone transmission systems.

Automatic telecommunication switching system

Abstract: An automatic telecommunication switching system handles all communications, whether voice or data, in packet switching manner. The switching network consists of a multi-stage network of co-ordinate matrix elements each of which has memory and processing means. Such an element is a single-chip VLSI device. Each packet has a header which includes the address of the network outlet to which that packet is to be routed, each such address consisting of a digit for each stage via which the packet is to be routed. At each matrix element the appropriate digit of that address is used to route the packet to the appropriate outlet from the matrix element.

Burst and fast packet switching: performance comparisons

Abstract: Two alternatives to the prevailing view of the ISDN backbone are burst switching and fast packet switching. Both these technologies have the potential to provide considerable savings in transmission and switching resources over systems with less integration, and treat the traffic generated by different services in a unified manner. In this paper we explore the significant differences between them from the performance perspective. Other important issues for a complete comparison of the two technologies, such as evolutionary development, processing complexity, and variable bit-rate encoding, are not considered. Burst and fast packet are first compared from a voice-only perspective. For the same TASI advantage and equal capacity, it is shown that fast packet can provide the same performance as burst switching. However, under these circumstances, the average residual capacity left for data is significantly greater for burst than fast packet. Nevertheless, using analytic models for both systems, it is shown that data performance within that residual capacity is — for 64 kb/s encoded voice — not significantly different except for regions of high utilization. A model developed and validated in earlier work is used to analyze the data performance in burst switching. To analyze the performance of data on an integrated packet-switched link, an analytic model is developed based on an earlier renewal theory model for packet voice and using generalized results for priority queues.