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Tunnel field-effect transistor

About: Tunnel field-effect transistor is a research topic. Over the lifetime, 949 publications have been published within this topic receiving 20803 citations. The topic is also known as: TFET.


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TL;DR: In this paper, a modified structure of tunnel field effect transistor (TFET), called the sandwich tunnel barrier FET (STBFET), has been proposed, which has a large tunneling cross-sectional area with a tunneling distance of ~2 nm.
Abstract: We propose a modified structure of tunnel field-effect transistor (TFET), called the sandwich tunnel barrier FET (STBFET). STBFET has a large tunneling cross-sectional area with a tunneling distance of ~2 nm. An orientation-dependent nonlocal band-to-band tunneling (BTBT) model was employed to investigate the device characteristics. The feasibility of the STBFET realization using a complementary metal-oxide-semiconductor-compatible process flow has been shown using advanced process calibration with Monte Carlo implantation. STBFET gives a high ION, exceeding 1 mA/μm at IOFF of 0.1 pA/μm with a subthreshold swing below 40 mV/dec. The device also shows better static and dynamic performances for sub-1-V operations. STBFET shows a very good drain current saturation, which is investigated using an ab initio physics-based BTBT model. Furthermore, the simulated ION improvement is validated through analytical calculations. We have also investigated the physical root cause of the large voltage overshoot of TFET inverters. The previously reported impact of Miller capacitance is shown to be of lower importance; the space-charge buildup and its relaxation at the channel drain junction are shown to be the dominant effect of large voltage overshoot of TFETs. The STBFET are shown to have negligible voltage overshoots compared with conventional TFETs.

142 citations

Journal ArticleDOI
TL;DR: In this article, the authors investigated the impact of source-material modifications on the tunnel current in n-channel nanowire TFETs and developed a semi-analytical model to determine the tunnel probability along the dominant tunnel path.
Abstract: Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because of the absence of short-channel effects and of a subthreshold-slope limit. As a solution to the low on-currents of silicon-based TFETs, the incorporation of silicon-germanium at the source-channel interface has been considered. However, the understanding of the band-to-band-tunneling mechanism at heterojunctions is incomplete. We have investigated through device simulations and modeling the impact of source-material modifications on the tunnel current in n-channel nanowire TFETs. Our modeling work includes the development of a semi-analytical model, which determines the tunnel probability along the dominant tunnel path in two-dimensional TFETs. In particular, we have analyzed the impact of the bandgap, electron affinity, effective mass, dielectric constant, and density of states of both source and channel material. We show that a small-bandgap source material and a large positive electron-affinity of...

139 citations

Journal ArticleDOI
TL;DR: In this paper, the effects of varying the dielectric constant and width of the spacer are studied, and it is observed that the use of a low-dielectric as a spacer causes an improvement in its on-state current.
Abstract: A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low- dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (~30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gate-source overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high- spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it.

139 citations

Journal ArticleDOI
TL;DR: In this article, the effect of drain doping profile on a double-gate tunnel field effect transistor (DG-TFET) and its radio-frequency (RF) performances was investigated.
Abstract: In this paper, we have investigated the effect of drain doping profile on a double-gate tunnel field-effect transistor (DG-TFET) and its radio-frequency (RF) performances. Lateral asymmetric drain doping profile suppresses the ambipolar behavior, improves OFF-state current, reduces the gate-drain capacitance, and improves the RF performance. Further, placing the high-density layer in the channel near the source-channel junction, a reduction in the width of depletion region, improvement in ON-state current (I ON ), and subthreshold slope are analyzed for this asymmetric drain doping. However, it also improves many RF figures of merit for the DG-TFET. Furthermore, lateral asymmetric doping effects on RF performances are also checked for the various channel length. Therefore, this paper would be beneficial for a new generation of RF circuits and systems in a broad range of applications and operating frequencies covering RF spectrum. So, the RF figures of merit for the DG-TFET are analyzed in terms of transconductance (g m ), unit-gain cutoff frequency (f T ), maximum frequency of oscillation (f max ), and gain bandwidth product. For this, the RF figures of merit have been extracted from the V-parameter matrix generated by performing the small-signal ac analysis. Technology computer-aided design simulations have been performed by 2-D ATLAS, Silvaco International, Santa Clara, CA, USA.

138 citations

Journal ArticleDOI
TL;DR: In this paper, a new L-shaped gate tunnel field effect transistor (LG-TFET) is proposed and investigated by Silvaco Atlas simulation, and the gate and n+ pocket region overlap both in the vertical and the lateral directions resulting in an enhanced electric field.
Abstract: In this letter, a new L-shaped gate tunnel field-effect transistor (LG-TFET) is proposed and investigated by Silvaco Atlas simulation. The tunneling junction in the LG-TFET is perpendicular to the channel direction that facilitates the implementation of a relatively large tunneling junction area. The channel is U-shaped that makes the channel mainly distribute in the vertical direction, reducing the device area. The n+ pocket design is also introduced between the source and the intrinsic regions to improve the device characteristic. In addition, the gate and n+ pocket region overlap both in the vertical and the lateral directions resulting in an enhanced electric field, and the ON-state current of the LG-TFET is increased up to $\sim 50$ % compared with the previous L-shaped channel TFET. The minimum subthreshold swing of the LG-TFET is 38.5 mV/decade at 0.2 V gate-to-source voltage. By using the L-shaped gate, U-shaped channel, and the insertion of n+ pocket, the overall performance of the LG-TFET is optimized.

135 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202340
2022107
2021119
2020135
201987
201879