Topic
Two's complement
About: Two's complement is a research topic. Over the lifetime, 345 publications have been published within this topic receiving 4660 citations.
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TL;DR: An algorithm for high-speed, two's complement, m-bit by n-bit parallel array multiplication is described, which is converted to an equivalent parallel array addition problem in which each partial product bit is the AND of a multiplier bit and a multiplicand bit.
Abstract: An algorithm for high-speed, two's complement, m-bit by n-bit parallel array multiplication is described. The two's complement multiplication is converted to an equivalent parallel array addition problem in which each partial product bit is the AND of a multiplier bit and a multiplicand bit, and the signs of all the partial product bits are positive.
663 citations
TL;DR: An algorithm to convert redundant number representations into conventional representations is presented, which is applicable in arithmetic algorithms such as nonrestoring division, square root, and on-line operations in which redundantly represented results are generated in a digit-by-digit manner.
Abstract: An algorithm to convert redundant number representations into conventional representations is presented. The algorithm is performed concurrently with the digit-by-digit generation of redundant forms by schemes such as SRT division. It has a step delay roughly equivalent to the delay of a carry-save adder and simple implementation. The conversion scheme is applicable in arithmetic algorithms such as nonrestoring division, square root, and on-line operations in which redundantly represented results are generated in a digit-by-digit manner, from most significant to least significant.
256 citations
TL;DR: This concise paper addresses the design of multipliers capable of accepting data in 2's complement notation, or both data and coefficients in 1's complement shorthand, and considers multiplier recoding techniques, such as the Booth algorithm.
Abstract: Digital filters and signal processors when realized in hardware often use serial transfer of data. Multipliers which are capable of accepting variable coefficients and data in sign and magnitude notation and producing serial products of the same length as the input data word have been known for some time. This concise paper addresses the design of multipliers capable of accepting data in 2's complement notation, or both data and coefficients in 2's complement notation. It also considers multiplier recoding techniques, such as the Booth algorithm. Specialized (fixed coefficient) multiplier designs are considered briefly. Finally, multiplier rounding and overflow characteristics are discussed, and a rough comparison is made between the complexity of the various designs.
245 citations
TL;DR: It is shown that architectures obtained from this new design technique are more area efficient, and have shorter interconnections than the classical Dadda CC multiplier, and that the technique is also suitable for the design of twos complement multipliers.
Abstract: In this paper, a new design technique for column-compression (CC) multipliers is presented. Constraints for column compression with full and half adders are analyzed and, under these constraints, considerable flexibility for implementation of the CC multiplier, including the allocation of adders, and choosing the length of the final fast adder, is exploited. Using the example of an 8/spl times/8 bit CC multiplier, we show that architectures obtained from this new design technique are more area efficient, and have shorter interconnections than the classical Dadda CC multiplier. We finally show that our new technique is also suitable for the design of twos complement multipliers. >
115 citations
TL;DR: A multibit recoding algorithm for signed two's complement binary numbers is presented and proved and it is shown that a correct SD representation of the original number is obtained by scanning K+1-tuples with one bit overlapping between adjacent groups.
Abstract: A multibit recoding algorithm for signed two's complement binary numbers is presented and proved. In general, a k+1-bit recoding will result in a signed-digit (SD) representation of the binary number in radix 2/sup k/, using digits -2/sup k-1/ to +2/sup k-1/ including 0. It is shown that a correct SD representation of the original number is obtained by scanning K+1-tuples (k>or=1) with one bit overlapping between adjacent groups. Recording of binary numbers has been used in computer arithmetic with 3-bit recoding being the dominant scheme. With the emergence of very high speed adders, hardware parallel multipliers using multibit recoding with k>2 are feasible, with the potential of improving both the performance and the hardware requirements. A parallel hardware multiplier based on the specific case of 5-bit recoding is proposed. Extensions beyond 5-bit recoding for multiplier design are studied for their performance and hardware requirements. Other issues relating to multiplier design, such as multiplication by a fixed or controlled coefficient, are also discussed in the light of multibit recoding. >
94 citations