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UltraSPARC

About: UltraSPARC is a research topic. Over the lifetime, 178 publications have been published within this topic receiving 6263 citations.


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Book
01 Jan 1976
TL;DR: This new edition includes a wealth of new material about modern I/O devices, a detailed discussion of the Java Virtual Machine (including a microprogrammed implementation of a subset of a JVM), extensive coverage of multiprocessing, and much more.
Abstract: From the Publisher: This book takes a modern structured, layered approach to understanding computer systems. It's highly accessible - and it's been thoroughly updated to reflect today's most critical new technologies, including Pentium II and UltraSPARC microprocessors, Windows NT and Java Virtual Machines.Tanenbaum and Goodman present a computer as a series of layers, each one built upon the ones below it, and understandable as a separate entity. The book includes detailed coverage at the digital logic and micro-architecture levels, instruction set level, and operating system machine level, and contains a completely rewritten and updated chapter on parallel computer architecture. This new edition includes a wealth of new material about modern I/O devices, a detailed discussion of the Java Virtual Machine (including a microprogrammed implementation of a subset of a JVM), extensive coverage of multiprocessing, and much more.For all computer professionals and engineers who need an overview or introduction to computer architecture.

1,139 citations

Proceedings ArticleDOI
16 Apr 1997
TL;DR: Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.
Abstract: Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.

1,030 citations

Journal ArticleDOI
TL;DR: UltraSparc's Visual Instruction Set, described here in detail, accelerates some widely used media-processing algorithms by as much as seven times.
Abstract: UltraSparc's Visual Instruction Set, described here in detail, accelerates some widely used media-processing algorithms by as much as seven times. Today's new media, increasingly sophisticated 3D graphics environments, videoconferencing, MPEG video playback, 3D visualization, image processing, and so on, demand enhancements to conventional RISC instruction sets, which were not originally designed to handle such applications. The Visual Instruction Set (VIS) is a comprehensive set of RISC-style instructions targeted at accelerating this new media processing.

266 citations

Proceedings ArticleDOI
18 Sep 2006
TL;DR: The first generation of Niagara SPARC processors implements a power-efficient multi-threading architecture to achieve high throughput with minimum hardware complexity.
Abstract: This first generation of "Niagara" SPARC processors implements a power-efficient Chip Multi-Threading (CMT) architecture which maximizes overall throughput performance for commercial workloads. The target performance is achieved by exploiting high bandwidth rather than high frequency, thereby reducing hardware complexity and power. The UltraSPARC T1 processor combines eight four-threaded 64-b cores, a floating-point unit, a high-bandwidth interconnect crossbar, a shared 3-MB L2 Cache, four DDR2 DRAM interfaces, and a system interface unit. Power and thermal monitoring techniques further enhance CMT performance benefits, increasing overall chip reliability. The 378-mm2 die is fabricated in Texas Instrument's 90-nm CMOS technology with nine layers of copper interconnect. The chip contains 279 million transistors and consumes a maximum of 63 W at 1.2 GHz and 1.2 V. Key functional units employ special circuit techniques to provide the high bandwidth required by a CMT architecture while optimizing power and silicon area. These include a highly integrated integer register file, a high-bandwidth interconnect crossbar, the shared L2 cache, and the IO subsystem. Key aspects of the physical design methodology are also discussed

144 citations

Journal ArticleDOI
TL;DR: The UltraSPARC-III is the third generation of Sun Microsystems' most powerful microprocessors, which are at the heart of Sun's computer systems and ensures compatibility with all existing SPARC applications and the Solaris operating system.
Abstract: The UltraSPARC-III is the third generation of Sun Microsystems' most powerful microprocessors, which are at the heart of Sun's computer systems. These systems, ranging from desktop workstations to large, mission critical servers, require the highest performance that the UltraSPARC line has to offer. The newest design permits vendors the scalability to build systems consisting of 1,000+ UltraSPARC processors. Furthermore, the design ensures compatibility with all existing SPARC applications and the Solaris operating system. The UltraSPARC-III design extends Sun's SPARC Version 9 architecture, a 64-bit extension to the original 32-bit SPARC architecture that traces its roots to the Berkeley RISC-I processor. The UltraSPARC-III design target is a 600-MHz, 70-watt, 13-mm die to be built in 0.25-micron CMOS with six metal layers for signals, clocks, and power.

143 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20181
20172
20151
20131
20124
20113