Universal memory

About: Universal memory is a research topic. Over the lifetime, 1393 publications have been published within this topic receiving 48560 citations.

A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5−x/TaO2−x bilayer structures

Abstract: Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaO(x)-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 10(12). Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

Scalable high performance main memory system using phase-change memory technology

Abstract: The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. An alternative memory technology that uses resistance contrast in phase-change materials is being actively investigated in the circuits community. Phase Change Memory (PCM) devices offer more density relative to DRAM, and can help increase main memory capacity of future systems while remaining within the cost and power constraints.In this paper, we analyze a PCM-based hybrid main memory system using an architecture level model of PCM.We explore the trade-offs for a main memory system consisting of PCMstorage coupled with a small DRAM buffer. Such an architecture has the latency benefits of DRAM and the capacity benefits of PCM. Our evaluations for a baseline system of 16-cores with 8GB DRAM show that, on average, PCM can reduce page faults by 5X and provide a speedup of 3X. As PCM is projected to have limited write endurance, we also propose simple organizational and management solutions of the hybrid memory that reduces the write traffic to PCM, boosting its lifetime from 3 years to 9.7 years.

Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors

Abstract: Memory isolation is a key property of a reliable and secure computing system--an access to one memory address should not have unintended side effects on data stored in other addresses. However, as DRAM process technology scales down to smaller dimensions, it becomes more difficult to prevent DRAM cells from electrically interacting with each other. In this paper, we expose the vulnerability of commodity DRAM chips to disturbance errors. By reading from the same address in DRAM, we show that it is possible to corrupt data in nearby addresses. More specifically, activating the same row in DRAM corrupts data in nearby rows. We demonstrate this phenomenon on Intel and AMD systems using a malicious program that generates many DRAM accesses. We induce errors in most DRAM modules (110 out of 129) from three major DRAM manufacturers. From this we conclude that many deployed systems are likely to be at risk. We identify the root cause of disturbance errors as the repeated toggling of a DRAM row's wordline, which stresses inter-cell coupling effects that accelerate charge leakage from nearby rows. We provide an extensive characterization study of disturbance errors and their behavior using an FPGA-based testing platform. Among our key findings, we show that (i) it takes as few as 139K accesses to induce an error and (ii) up to one in every 1.7K cells is susceptible to errors. After examining various potential ways of addressing the problem, we propose a low-overhead solution to prevent the errors

A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram

Abstract: A novel nonvolatile memory utilizing spin torque transfer magnetization switching (STS), abbreviated spin-RAM hereafter, is presented for the first time The spin-RAM is programmed by magnetization reversal through an interaction of a spin momentum-torque-transferred current and a magnetic moment of memory layers in magnetic tunnel junctions (MTJs), and therefore an external magnetic field is unnecessary as that for a conventional MRAM This new programming mode has been accomplished owing to our tailored MTJ, which has an oval shape of 100 times 150 nm The memory cell is based on a 1-transistor and a 1-MTJ (ITU) structure The 4kbit spin-RAM was fabricated on a 4 level metal, 018 mum CMOS process In this work, writing speed as high as 2 ns, and a write current as low as 200 muA were successfully demonstrated It has been proved that spin-RAM possesses outstanding characteristics such as high speed, low power and high scalability for the next generation universal memory

A durable and energy efficient main memory using phase change memory technology

Abstract: Using nonvolatile memories in memory hierarchy has been investigated to reduce its energy consumption because nonvolatile memories consume zero leakage power in memory cells One of the difficulties is, however, that the endurance of most nonvolatile memory technologies is much shorter than the conventional SRAM and DRAM technology This has limited its usage to only the low levels of a memory hierarchy, eg, disks, that is far from the CPUIn this paper, we study the use of a new type of nonvolatile memories -- the Phase Change Memory (PCM) as the main memory for a 3D stacked chip The main challenges we face are the limited PCM endurance, longer access latencies, and higher dynamic power compared to the conventional DRAM technology We propose techniques to extend the endurance of the PCM to an average of 13 (for MLC PCM cell) to 22 (for SLC PCM) years We also study the design choices of implementing PCM to achieve the best tradeoff between energy and performance Our design reduced the total energy of an already low-power DRAM main memory of the same capacity by 65%, and energy-delay2 product by 60% These results indicate that it is feasible to use PCM technology in place of DRAM in the main memory for better energy efficiency