Showing papers on "Very-large-scale integration published in 1978"

Planar GaAs IC technology: Applications for digital LSI

Abstract: This technology utilizes multiple localized ion implantations directly into semi-insulating GaAs substrates, with unimplanted areas providing isolation between circuit elements. This approach allows for high yield, high density circuits, with optimization of various types of devices (e.g., GaAs MESFETs, high-speed Schottky-barrier diodes, etc.) made possible by optimizing the implantation profile for each type of device. The application of this fabrication technology for high-speed, ultra low power digital integrated circuits using a new circuit approach called Schottky diode-FET logic (SDFL) is described. Experimental GaAS SDFL logic ICs with LSI/VLSI compatible power levels (200-500 /spl mu/W/gate) and circuit densities (<10/SUP -3/ mm/SUP 2//gate) have been fabricated.

Methods for Hierarchical Automatic Layout of Custom LSI Circuit Masks

Abstract: A new automatic IC mask layout code is described which avoids most of the problems inherent in the present generation of layout codes such as lack of flexibility, inefficient use of area, and restricted design complexity. The structured hierarchical layout approach, construction graphs, and placement and routing algorithms are outlined.

MA-4 the prospects for ultra-high speed VLSI GaAs digital logic

Abstract: Recent advances in the state of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance ( \tau_{d} \sim 100 ps) GaAs digital IC's with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. It is the purpose of this paper to evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. The paper includes a performance comparison analysis of Si and GaAs FET's and switching circuits which indicates that, for equivalent speed-power product operation, GaAs IC's should be about six times faster than Si IC's. The state of the art in GaAs IC fabrication and logic circuit approaches is reviewed, with particular emphasis on those approaches which are LSI/VLSI compatible in power and density. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits (which have demonstrated equivalent gate delays as low as \tau_{d} = 110 ps).

A study of standard building blocks for the design of fault-tolerant distributed computer systems

Abstract: This paper presents the results of a study that has established a standard set of four semiconductor VLSI building-block circuits These circuits can be assembled with off-the-shelf microprocessors and semiconductor memory modules into fault-tolerant distributed computer configurations The resulting multi-computer architecture uses self-checking computer modules backed up by a limited number of spares A redundant bus system is employed for communication between computer modules

Self-aligned contacts in an ion implanted VLSI circuit

Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate Mask alignment tolerances are increased and rendered non-critical The use of materials in successive layers having different etch characteristics permits selective oxidation of only desired portions of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking There results VLSI circuits having increased density and reliability The process allows the simultaneous doping of two or more regions resulting in uniformity of device characteristics

A 64-kbit dynamic MOS RAM

Abstract: A 64-kbit dynamic MOS RAM is developed by using 2 /spl mu/m rule VLSI fabrication technology and low power circuit technology. The 2 /spl mu/m rule VLSI fabrication technology is achieved by improving various aspects of the ultraviolet photolithographic, thin-gate oxidation, arsenic ion implantation, and multilevel interconnection processes. Microminiaturization of the device structure has made the voltage requirements for its MOST threshold voltage and DC supply voltages low. A highly sensitive and low power dissipating sense circuit has been developed for the VLSI RAM. A new level-detecting circuit with a logic threshold which is independent of MOST threshold voltage is proposed. A dynamic address-buffer circuit is also shown. The fabricated 64K RAM has 200 ns of access time, 370 ns of minimum cycle time, and 150 mW of power dissipation under typical supply voltage conditions of V/SUB DD/=7 V and V/SUB BB/=-2 V.

Ultra-High Density VLSI Modules

Abstract: A novel packaging approach is described for low-power digital VLSI (very large-scale integration) technologies, which provides low-capacity interconnections throughout and eliminates higher packaging levels. The approach is based on the use of hybrid circuits utilizing high-density interconnections on sapphire substractes with a Fotoceram (trademark-Corning Glass Company) backing. These sapphire/Fotoceram wafers are assembled in a single stack, and wafer-to-wafer interconnections are provided by a ring of elastomeric contacts. This assembly is mounted in a sealed container utilizing ebullient cooling. This design provides very high packaging densities, minimizes circuit delays, and is easily maintainable.

Microprocessors: How VLSI impacts computer architecture: A solution is suggested to the imminent problem of having more computer intelligence on a chip than anyone can use

Abstract: A solution is suggested to the imminent problem of having more computer intelligence on a chip than anyone can use. The author suggests a specific direction for a future VLSI microprocessor architecture.

VLSI Processing, Radiation, and Hardening

Abstract: Process-induced radiation damage to silicon dioxide films is expected to be commonplace for VLSI circuit fabrication. This might be expected to be most serious for the production of radiation-hardened VLSI. In this paper, the oxide damage due to ion processing is reviewed and the radiation levels associated with advanced lithographic techniques are estimated. Implications for radiation-hardened VLSI circuits are considered.

An approach to using VLSI in digital systems

Abstract: We explore the use of a proposed general purpose programmable Storage/Logic Array chip (SLA) as a universal logic element for digital computers. Design examples are given to show how SLAs could be used in computer design. This approach to VLSI is compared and contrasted with other contending approaches using microprocessors, gate arrays and customized VLSI chips. The SLA appears attractive because of low cost, reasonable high performance and shorter implementation time.

Selective Controllability: A Proposal for Testing and Diagnosis

Abstract: This paper proposes a testing and diagnostic method that reduces fault location and repair costs on printed circuit boards populated with LSI and VLSI modules. The method requires some additional circuitry on the module subassembly. It enhances the following test strategies: automatic probing, bed-of-nails, Subassembly-in-Place, and Level Sensitive to Scan Design (LSSD). In addition, this technique makes it possible to partition large networks into manageable subnetworks for Automatic Test Generation.

VLSI - Very large scale integration

Abstract: • VLSI is an implementation technology for electronic circuitry – it can be used for either analogue or digital circuitry – but we are concerned here with digital circuitry • It is concerned with – forming a pattern of interconnected switches and gates on the surface of a crystal of semiconductor • Key technology – used in computers – consumer devices • televisions, radios, telephones • CD players, automatic cameras • washing machines, etc. – has made highly sophisticated control systems mass-producable and therefore cheap.

The Oregon Report Basic Technology

Abstract: Computer technology will continue to advance, and the capabilities we need will exist in VLSI. But capitalizing on them will require innovative design tools and architectures.

CAD VLSI design techniques and microprocessor application

Abstract: This paper will describe CAD techniques, including fully automatic layout capabilities for VLSI devices and the application of a CMOS-SOS microprocessor. Methods for debugging critical race and delay variations will also be discussed.

A New VLSI Printer

Abstract: In order to accurately achieve VLSI micro-lithography for integrated circuit applications, with high throughput, new optical printing systems are required. The manufacturer of a projection alignment system must contend with and solve numerous problems in optical, electronic, and mechanical technologies. This paper describes a new projection aligner, and the solutions which were employed to achieve the desired goals. Test results are given where applicable. Included is the basic optical concept, methods of achieving VLSI precision alignment, operator-machine interaction, and the high intensity exposure system. In addition, for VLSI imaging,an automatic focusing system has been designed which monitors the focus of the wafer through the actual optical path. A system of automatic wafer alignment will also be described.

Heavy ion radiation effects in VLSI

Abstract: : Impressive results have been achieved using electron beam, soft x-ray, or synchrotron radiation for lithography and photoresist exposure. Application to microelectronic circuitry paved the way for Very Large Scale Integration (VLSI) in which device sizes of micron and submicron dimension are forecast. This small size presents new problems for radiation effects test and assessment. One example is the interaction of heavy ions (namely, cosmic rays) with a VLSI size device and the associated nonequilibrium dosimetry involved. This report treats the case of VLSI exposure in satellite environment. The numbers suggest that very small size is not a desirable feature for devices in that environment. (Author)

The evolution of FET technology for VLSI applications

Abstract: An overview of the development of a 1 µm MOSFET technology using electron beam lithography for VLSI applications is described. Various aspects of the technology including device design, threshold stability, reliability studies, dimensional control and performance evaluation will be reviewed briefly. Experimental results based on a device test chip and a circuit test chip will be presented as confirmation of device design and circuit performance in a VLSI chip environment.

Implications Of VLSI On Computer Design(Panel Discussion)

Abstract: Strictly speaking, the term “Very Large Scale Integration” refers to the number of gates or elementary cells which can be reliably fabricated on a single integrated circuit chip. The current state of the art yields memory chips having 16K elements and random logic (microprocessor) chips having 5K gates. The near future should see 64K bit memory chips and 10K gate random logic chips in production. Utilizing this tremendous gate density in the design of the “random logic” portion of computers is not at all straight-forward. It is the objective of this panel session to identify and discuss many of the technical issues related to designing computers with VLSI. This document will serve to highlight several of these issues. A brief bibliography is included for those who would like to pursue this subject further.

Modular Digital Missile Guidance.

Abstract: : A set of macromodular microcomputer specifications has been prepared to meet a wide range of missile guidance and control requirements. These specifications define the function performance and interface requirements of each microcomputer module i.e. microprocessor, memory and input-output I/O interface for analog and serial digital I/O, such that device technology improvements can continually be accommodated within the bounds of module function performance and interface requirements. To ensure such flexibility in design, other alternative device technologies were reviewed and evaluated for the MIL-STD-4553A serial digital I/O interface and the spectrum analyzer module, viz: fiber-optic data link and charge-coupled device, (CCD), very-large-scale integration (VLSI) analyzer options. In addition the requirements for universal microcomputer development systems were explored in order to support both medium-speed single-chip microprocessors and high-speed bit-slice emulators to preserve software commonality. Lastly, the compatibility of the Navy AN/UYK-30 microprocessor with the macromodular microcomputer family was investigated on the basis of throughput and electrical interface. In summary, this phase of the program has culminated in the generation of a practical set of microcomputer module specifications for multi-source procurement. (Author)

Bipolar structures for BIMOS VLSI

Abstract: Recent advances in VLSI has offered many possibilities in mixing MOSFET and Bipolar integrated structures on the same chip. The purpose of this work is to study the integration of bipolar structures in BIMOS VLSI environments. More specifically bipolar structures are studied under the constraints and guidelines of a given MOS technology; e.g. the non-exsistance of a n+underlayer, and the high epitaxial (substrate) resistivity. A bipolar structure, based on merging a multicollector p-n-p transistor with a multiemitter n-p-n transistor is proposed. The structure takes advantage of the availability of clock signals on a MOS chip. It can be used to realise analog, logic, memory, and digital functions. Computer simulation as well as experimental results, show that the structure can perform efficiently in a wide range of BIMOS VLSI technologies.

Fault detection of MOS combinatorial networks

Abstract: Since the technology has gone into large and very large scale integration (LSI and VLSI), one important problem is the testing of such integrated circuits. Recently, increasing interest and attention has been given to “design for testability” or design of diagnosable digital networks.Computer algorithms for designing diagnosable metal oxide semiconductor (MOS) networks have recently been presented by these authors. In this paper, we discuss the testing aspect of these designed networks.A basic cell model was presented for the purpose of simulation and test generation. Procedures for describing the generation of a complete fault detection set for the complex cell are given. Both minimal and near-minimal solutions are presented for both fan-out free and arbritrary complex cells respectively. Also, a procedure for generating the fault detection test list for arbitrary combinational networks is given also.Some future work problems are presented and the application of this design technique for improving the LSI and VLSI testability is introduced.