Showing papers on "Very-large-scale integration published in 1979"

Area-time complexity for VLSI

Abstract: The complexity of the Discrete Fourier Transform (DFT) is studied with respect to a new model of computation appropriate to VLSI technology. This model focuses on two key parameters, the amount of silicon area and time required to implement a DFT on a single chip. Lower bounds on area (A) and time (T) are related to the number of points (N) in the DFT: AT2≥ N2/16. This inequality holds for any chip design based on any algorithm, and is nearly tight when T = θ(N1/2) or T = θ(log N). A more general lower bound is also derived: ATx = Ω(N1+x/2), for 0≤×≤2.

Let's Design Algorithms for VLSI Systems

Abstract: Very Large Scale Integration (VLSI) technology offers the potential of implementing complex algorithms directly in hardware [Mead and Conway 79). This paper (i) gives examples of algorithms that we believe are suitable for VLSI implementation, (ii) provides a taxonomy for algorithms based on their communication structures, and (iii) discusses some of the insights that are beginning to emerge from our efforts in designing algorithms for VLSI systems.

Direct VLSI Implementation of Combinatorial Algorithms

Abstract: We present new algorithms for dynamic programming and transtivc closure which arc appropriate for very large-scale integration implementation.

Systolic Priority Queues

Abstract: Very large scale integrated (VLSI) circuit technology has made it possible to build multiprocessor hardware devices to aid in the rapid solution of sophisticated problems. An algorithms designer wishing to take full advantage of the massive parallelism offered by VLSI must address geometric issues hitherto relegated to layout artists. The reason for this is that VLSI is a planar technology in which the interconnections among components on a chip may cost more than the components themselves. The designer of a multiprocessor algorithm to be implemented in this technology must consider the complexity of the data paths between processors in evaluating the algorithm.

The cube-connected-cycles: A versatile network for parallel computation

Abstract: We introduce a network of processing elements, the cube-connected-cycles (CCC), complying with the present technological constraints of VLSI design. By combining the principles of parallelism and pipelining, the CCC can emulate the cube-connected machine with no significant degradation of performance but with a much more compact structure. We describe in detail how to program the CCC for efficiently solving a large class of problems, which includes Fast-Fourier-Transform, sorting, permutations, and derived algorithms. The CCC can also be used as a general purpose parallel processor.

1 µm MOSFET VLSI technology: Part II—Device designs and characteristics for high-performance logic applications

Abstract: Micrometer-dimension n-channel silicon-gate MOSFET's optimized for high-performance logic applications have been designed and characterized for both room-temperature and liquid-nitrogen-temperature operation. Appropriate choices of design parameters are shown to give proper device thresholds which are reasonably independent of channel length and width. Depletion-type devices are characterized at room temperature for load device use. Logic performance capability is demonstrated by test results on NOR circuits for representative fan-out and loading conditions. Unloaded ring oscillators achieved switching delays down to 240 ps at room temperature and down to 100 ps at liquid nitrogen temperature.

The prospects for ultrahigh-speed VLSI GaAs digital logic

Abstract: Recent advances of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance GaAs digital ICs with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. The authors evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. GaAs IC fabrication and logic circuit approaches is reviewed. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits.

Testing Logic Networks and Designing for Testability

Abstract: VLSI has brought exciting increases in circuit density and performance capability. But it has also aggravated the problem of chip, component and system testing. Here are some approaches to dealing with that problem.

Placement Algorithms for Arbitrarily Shaped Blocks

Abstract: New placement algorithms have been developed which are suitable for the layout of Very Large Scale Integrated (VLSI) circuits. Hierarchical decomposition is used to reduce the circuit function to a size that can be comprehended by the designer and is computationally feasible to layout. At each hierarchical level the problem consists of the placement of interconnected rectangular blocks of arbitrary size and shape such that the area occupied by the blocks and their interconnections is minimal. Constructive initial placement and iterative improvement algorithms are presented.

Self-Timed VLSI Systems

Abstract: This short paper is intended to explain why the subject of self-timed logic is relevant to a conference on VLSI. Scaling down feature size and scaling up chip area not only increases the complexity of chips, but also changes relationships in the parameters which describe the physical characteristics of switching devices, circuits, and wires. The physical change which most impacts the design disciplines employed for VLSI -- particularly the timing aspect of design -- is the increased wire delay associated with the increased resistivity of scaled down wires. Wires that run even a small fraction of the way across a chip will impose a significant delay. Clock distribution and long-distance communication required by synchronous systems will become problematic. Otherwise, it appears that the timing aspect of design for submicron feature size circuits will generally resemble that of today's MOS technology, in that delays will be largely determined by parasitic wiring capacitance.

A Programmable Logic Approach for VLSI

Abstract: This paper explores the use of a proposed programmable storage/logic array (SLA) chip as a general purpose universal logic element for digital computers. The SLA is compared to other programmable logic arrays in implementation and utilization, showing how it permits construction of complete digital subsystems on one chip without sacrifice in programmability. When compared with other contending very large-scale integrated technology (VLSI) approaches, such as microprogrammed processors and gate arrays, the SLA offers an attractive combination of cost, performance, and ease of implementation.

Cost and performance of VLSI computing structures

Abstract: Using VLSI technology, it will soon be possible to implement entire computing systems on one monolithic silicon chip. Conducting paths are required for communicating information throughout any integrated system. The length and organization of these communication paths place a lower bound on the area and time required for system operations. Optimal designs can be achieved in only a few of the many alternative structures. Two illustrative systems are analyzed in detail: a RAM-based system and an associative system. It is shown that in each case an optimum design is possible using the area-time product as a cost function.

Solid State: VLSI: Some fundamental challenges: Defining and designing the products made possible by very-large-scale integration are first on the list of priority tasks

Abstract: A tremendous interest in VLSI is all around us. There is much talk of electron-beam and X-ray lithography tools to achieve VLSI's submicron structures. In all of the discussions, the implication is that VLSI will allow us to enjoy the same kind of fantastic low-cost advantages that previous IC technologies have provided in electronic products. Perhaps. But if the semiconductor industry had today a commercial million-transistor technology like VLSI, I'm not so sure it would know what to do with it. Besides products containing memory devices, it isn't clear how future VLSI can be used in electronic products.

The evolution of digital electronics towards VLSI

Abstract: Technological trends are extrapolated to the end of this century. Problems of utilizing high levels of integration are noted, and the capabilities of technology are viewed in the perspective of the problems to provide a forecast of the levels of integration that will be found in large computing systems. A physical model and some more speculative system assumptions are used to estimate the performance of the systems. The physical characteristics forecast for the system are summarized.

The evolution of digital electronics towards VLSI

Abstract: Technological trends are extrapolated to the end of this century. Problems of utilizing high levels of integration are noted, and the capabilities of technology are viewed in the perspective of the problems to provide a forecast of the levels of integration that will be found in large computing systems. A physical model and some more speculative system assumptions are used to estimate the performance of the systems. The physical characteristics forecast for the system are summarized.

1 /spl mu/m MOSFET VLSI technology. II. Device designs and characteristics for high-performance logic applications

Abstract: For pt.I see ibid., vol.SC14, no.2, p.240 (1979). Micrometer-dimension n-channel silicon-gate MOSFETs optimized for high-performance logic applications have been designed and characterized for both room-temperature and liquid-nitrogen-temperature operation. Appropriate choices of design parameters are shown to give proper device thresholds which are reasonably independent of channel length and width. Depletion-type devices are characterized at room temperature for load device use. Logic performance capability is demonstrated by test results on NOR circuits for representative fanout and loading conditions. Unloaded ring oscillators achieved switching delays down to 240 ps at room temperature and down to 100 ps at liquid nitrogen temperature.

Fault detection and isolation system

Abstract: OF THE DISCLOSURE The invention provides data processing duplication and internal error checking within an integrated circuit chip at intermediate points along the logic chain. In one aspect of the invention. duplicate functional logic within the chip is utilized together with multiple fault detectors to provide error checking of the primary logic chain, mechanical inter-connection failures, and power and clock pulse checking. The detectable failures are both transient and hard failures. Other problems are in addition resolvable by utilization of duplicate complementary logic in place of duplicate functional logic, such other problems including chip contamination during manu-facture, mask problems and functional design problems. The multiple fault detectors provide a multiplicity of error signals which are multiplexed within the chip to produce encoded output error signals each of which designates the fault which has been detected within the chip. These encoded error signals are routed to a special error handling chip which receives encoded error signals from a large number of places, such as a group of chips or circuit cards, and by correlating the information contained in the encoded error signals is able to identify the source of the error as a particular VLSI chip, the interconn-ections between VLSI chips, a particular circuit card, a power supply line to a circuit card or a group of such cards. or other faults.

Model and performance of hot-electron MOS transistors for VLSI

Abstract: VLSI reduces the dimensions of MOS transistors so far that the product of channel length L and hot-electron critical field E C becomes comparable to or smaller than the transistor operating voltages. These transistors are classified as hot-electron MOS (HEMOS) transistors. On the basis of a hyperbolic velocity-field characteristic, a powerful nonlinear analytical model both for conductive and capacitive contributions is presented, which covers the triode and saturation regions continuously. The crucial parameter is the pinch-off field E G , for which a sensitive measurement technique is described. Static and dynamic simulations are in good agreement with 2-µm transistors and circuits, self-aligned by ion implantation. Expressions are developed for transistor transconductance, output resistance, available voltage gain, and effective input capacitance as well as inverter supply voltage, threshold voltages, ratio, noise margin, power dissipation, and delay time. These quantities are in terms of the characteristic product of channel length L and pinch-off field E G so that the effects of scaling into the submicron regime can be predicted as demonstrated by the design parameter set for a 5-fJ inverter with a 0.5-µm HEMOS driver transistor.

1 µm MOSFET VLSI technology: Part VI—Electron-beam lithography

Abstract: This paper discusses the fabrication of 1 µm minimum linewidth FET polysilicon-gate devices and circuits. These were designed for the tight dimensional ground rules (resolution, linewidth control, and overlay) achievable using direct wafer write scanning electron-beam lithography with individual chip registration. The present work focuses on vector-scan electron-beam technology and processing, while other papers in this series discuss other aspects of the work. Different types of 1 µm MOSFET chips were written on 57 mm Si wafers using a totally automated electron-beam system which performs table stepping, registration to fiducial marks, and pattern writing in a vector scan mode (on an individual shape basis) with control of exposure dose for individual shapes. The pattern data were prepared by batch processing which includes proximity correction as well as sorting of shapes to achieve data compaction and minimal distance between shapes. A novel two-layer positive resist system has been developed to achieve reproducible liftoff profiles over topography and better linewidth control. The final results presented here demonstrate that there are no fundamental barriers to the extension of this work to small dimensions.

Electron-beam testing of VLSI circuits

Abstract: The voltages at the internal voltage nodes of an IC have to be measured if the device operates imperfectly or the quality of a device or computer simulation have to be checked. Whereas the mechanical probe conventionally used for this purpose usually imposes such a large capacitive load on the specimen that its performance undergoes a change, the electron probe is both nonloading and nondestructive and can be used not only for quantitative waveform measurements on an IC but also for obtaining images of the logical states of relatively large portions of its circuit configuration. Since each type of configuration calls for a separate measuring technique, six different techniques are treated and their application and equipment needs described. The state of the art of electron-beam testing is demonstrated with reference to three typical applications, viz., checking a decoding schema, measuring the sense signal (approximately 300 mV) of a 16-kbit MOS RAM, and checking the operation of the timing circuitry of a 4-bit microprocessor. The present applicational limitations and future perspectives of electron-beam testing are discussed.

A Placement Capability Based on Partitioning

Abstract: Placement is one of the numerous coordinated capabilities of the Hughes Computer-Aided Design (CAD) System. It is applicable to all of the technologies currently used to produce digital electronic assemblies and is particularly well suited to the allocation requirements of LSI and VLSI. The algorithm that is used iteratively selects sequences of module interchanges that minimize the number of signal crossings over a designated partition (line) across the assembly. An orderly succession of horizontal and vertical partitions causes a rearrangement of modules that facilitates routing, distributes wiring density and achieves minimal wirelength. The placement algorithm, its computational efficiency, its robust applicability, and the parts it plays within the Hughes CAD System are presented.

Topological Analysis for VLSI Circuits

Abstract: Algorithms are presented which use a bit map approach to derive connectivity checks, design rule checks, and electrical parameters for VLSI circuit artwork

Circuit optimization of the taper isolated dynamic gain RAM cell for VLSI memories

Abstract: A one transistor only, ROM like dynamic RAM cell, whose operation depends on the modulation of the threshold of a buried channel device by a hole packet, derived from the channel stop region will be covered. Tapered oxide between the field and gate oxide is used to form a potential barrier for holes.

A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital systems

Abstract: A fully ion-implanted process allows high-density integration of NMOS, CMOS, and bipolar transistors for VLSI of analog-digital systems. Supply voltage can be 20 V. Thresholds are /spl plusmn/1.5 V for p- and n-channel enhancement transistors, respectively. Standard deviation per wafer is 15 mV for the NMOS threshold, while the NMOS gain constant is 30 /spl mu/AV/SUP -2/. The bipolar transistors have a low-resistance base contact. Current gain can be set independently. For current gain=90, the Early voltage if V/SUB A/=110 V. No epi layer, isolation diffusions, or channel stoppers are required. The mask count is 6 for structure definition plus 2 for the masking of implants. The process can be scaled along the learning curve of digital MOS VLSI.

Electron-beam testing of VLSI circuits

Abstract: The electron probe is both nonloading and nondestructive and can be used not only for quantitative waveform measurements on an IC but also for obtaining images of the logical states of relatively large portions of its circuit configuration. Since each type of configuration calls for a separate measuring technique, six different techniques are treated and their application and equipment needs described. The state of the art of electron-beam testing is demonstrated with reference to three typical applications, viz., checking a decoding scheme, measuring the sense signal (approximately 300 mV) of a 16-kbit MOS RAM and checking the operation of the timing circuitry of a 4-bit microprocessor. The present applicational limitations and future perspectives of electron-beam testing are discussed.

VLSI Design Methodology - the Problem of the 80's for Microprocessor Design

Abstract: The rapid evolution of semiconductor technology continues to make possible increasingly sophisticated electronic systems on single chips of silicon. By 1982, a single silicon chip is projected to have well over 100,000 transistors. This level of complexity represents a major problem for the VLSI designer in the 1980's. Unless there is a fundamental change in design methodology, this level of VLSI technology will be grossly under-utilized due to the problems of design, layout and checking. With present design methods, the mask set for a 100,000 transistor MOS chip will take 60 man years to lay out and another 60 man years to debug.

Single-Chip Computers, the New VLSI Building Blocks

Abstract: Current trends in the design of general purpose VLSI chips are analyzed to explore what a truly modular, general-purpose component for digital computing systems might look like in the mid 1980's. It is concluded that such a component would be a complete single-chip computer, in which the hardware for effective interprocessor communication has been designed with the architecture of the overall multiprocessor system in mind. Computation and communication are handled by separate processors in such a manner, that both can be performed simultaneously with full efficiency. This paper then describes relevant features of X-TREE, a research project which addresses the question how the power of VLSI of the next decade can best be used to build general purpose computing systems of arbitrary size. In X-TREE, a general VLSI component realizable in the mid 1980's is defined, and its interconnection into a hierarchical tree-structured network is studied. The overall architecture, communications issues and the blockdiagram of the modular component used are discussed.

Analog-binary CCD correlator: a VLSI signal processor

Abstract: Designs of key sections of a 512-stage correlator are discussed. The chip measures nearly 400 by 300 mils and contains all circuits necessary to accept and store a reference code and compare it to a signal. In addition, it contains many support circuits including the clock logic and drivers, code load logic, and TTL-to-MOS converters. Design of the floating-gate tap structure minimizes code-dependent bias, harmonic distortion, and tap-to-tap nonuniformity, while holding power dissipation to 1 mW per tap. Electron-beam lithography was used to produce photomasks with low defect density and tight dimensional tolerances over the array.

High-resolution lithography with projection printing

Abstract: Very large-scale integration (VLSI) will want to increase circuit density and to reduce power dissipation at no sacrifice in speed. It will, therefore, ask for ever smaller circuit geometries, which, because of the increased sensitivity to defects, can economically be only projection printed. Projection optics are diffraction limited. Only blurred images of the mask expose the photoresist on the silicon wafer: the whole photoprocess becomes increasingly sensitive to variations of its many parameters. The parameters' interdependencies have been modeled identifying four distinct process steps. Measurement techniques are described, which allow to quantize each step independently. With standard IC technology one may measure the illumination profiles of the mask image directly in the projection printer. Characteristic curves describe the photoresist response to exposure. A simple time measurement allows to real-time control the photoresist development. Finally, the concept of an operating point on a characteristic is introduced. It helps to define an optimized set of process parameters.