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Showing papers on "Very-large-scale integration published in 1980"


Journal ArticleDOI
TL;DR: Structured VLSI design proceeds from algorithm to logic cell to cell array to special-purpose chip, yielding cheap, powerful, and modular hardware that will permanently alter the systems landscape of the 80's.
Abstract: Structured VLSI design proceeds from algorithm to logic cell to cell array to special-purpose chip, yielding cheap, powerful, and modular hardware that will permanently alter the systems landscape of the 80's.

258 citations


Journal ArticleDOI
TL;DR: In this paper, a method for testing the logic function of complex digital integrated circuits is presented, which is based on an adapted version of signature analysis, and on circuit partitioning (the structure of VLSI circuits is assumed to be inherently modular).
Abstract: A method for testing the logic function of complex digital integrated circuits is presented. The extra hardware needed is kept minimal by functional conversion of already existing components (e.g., registers). The feasibility of the proposed method is demonstrated by results from both hardware simulation and logic simulation. The method is based on an adapted version of signature analysis, and on circuit partitioning (the structure of VLSI circuits is assumed to be inherently modular).

174 citations


Proceedings ArticleDOI
14 May 1980
TL;DR: In this paper, the use of VLSI technology to perform relational database operations directly in hardware is proposed, such as intersection, remove-duplicates, union, join and division, which can all be pipelined elegantly and efficiently on networks of processors having an array structure.
Abstract: This paper proposes the use of VLSI technology to perform relational database operations directly in hardware. It is shown that relational compulations, such as intersection, remove-duplicates, union, join, and division, can all be pipelined elegantly and efficiently on networks of processors having an array structure. These (systolic) processor arrays are readily and cost-effectively implementable with present technology, due to the extreme simplicity of their processors, and the high regularity of their interconnection structures.

139 citations


Proceedings ArticleDOI
28 Apr 1980
TL;DR: Lower and upper bounds on the area-time complexity for chips that implement binary arithmetic are derived, assuming a model of computation which is intended to approximate, current and anticipated LSI or VLSI technology.
Abstract: The chip complexity of a computation is concerned with the chip area, A, and the time, T, required to perform the computation when implemented on a chip. An area-time product ATα,for α ≥ 0, is used as a complexity measure. A particular value of α, which is chosen by the user, reflects the relative importance between A and T. This paper derives lower and upper bounds on the area-time complexity for chips that implement binary arithmetic, assuming a model of computation which is intended to approximate, current and anticipated LSI or VLSI technology.

125 citations


01 Jan 1980

122 citations


Journal ArticleDOI
A.D. Lopez1, H.-F.S. Law1
TL;DR: A rapid and systematic method for performing chip layout of VLSI circuits is described, which utilizes the configuration of a matrix composed of interacting rows and columns to provide transistor placement and interconnections.
Abstract: A rapid and systematic method for performing chip layout of VLSI circuits is described. This method utilizes the configuration of a matrix composed of intersecting rows and columns to provide transistor placement and interconnections. This structure, which is orderly and regular, gives high device-packing density and allows ease of checking for layout errors. Resulting layouts may be updated to new design rules automatically. This method has been used in the layout of a 20 000-transistor section of a VLSI circuit.

119 citations


Book
01 Jan 1980
TL;DR: This chapter discusses digital filter, an established method of filtering electrical waveforms and digital images, and it is an important topic in a number of diverse fields of science and technology.
Abstract: In this chapter, digital filter are discussed. Digital signal processing (DSP) is an established method of filtering electrical waveforms and digital images, and it is an important topic in a number of diverse fields of science and technology. The realisation of the many practical applications has been made possible by the increased availability and falling costs of sophisticated very-large-scale integrated (VLSI) circuits. In particular, the ubiquitous microprocessor and associated peripheral chips provide the means of implementing relatively simple and cost-effective digital filters.

111 citations


Proceedings ArticleDOI
Louis Carl Parrillo1, R.S. Payne, R.E. Davis, G.W. Reutlinger, R.L. Field 
01 Jan 1980
TL;DR: In this article, a two-tub approach was adopted to enable a separate optimization of both transistors and to utilize the dopant control available with implanted layers, a combination of n on n+epi and careful I/O layout rendered the circuits latch-up free.
Abstract: CMOS technology has been developed through several generations of design rules with an n-type substrate (where p-channel transistors were formed) and with a p-tub implanted and diffused region (where n-channel transistors were formed). In order to enable a separate optimization of both transistors and to utilize the dopant control available with implanted layers, a two-tub approach was adopted. Utilizing lightly doped epi on an n+substrate (for latch-up protection), nitride-masked self-aligned tubs, 1016cm-3surface doping and 600A gate oxides, an 8-mask CMOS process (named 'Twin-Tub") was formulated. The combination of n on n+epi and careful I/O layout renders the circuits latch-up free. Novel aspects of the process, the devices it produces and finally the resultant circuit performance are herein described.

86 citations


Proceedings ArticleDOI
24 Dec 1980
TL;DR: Based on the systolic array approach, new designs of special-purpose devices for filtering, correlation, convolution, and discrete Fourier transform are proposed and discussed and it is argued that because of high degrees of simplicity, regularity and concurrency inherent to these designs, their VLSI implementation will be cost effective.
Abstract: Based on the systolic array approach, new designs of special-purpose devices for filtering, correlation, convolution, and discrete Fourier transform are proposed and discussed. It is argued that because of high degrees of simplicity, regularity and concurrency inherent to these designs, their VLSI implementation will be cost effective.

81 citations


Journal ArticleDOI
TL;DR: It is shown that communication considerations alone dictate that any VLSI design for computing the 2-bit product of two n-bit integers must satisfy the constraint AT-AT-2/64.
Abstract: The need to transfer information between processing elements can be a major factor in determining the performance of a VLSI circuit. We show that communication considerations alone dictate that any VLSI design for computing the 2n-bit product of two n-bit integers must satisfy the constraint AT2 ≥ n2/64 where A is the area of the chip and T is the time required to perform the computation. This same tradeoff applies to circuits which can shift n-bit words through n different positions.

80 citations


Journal ArticleDOI
B.M. Welch1, Yie-Der Shen1, R. Zucca1, R.C. Eden1, S.I. Long1 
TL;DR: In this article, a planar GaAs integrated circuit (IC) fabrication technology capable of LSI complexity has been developed, which utilizes Schottky-diode FET logic (SDFL) incorporating both high-speed switching diodes and 1-µ m GaAs MESFET's.
Abstract: A planar GaAs integrated circuit (IC) fabrication technology capable of LSI complexity has been developed. The circuit and fabrication approaches were chosen to satisfy LSI requirements for high yield, high density, and low power. This technology utilizes Schottky-diode FET logic (SDFL) incorporating both high-speed switching diodes and 1-µ m GaAs MESFET's. Circuits are fabricated directly on semi-insulating GaAs using multiple localized implantations. Rapid progress in the development of this technology has already led to the successful demonstration of high-speed ( \tau_{d} \sim 100 ps) low-power (∼500 µW/gate) GaAs MSI (∼60-100 gates) circuits. Extension of the current MSI technology to the LSI/VLSI domain will depend critically on device yield which will be dictated by the GaAs material properties and by the fabrication processes used. The purpose of this paper is to describe a GaAs IC process technology which combines advanced planar device and multilevel interconnect structures with several LSI compatible processes including multiple localized ion implantations, reduction photolithography, plasma etching, reactive ion etching, and ion milling.

Journal ArticleDOI
TL;DR: A rapid and systematic method for performing chip layout of VLSI circuits is described, which utilizes the configuration of a matrix composed of intersecting rows and columns to provide transistor placement and interconnections.
Abstract: A rapid and systematic method for performing chip layout of VLSI circuits is described. This method utilizes the configuration of a matrix composed of interacting rows and columns to provide transistor placement and interconnections. This structure, which is orderly and regular, gives high device-packing density and allows ease of checking for layout errors. Resulting layouts may be updated to new design rules automatically. This method has been used in the layout of a 20 000-transistor section of a VLSI circuit.

Journal ArticleDOI
TL;DR: There are significant problems in using some conventional fault-tolerant techniques in VLSI implementations for general purpose computers; consequently, modified approaches must be investigated.
Abstract: The construction of computer systems containing integrated circuit logic components with very large scale integration (VLSI), that is, many thousands of gates, is inevitable. Such levels of integration have already been achieved in memory components. There are significant problems in using some conventional fault-tolerant techniques in VLSI implementations for general purpose computers; consequently, modified approaches must be investigated.

Journal ArticleDOI
Clark1
TL;DR: Emphasizing ease of scaling and sharing of design tools, a new approach to VLSI systems design may deliver inexpensive specialized hardware.
Abstract: Emphasizing ease of scaling and sharing of design tools, a new approach to VLSI systems design may deliver inexpensive specialized hardware.


Proceedings ArticleDOI
23 Jun 1980
TL;DR: An investigation into the feasibility of logic synthesis in this new context is outlined which will produce a naive implementation automatically from a functional specification, and then will interact with the designer, allowing him to evaluate it with respect to these many factors, and to improve it incrementally by applying local transformations until it is acceptable for manufacture.
Abstract: Despite many attempts to generate hardware implementations automatically from functional specifications, the literature does not record any commercial success. Previous efforts have dealt primarily with technology-independent primitives and have emphasized circuit minimization. However, larger scales of integration have made other design requirements and technology restrictions as important as circuit count, and have increased the cost of making an engineering change. Thus it is becoming increasingly important to insure that initial chip designs are correct. This paper outlines an investigation into the feasibility of logic synthesis in this new context. A system is described which will produce a naive implementation automatically from a functional specification, and then will interact with the designer, allowing him to evaluate it with respect to these many factors, and to improve it incrementally by applying local transformations until it is acceptable for manufacture. The use of simple local transformations will insure correct implementations, will isolate technology-specific data, and will allow the total process to be applied to larger VLSI designs. This approach has been tested on the design of a single chip with encouraging results. A prototype synthesis system is now being used to perform further experiments.

Journal ArticleDOI
TL;DR: In this paper, a single-chip VLSI echo canceler has been fabricated in NMOS(N-channel metaloxide semiconductor), which has a 128-tap (16-ms) delay line and a white-noise convergence rate of 70 dB/s.
Abstract: A single-chip VLSI (very large-scale integration) echo canceler has been fabricated in NMOS(N-channel metal-oxide semiconductor). The canceler has a 128-tap (16-ms) delay line and a white-noise convergence rate of 70 dB/s. The chip measures 313 by 356 mils and contains 35,000 devices.

Journal ArticleDOI
TL;DR: It is concluded that a viable modular building block for the next generation of computing systems will be a self-contained computer on a single chip.
Abstract: In the mid 1980's it will be possible to put a million devices (transistors or active MOS gate electrodes) onto a single silicon chip. General trends in the evolution of silicon integrated circuits are reviewed and design constraints for emerging VLSI circuits are analyzed. Desirable architectural features in modern computers are then discussed and consequences for an implementation with large-scale integrated circuits are investigated. The resulting recommended processor design includes features such as an on-chip memory hierarchy, multiple homogeneous caches for enhanced execution parallelism, support for complex data structures and high-level languages, a flexible instruction set, and communication hardware. It is concluded that a viable modular building block for the next generation of computing systems will be a self-contained computer on a single chip. A tentative allocation of the one milion transistors to the various functional blocks is given, and the result is a memory intensive design.

01 Jul 1980
TL;DR: Based on the systolic array approach, new designs of special-purpose devices for filtering, correlation, convolution, and discrete Fourier transform are proposed and discussed and it is argued that because of high degrees of simplicity, regularity and concurrency inherent to these designs, their VLSI implementation will be cost effective.
Abstract: : Based on the systolic array approach, new designs of special-purpose devices for filtering, correlation, convolution, and discrete Fourier transform are proposed and discussed. It is argued that because of high degrees of simplicity, regularity and concurrency inherent to these designs, their VLSI implementation will be cost effective. (Author)

Proceedings ArticleDOI
06 May 1980
TL;DR: In this paper, the authors identify important steps in the design of a special purpose VLSI chip, and argue that the most crucial step is the implementation of the underlying algorithm, which determines the degree of parallelism and pipelining that is possible.
Abstract: This paper identifies important steps in the design of a special purpose VLSI chip, and argues that the most crucial step is the design of the underlying algorithm. Because the algorithm determines the degree of parallelism and pipelining that is possible, it largely determines the performance of the chip. Furthermore, if the underlying algorithm has the right properties such as modularity and regularity, then the rest of the design should be routine and thus take little effort. These claims are supported by a concrete example—the design of an efficient pattern matching chip, which has been fabricated for testing.

Journal ArticleDOI
TL;DR: It is concluded that a viable modular building block for the next generation of computing systems will be a self-contained computer on a single chip.
Abstract: In the mid 1980's it will be possible to put a million devices (transistors or active MOS gate electrodes) onto a single silicon chip. General trends in the evolution of silicon integrated circuits are reviewed and design constraints for emeging VLSI circuits are analyzed. Desirable architectural features in modem computers are then discussed and consequences for an implementation with large-scale integrated circuits are investigated. The resulting recommended processor design includes features such as an on-chip memory hierarchy, multiple homogeneous caches for enhanced execution parallelism, support for complex data structures and high-level languages, a flexible instruction set, and communication hardware. It is concluded that a viable modular building block for the next generation of computing systems will be a self-contained computer on a single chip. A tentative allocation of the one million transistors to the various functional blocks is given, and the result is a memory intensive design.

Proceedings ArticleDOI
Y.W. Sing1, B. Sudlow
01 Jan 1980
TL;DR: In this article, a simple closed form expression for short channel MOS transistor substrate current was proposed based on the physical operating principle of impact ionization, as well as the electric field dependence on drain and gate voltage.
Abstract: Some VLSI design constraints due to substrate current will be discussed and a simple closed form expression for short channel MOS transistor substrate current is proposed. This model is based on the physical operating principle of impact ionization, as well as the electric field dependence on drain and gate voltage. By using this model, the calculated substrate current of a transistor with L eff ≃ 1.5 µm was found to be within 10% of measured values over the operating range of interest. In addition, this model also correctly predicts parasitic bipolar breakdown phenomenon as a function of gate voltage. Because of its simplicity, the model has been easily implemented into a computer-aided circuit analysis program to simulate the actual circuit with very little increase in execution time.

Proceedings ArticleDOI
Vishwani D. Agrawal1, Ajoy K. Bose, P. Kozak, H. N. Nham, E. Pacas-Skewes 
23 Jun 1980
TL;DR: The Mixed-Mode Simulator allows different elements of a circuit to be modeled and simulated at different levels of detail and is being used on production LSI chips and its performance is discussed.
Abstract: To provide flexibility and efficiency in logic and timing verification of MOS VLSI circuits, it is desirable that various portions of a circuit can be described and simulated at appropriate levels of detail. Such a capability is provided by the Mixed-Mode Simulator described here. This simulator allows different elements of a circuit to be modeled and simulated at different levels of detail. The modeling levels are MOS transistor level, logic gate level and functional level. The simulation levels are timing, multiple delay and unit delay. The simulator is being used on production LSI chips and its performance is discussed.


Journal ArticleDOI
TL;DR: This note will develop a lower bound on the area-time complexity of binary addition, using very similar models of VLSI chips to find bounds on the complexity of various computations such as multiplication and discrete Fourier transformation.

17 Apr 1980
TL;DR: A statistical study of the components on VLSI chips is presented, and an algorithm for solving the 'rectangle intersection' problem that arises in design rule checkers is presented.
Abstract: : This paper presents a statistical study of the components on VLSI chips. We examine the size and shape of components, and their placement over the chip area. The data is useful for building efficient VLSI design tools: the form of the distribution shows that some simple strategies can lead to efficient algorithms, and the parameters of the distribution aid in choosing program parameters. To illustrate the application of the statistics to VLSI design tasks, we present an algorithm for solving the 'rectangle intersection' problem that arises in design rule checkers. (Author)

Journal ArticleDOI
D. Takacs1, W. Muller, U. Schwabe
TL;DR: In this article, test patterns and measurement techniques for automatic electrical measurements of misalignments and feature sizes have been developed for the control of an MOS Si2-gate process using these methods, correlations between the electrically relevant device parameters and the feature sizes are obtained.
Abstract: The reduced device dimensions of VLSI circuits resulting from improved lithographic techniques require very careful control of the feature sizes during the production process. For this purpose, test patterns and measurement techniques for automatic electrical measurements of misalignments and feature sizes have been developed for the control of an MOS Si2-gate process. Using these methods, correlations between the electrically relevant device parameters and the feature sizes are obtained. A sensitivity analysis for the threshold voltage has been made. It was found that for the technology under consideration, the variation of the feature sizes predominates over the influences of all other technological parameters at transistor lengths of 1-2 µm.

01 Jun 1980
TL;DR: Current methods of designing Very Large Scale Integrated (VLSI) chips do not insure that the chips will perform correctly when manufactured, so some better method is needed to catch all of the errors.
Abstract: : Current methods of designing Very Large Scale Integrated (VLSI) chips do not insure that the chips will perform correctly when manufactured. Because the turnaround time on chip fabrication varies from a few weeks to a few months, a scheme other than try it and see if it works is needed. Checking of chips by hand simulation and visual inspection of checkplots will not catch all of the errors. In addition, the number of transistors per chip is likely to increase from ten thousand to over a million in the next few years. This increase in complexity precludes any manual verification methods; some better method is needed. A series of programs that use the actual mask descriptions for input are described. These programs perform various levels of checks on the masks, yielding files suitable for simulation. Some of the checks are the usual 'design rule' checks of looking for minimum line widths and adequate spacing between wires. However, there are many more constraints in VLSI circuits than are expressed by usual design rules. The programs check these constraints using the mask descriptions as input. All of the errors mentioned so far can be classified as syntactic errors; in addition, certain errors are detected. The detection of semantic errors requires various levels of simulation. The input to the simulators is derived from the artwork.

ReportDOI
31 Mar 1980
TL;DR: The objective of the Restructurable Very Large Scale Integration (RVLSI) Program is to develop and demonstrate techniques which will make possible integration of large systems as single-package modules.
Abstract: : The objective of the Restructurable Very Large Scale Integration (RVLSI) Program is to develop and demonstrate techniques which will make possible integration of large systems as single-package modules. We are developing techniques for restructuring large-area IC chips after fabrication in order to provide access for testing, perform defect avoidance and customization, and reconfigure a system while it is being used. The DARPA-sponsored program is focused on development or architectural concepts for data- and signal-processing systems for RVLSI implementation, development of design aids for unique RVLSI design problems, and development of test techniques suitable for RVLSI applications. An overview of the goals and proposed techniques is given in Sec. II. In Sec. III the functional requirements on programmable connections or links are presented and three types of links are described and compared. In the near term the emphasis will be on laser programmed links and links made from standard logic circuitry; a longer-term goal is development of an electrically programmable nonvolatile link. In Sec. IV we describe a hardware description language designed for efficient description of hierarchical and iterative structures of digital circuits. Since each RVLSI chip may have a different wiring configuration, complete automation of the signal routing process is essential. Solutions for this problem are presented in Sec. IV. Results of an investigation of mapping a regular locally connected array of processing elements onto a physical array with defective elements are presented in Sec. V. An integrator for a spread-spectrum packet radio receiver has been chosen for a first implementation.

Journal ArticleDOI
TL;DR: In this article, a 1-µm VLSI process was developed for the fabrication of bipolar circuits, which employs electron-beam slicing writing, plasma processing, ion implantation, and low-temperature oxidation/annealing to fabricate bipolar device structures.
Abstract: A 1-µm VLSI process technology has been developed for the fabrication of bipolar circuits. The process employs electron-beam slicing writing, plasma processing, ion implantation, and low-temperature oxidation/annealing to fabricate bipolar device structures with a minimum feature size of 0.9 µm. Both nonisolated I2L and isolated Schottky transistor logic (STL) devices and circuits have been fabricated with this process technology. The primary demonstration vehicle is a scaled LSI, I2L, 4-bit processor chip (SBP0400) with a minimum feature size of 1 µm. Scaled SPB0400's have been fabricated that operate at clock speeds 3 × higher than their full-size counterparts at 50-mA chip current. Average propagation delay has been measured as a function of minimum feature size for both I2L and STL device designs. Power-delay products of 14 fJ for I2L and 30 fJ for STL have been measured.