scispace - formally typeset
Search or ask a question

Showing papers on "Very-large-scale integration published in 2020"


Journal ArticleDOI
TL;DR: A revised version of SFLL, namely SFLL-rem, is presented, that not only retains all security properties ofSFLL but also delivers resilience to all the state-of-the-art attacks SFLL can thwart, but also to the latest removal attacks that broke some SFLL instances.
Abstract: Logic locking is a holistic solution to counter manufacturing threats, such as intellectual property (IP) piracy and overbuilding at the hardware level. However, years of research has exposed various flaws in locking, including a Boolean satisfiability (SAT)-based attack. Consequently, several SAT-resilient locking techniques, such as SARLock, Anti-SAT, and SFLL have been proposed, although certain instances of them have also been broken by a class of attacks, called removal attack. In this article, we approach logic locking by leveraging well-known principles from very large-scale integration (VLSI) testing and elicit logic locking properties that dictate the resilience of a locking technique against different attacks. We present a revised version of SFLL, namely SFLL-rem, that not only retains all security properties of SFLL, delivering resilience to all the state-of-the-art attacks SFLL can thwart, but also to the latest removal attacks that broke some SFLL instances. Further, we develop a security-aware CAD framework integrated with industry tools that incurs only −1.5%, 0%, and 4.13% overhead for power, performance, and area, respectively. We demonstrate a silicon implementation of SFLL-rem on ARM Cortex-M0 microprocessor in 65 nm. Moreover, we provide a framework for an SoC designer to customize logic locking based on the SoC blocks and their threat models; this is illustrated by locking a multimillion-gate SoC provided by DARPA, and taking the SoC all the way to GDSII layout.

54 citations


Proceedings ArticleDOI
01 Aug 2020
TL;DR: In this paper, the VLSI implementation of HAAR wavelet-based image compression is proposed and designed and provides a hardware-free architecture with low cost.
Abstract: The Discrete Wavelet transform is one of the best tools for signal and data analysis, It requires efficient hardware implementation in the real-time applications. The submissions established in the field of imaging necessitates compacted architecture. In DWT discrete sampling is accomplished for the wavelets. In this paper, the VLSI implementation of HAAR wavelet-based image compression is proposed and designed. HAAR wavelet transform is one of the easiest methods for image compression because it has coefficients as either 1 or −1. In this work software alone is used for the compression together with optimizing it with a continuous optimization algorithm and provides a hardware-free architecture with low cost. The VHDL work is carried out in Xilinx Platform and provides a truncated power architecture for a concrete application. The same VHDL architecture can also be instigated in FPGA which will harvest hardware effectual compromising outcomes.

47 citations


Journal ArticleDOI
TL;DR: This work reviews recent research applying techniques such as deep convolutional neural networks and graph-based neural networks in the areas of automatic design space exploration, power analysis, VLSI physical design, and analog design.
Abstract: Recent advancements in machine learning provide an opportunity to transform chip design workflows. We review recent research applying techniques such as deep convolutional neural networks and graph-based neural networks in the areas of automatic design space exploration, power analysis, VLSI physical design, and analog design. We also present a future vision of an AI-assisted automated chip design workflow to aid designer productivity and automate optimization tasks.

29 citations


Proceedings ArticleDOI
02 Nov 2020
TL;DR: This work proposes a machine learning-based routing-free crosstalk prediction framework that can instantly classify more than 70% of crosStalk-critical nets after placement with a false-positive rate of less than 2%.
Abstract: Interconnect spacing is getting increasingly smaller in advanced technology nodes, which adversely increases the capacitive coupling of adjacent interconnect wires. It makes crosstalk a significant contributor to signal integrity and timing, and it is now imperative to prevent crosstalk-induced noise and delay issues in the earlier stages of VLSI design flow. Nonetheless, since the crosstalk effect depends primarily on the switching of neighboring nets, accurate crosstalk evaluation is only viable at the late stages of design flow with routing information available, e.g., after detailed routing. There have also been previous efforts in early-stage crosstalk prediction, but they mostly rely on time-expensive trial routing. In this work, we propose a machine learning-based routing-free crosstalk prediction framework. Given a placement, we identify routing and net topology-related features, along with electrical and logical features, which affect crosstalk-induced noise and delay. We then employ machine learning techniques to train the crosstalk prediction models, which can be used to identify crosstalk-critical nets in placement stages. Experimental results demonstrate that the proposed method can instantly classify more than 70% of crosstalk-critical nets after placement with a false-positive rate of less than 2%.

28 citations


Journal ArticleDOI
TL;DR: Asynchronous logic gates greatly reduce the complexity of the clock network in large-scale RSFQ circuits, thereby alleviating certain timing issues and reducing the required bias currents.
Abstract: Among the major issues in modern large-scale rapid single-flux quantum (RSFQ) circuits are the complexity of the clock network, tight timing tolerances, poor applicability of existing CMOS-based design algorithms, and extremely deep pipelines, which reduce the effective clock frequency. In this article, asynchronous dynamic single-flux quantum majority gates are proposed to solve some of these problems. The proposed logic gates exhibit high bias margins and do not require significant area or a large number of Josephson junctions as compared to existing RSFQ logic gates. These gates exhibit a tradeoff among the input skew tolerance, clock frequency, and bias margins. Asynchronous logic gates greatly reduce the complexity of the clock network in large-scale RSFQ circuits, thereby alleviating certain timing issues and reducing the required bias currents. Furthermore, asynchronous logic allows existing design algorithms to utilize CMOS approaches for synthesis, verification, and testability. The adoption of majority logic in complex RSFQ circuits also reduces the pipeline depth, enabling higher clock speeds in very large scale integration RSFQ circuits.

24 citations


Journal ArticleDOI
TL;DR: This paper reviews the application of several SI techniques to the VLSI routing filed, and three classic routing problems are described: Steiner tree construction, global routing and detailed routing.
Abstract: Routing is a complex and critical stage in the physical design of Very Large Scale Integration (VLSI), minimizing interconnect length and delay to optimize overall chip performance. With the rapid development of modern technology, VLSI routing faces enormous challenges such as large delay, high congestion, and high-power consumption. As a rising optimization method, Swarm Intelligence (SI) inspired from collective intelligence behaviors through cooperation or interaction with the environment provides effectiveness and robustness for solving NP-hard problems. Many researchers have consequently used SI techniques to solve routing-related problems in VLSI. This paper reviews the application of several SI techniques to the VLSI routing filed. Firstly, five commonly used SI techniques and related models, and three classic routing problems are described: Steiner tree construction, global routing and detailed routing. Then an overview of the current state of this field is given according to the above categories, and the survey offers informative discussions from five aspects: 1) Steiner minimum tree construction; 2) wirelength-driven routing; 3) obstacle-avoiding routing; 4) timing-driven routing; 5) power-driven routing. Finally, under three new technology models: X-architecture, multiple dynamic supply voltage and via-pillar, the future development trends are pointed as follows: 1) suggesting suitable SI techniques to specific routing problems for advanced technology models; 2) exploring new and available SI techniques that have not yet been applied to VLSI routing.

23 citations


Journal ArticleDOI
TL;DR: A novel logic-in-memory (LIM) architecture of magnetic arithmetic logic unit (P-MALU) based on hybrid STT-MTJ/CMOS circuits is proposed which is superior than other two ALU designs in terms of power dissipation, delay and device count.
Abstract: One of the major concern for CMOS technology is the increase in power dissipation as the technology node lowers down to deep submicron region. Magnetic tunnel junction (MTJ) working on Spin transfer torque (STT) switching mechanism is recognized as one of the most promising spintronic device for post CMOS era due to its non-volatility, high speed, high endurance, CMOS compatibility and mainly the low power dissipation which can offer the solutions for the problems posed by existing CMOS technology. We have proposed a novel logic-in-memory (LIM) architecture of magnetic arithmetic logic unit (P-MALU) based on hybrid STT-MTJ/CMOS circuits. Simulation results reveal that there is significant reduction in the total power dissipation and transistor count of arithmetic unit by 28.44% and 29.16% compared to double pass transistor logic based clocked CMOS ALU design (DPTL-C2MOS-ALU), while 58.87% and 45.16% to modified magnetic arithmetic logic unit (M-MALU) respectively. Reduction in average power dissipation for logical unit is 37.61% and 52.55% along with 47.22% and 42.42% fewer transistors than DPTL-C2MOS-ALU and M-MALU design respectively. Monte-Carlo(MC) simulation is then performed by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ, to study the behavior of DPTL-C2MOS-ALU, M-MALU and P-MALU designs in terms of power dissipation. All the simulation results reveal that the P-MALU is superior than other two ALU designs in terms of power dissipation, delay and device count. Further, the P-MALU circuit is extended for 4-bits arithmetic operations. Electrical simulations are performed to verify the functionality of the design for higher bit operations which demonstrates the feasibility of the proposed design in VLSI circuits.

23 citations


Journal ArticleDOI
TL;DR: Three types of subproblems in Steiner tree construction and three types of GR methods are systematically dissected to understand GR and SMT problems and to learn the available solutions.
Abstract: Global Routing (GR) is a crucial and complex stage in the Very Large-Scale Integration (VLSI) design, which minimizes interconnect wirelength and delay to optimize the overall chip performance. Steiner tree construction is one of the basic models of VLSI physical design, which is usually used in the initial topology creation for noncritical nets in physical design. In a GR process, a Steiner Minimum Tree (SMT) algorithm can be invoked millions of times, which means that SMT algorithm has great significance for the final quality of GR. Some of the research works are surveyed in this paper to understand GR and SMT problems and to learn the available solutions. Firstly, we systematically dissect three types of subproblems in Steiner tree construction and three types of GR methods. Then, we investigate the recent progress under two new technology models. Finally, the survey concludes with a summary of possible future research directions.

21 citations


01 Jan 2020
TL;DR: The carry select adder present in this paper is suitable for the VLSI implementation and is estimated with static and compact carry look ahead adder with a simple select circuit.
Abstract: In all the arithmetic operations, addition is one of the most important and initial operation used everywhere. The operation is performed by many adders present in the digital world. These adders gives us carries with preferred delay and power. The three main features like structure, logic used and the compact circuit layout helps to design a better adder. In this paper the CSA adder is built or designed using the compact carry look ahead adder which is the vital component. The adder CSA is designed using the software tool called cadence with the FinFET technology. This technology is the fastest and much used in the present world for designing the VLSI circuits. Cadence software is more sophisticated and advanced tool which provides us the results in accurate values. The carry select adder which is represented is simulated using the Cadence tool and designed with FinFET transistors of different specifications. The FinFET technology used in this paper is 18nm. The carry select adder present in this paper is suitable for the VLSI implementation. The carry select adder is estimated with static and compact carry look ahead adder with a simple select circuit. These adders are used in electrical industries for fast and exact results in the large circuits. The FinFET based CSA is designed and parameters are calculated in this paper.

18 citations


Journal ArticleDOI
TL;DR: An innovative configuration namely Tetramorphic (TM) is contrived for the bundle of MWCNTs with four different diameters which will offer the size shrinkage feature in a substantial manner and the propagation delay results for local, semi-global and global level interconnect are obtained.
Abstract: Having a 1D material like Multiwall Carbon Nanotube (MWCNT) as a potential candidate for high speed Very Large Scale Integration (VLSI) interconnect creates a good scope to reduce the delay by estimating the parasitic elements i.e. Resistance ( $R$ ), Inductance ( $L$ ) and Capacitance ( $C$ ) properly. We have contrived an innovative configuration namely Tetramorphic (TM) for the bundle of MWCNTs with four different diameters. We have focused on 45 nm, 22 nm, 11 nm and 7 nm technology nodes to justify the novelty of our proposed configuration over the existing MWCNT bundle configurations. Having the parasitic $RLC$ elements for a specific technology node, the diameter optimization took place in this work. Subsequently, we obtain the propagation delay results for local, semi-global and global level interconnect. Finally, we compare the results with the other existing configuration to show the supremacy of our introduced configuration for MWCNT bundle to explore high speed VLSI interconnect and represent crosstalk delay and power dissipation. Moreover, this configuration is highly dense which will offer the size shrinkage feature in a substantial manner.

17 citations


Journal ArticleDOI
TL;DR: This work proposes Efficient VLSI design in terms of Area, Delay, Power and PDP (Power delay product) and reports a delay aware signal distribution methodology applicable for any type of QCA logic circuit design.

Proceedings ArticleDOI
16 Jun 2020
TL;DR: Back-end-of-line (BEOL) integration of multi-tier logic and memory established within a commercial foundry is reported, enabled by a low-temperature BEOL-compatible complementary carbon nanotube (CNT) field-effect transistor (CNFET) logic technology, alongside a BE OL compatible Resistive RAM (RRAM) technology.
Abstract: The inevitable slowing of two-dimensional scaling is motivating efforts to continue scaling along a new physical axis: the 3 rd dimension. Here we report back-end-of-line (BEOL) integration of multi-tier logic and memory established within a commercial foundry. This is enabled by a low-temperature BEOL-compatible complementary carbon nanotube (CNT) field-effect transistor (CNFET) logic technology, alongside a BEOL-compatible Resistive RAM (RRAM) technology. All vertical layers are fabricated sequentially over the same starting substrate, using conventional BEOL nano-scale inter-layer vias (ILVs) as vertical interconnects (e.g., monolithic 3D integration, rather than chip-stacking and bonding). In addition, we develop the entire VLSI design infrastructure required for a foundry technology offering, including an industry-practice monolithic 3D process design kit (PDK) as well as a complete monolithic 3D standard cell library. The initial foundry process integrates 4 device tiers (2 tiers of complementary CNFET logic and 2 tiers of RRAM memory) with 15 metal layers at a ~130 nm technology node. We fabricate and experimentally validate the standard cell library across all monolithic 3D tiers, as well as a range of sub-systems including memories (BEOL SRAM, 1T1R memory arrays) as well as logic (including the compute core of a 16-bit microprocessor) - all of which is fabricated in the foundry within the BEOL interconnect stack. All fabrication is VLSI-compatible and leverages existing silicon CMOS infrastructure, and the entire design flow is compatible with existing commercial electronic design automation tools.

Proceedings ArticleDOI
05 Nov 2020
TL;DR: Several area and power efficient splitters are proposed for large scale SFQ integrated circuits for driving long and short interconnect in VLSI complexity SFQ systems.
Abstract: On-chip signal routing has become an issue of growing importance in modern VLSI complexity single flux quantum (SFQ) systems. In this paper, different routing methods for these systems are described. The routing methods include either passive transmission lines (PTLs) or Josephson transmission lines (JTLs) as interconnects. Driving multiple SFQ gates is also a challenging issue in automated layout and clock tree synthesis (CTS) due to the limited fanout of SFQ gates. To support multiple fanout, splitters are used to distribute multiple SFQ pulses. These splitters require significant area, delay, and power. In this paper, several area and power efficient splitters are proposed for large scale SFQ integrated circuits. A primary issue within a long SFQ interconnect is resonance effects due to the imperfect match between the PTLs and Josephson junctions. A repeater insertion methodology for long interconnect to reduce and manage these resonance effects is also described. Summarizing, guidelines and tradeoffs appropriate for automated layout and synthesis are described for driving long and short interconnect in VLSI complexity SFQ systems.

Journal ArticleDOI
TL;DR: An efficient VLSI routing algorithm employing novel discrete particle swarm optimization (PSO) and multi-stage transformation is proposed to build two types of SMT, including X-architecture Steiner minimal tree and rectilinear Steiners minimal tree.
Abstract: For routing industrial circuits, the Steiner minimal tree (SMT) model can be applied in different routing problems, such as wirelength optimization, congestion reduction, and delay optimization. In this paper, an efficient VLSI routing algorithm employing novel discrete particle swarm optimization (PSO) and multi-stage transformation is proposed to build two types of SMT, including X-architecture Steiner minimal tree and rectilinear Steiner minimal tree. Firstly, to simultaneously handle two types of SMT problems, an effective encoding strategy is proposed to be more suitable for PSO and thus it can overcome the difficulty of designing different algorithms for different routing architectures. Secondly, a multi-stage transformation strategy is presented to expand the search space of the proposed algorithm and accelerate the convergence speed of the proposed algorithm. Various combinations of multi-stage transformation strategies have been tested to highlight the best combination. Furthermore, the various genetic operators combined with union-find data structure strategy are proposed to construct the novel and effective discrete particle update formula. Experimental simulation results on industrial circuits show that the proposed algorithm can get the best solutions among the existing algorithms.

Posted Content
TL;DR: A novel supervised learning algorithm for SNNs based on temporal coding is proposed, designed to facilitate analog VLSI implementations with analog resistive memory, by which ultrahigh energy efficiency can be achieved.
Abstract: Spiking neural networks (SNNs) are brain-inspired mathematical models with the ability to process information in the form of spikes. SNNs are expected to provide not only new machine-learning algorithms, but also energy-efficient computational models when implemented in VLSI circuits. In this paper, we propose a novel supervised learning algorithm for SNNs based on temporal coding. A spiking neuron in this algorithm is designed to facilitate analog VLSI implementations with analog resistive memory, by which ultra-high energy efficiency can be achieved. We also propose several techniques to improve the performance on a recognition task, and show that the classification accuracy of the proposed algorithm is as high as that of the state-of-the-art temporal coding SNN algorithms on the MNIST dataset. Finally, we discuss the robustness of the proposed SNNs against variations that arise from the device manufacturing process and are unavoidable in analog VLSI implementation. We also propose a technique to suppress the effects of variations in the manufacturing process on the recognition performance.

Proceedings ArticleDOI
01 Nov 2020
TL;DR: In this article, a new simulation tool, Rad-Ray, has been developed to simulate and model the passage of heavy ion into the silicon matter of modern Integrated Circuit and predict the transient voltage pulse taking into account the physical description of the design.
Abstract: As today’s process technologies continuously scale down, circuits become increasingly more vulnerable to radiation-induced soft errors in nanoscale VLSI technologies. The reduction of node capacitance and supply voltages coupled with increasingly denser chips are raising soft error rates and making them an important design issue. This research work is focused on the development of design techniques for high-reliability modern VLSI technologies, focusing mainly on Radiation-induced Single Event Transient. In this work, we evaluate the complete life-cycle of the SET pulse from the generation to the mitigation. A new simulation tool, Rad-Ray, has been developed to simulate and model the passage of heavy ion into the silicon matter of modern Integrated Circuit and predict the transient voltage pulse taking into account the physical description of the design. An analysis and mitigation tool has been developed to evaluate the propagation of the predicted SET pulses within the circuit and apply a selective mitigation technique to the sensitive nodes of the circuit. The analysis and mitigation tools have been applied to many industrial projects as well as the EUCLID space mission project, including more than ten modules. The obtained results demonstrated the effectiveness of the proposed tools.

Journal ArticleDOI
TL;DR: The experimental results shows that the proposed designed circuit achieves better performance compared with the existing reversible logic circuits such as Feynman gate basedFA, Peres gate based FA, TSG based FA in terms of average power, static power dissipation, static current and area.

Journal ArticleDOI
TL;DR: A novel approach of DWT is presented by replacing conventionalAdders and multipliers with XOR-MUX adders and Truncations multipliers thereby reducing the 2n logic size to n-size logic.

Proceedings ArticleDOI
01 Sep 2020
TL;DR: During this work, the on-chip variation method was briefly addressed with the aid of CMOS technology.
Abstract: Present digital world anticipates the high performance, low cost, and low power consumption in the semiconductor industry accompanied with a rapid growth in technology. Nowadays, the economy relies on the chip system, so that the semiconductor business enters the innovation in the transistor at each hub and further this innovation comes with a lot of difficulties like reduced quality, manufacturing and multi-faceted planning. Variety with primarily random and organized combinations is one of the essential challenges in assembling the boundaries. One of the most important differences observed from these variants is on-chip variation. During this work, the on-chip variation method was briefly addressed with the aid of CMOS technology.

Journal ArticleDOI
21 Aug 2020-Sensors
TL;DR: A noise-aware range kernel, which estimates noise using an intensity difference-based image noise model and dynamically adjusts weights according to the estimated noise, in order to alleviate the quality degradation of bilateral filters by noise is proposed.
Abstract: The range kernel of bilateral filter degrades image quality unintentionally in real environments because the pixel intensity varies randomly due to the noise that is generated in image sensors. Furthermore, the range kernel increases the complexity due to the comparisons with neighboring pixels and the multiplications with the corresponding weights. In this paper, we propose a noise-aware range kernel, which estimates noise using an intensity difference-based image noise model and dynamically adjusts weights according to the estimated noise, in order to alleviate the quality degradation of bilateral filters by noise. In addition, to significantly reduce the complexity, an approximation scheme is introduced, which converts the proposed noise-aware range kernel into a binary kernel while using the statistical hypothesis test method. Finally, blue a fully parallelized and pipelined very-large-scale integration (VLSI) architecture of a noise-aware bilateral filter (NABF) that is based on the proposed binary range kernel is presented, which was successfully implemented in field-programmable gate array (FPGA). The experimental results show that the proposed NABF is more robust to noise than the conventional bilateral filter under various noise conditions. Furthermore, the proposed VLSI design of the NABF achieves 10.5 and 95.7 times higher throughput and uses 63.6–97.5% less internal memory than state-of-the-art bilateral filter designs.

Proceedings ArticleDOI
03 Dec 2020
TL;DR: In this article, a 4-bit and an 8-bit Manchester carry chain adder (MCC) using domino logic design consumes less power and reduction in the delay of the proposed circuit compared with the previous architecture.
Abstract: Designers primary goal is to develop the Adder cell with improved performance viz. speed, fixed rise and fall time, as it the fundamental block in VLSI design process. The dynamic logic circuits are far better than the static logic circuits because it consumes less power and speed performance also increased. But, cascading of several blocks in dynamic logic is found to be a wrong analysis. This drawback of increased complexity with mismatched cascading is overcome by using domino logic circuits. By using domino logic circuits, the reduction of noise margins and increase the speed performance of the circuit is achieved. In this paper, domino logic based Manchester carry chain adder (MCC) is designed using FinFET 18nm technology in Cadence virtuoso. It is noticed that 4-bit and an 8-bit Manchester Carry Chain Adder (MCC) using domino logic design consumes less power and reduction in the delay of the proposed circuit compared with the previous architecture. Implementation results reveal that the 4-Bit MCC Adder has delay of 79.45% less compared to the existed standard design and power consumption also reduced to 94.15%.

Proceedings ArticleDOI
09 Mar 2020
TL;DR: In this article, a deep learning-based framework is proposed to approximately predict the initial design of the power grid network, considering different reliability constraints, and the proposed framework reduces many iterative design steps and speeds up the total design cycle.
Abstract: With the increase in the complexity of chip designs, VLSI physical design has become a time-consuming task, which is an iterative design process. Power planning is that part of the floorplanning in VLSI physical design where power grid networks are designed in order to provide adequate power to all the underlying functional blocks. Power planning also requires multiple iterative steps to create the power grid network while satisfying the allowed worst-case IR drop and Electromigration (EM) margin. For the first time, this paper introduces Deep learning (DL)-based framework to approximately predict the initial design of the power grid network, considering different reliability constraints. The proposed framework reduces many iterative design steps and speeds up the total design cycle. Neural Network-based multi-target regression technique is used to create the DL model. Feature extraction is done, and training dataset is generated from the floorplans of some of the power grid designs extracted from IBM processor. The DL model is trained using the generated dataset. The proposed DL-based framework is validated using a new set of power grid specifications (obtained by perturbing the designs used in the training phase). The results show that the predicted power grid design is closer to the original design with minimal prediction error (~2%). The proposed DL- based approach also improves the design cycle time with a speedup of ~6x for standard power grid benchmarks.

Journal ArticleDOI
05 Feb 2020
TL;DR: In this work, a systematic prediction methodology to assess and improve the SET immunity of digital circuits is presented, and an analysis based on signal probability and pin assignment is proposed to achieve a more application-efficient SET-aware optimization of synthesized circuits.
Abstract: Due to the intrinsic masking effects of combinational circuits in digital designs, Single-Event Transient (SET) effects were considered irrelevant compared to the data rupture caused by Single-Event Upset (SEU) effects. However, the importance of considering SET in Very-Large-System-Integration (VLSI) circuits increases given the reduction of the transistor dimensions and the logic data path depth in advanced technology nodes. Accordingly, the threat of SET in electronics systems for space applications must be carefully addressed along with the SEU characterization. In this work, a systematic prediction methodology to assess and improve the SET immunity of digital circuits is presented. Further, the applicability to full-custom and cell-based design methodologies are discussed, and an analysis based on signal probability and pin assignment is proposed to achieve a more application-efficient SET-aware optimization of synthesized circuits. For instance, a SET-aware pin assignment can provide a reduction of 37% and 16% on the SET rate of a NOR gate for a Geostationary Orbit (GEO) and the International Space Station (ISS) orbit, respectively.

Journal ArticleDOI
TL;DR: A new technique for domino circuit is proposed to reduce the process variations and power dissipation with optimized delay for wide fan-in OR logic and can be used to design the low power VLSI circuits and deep submicron regime.
Abstract: In this work, a new technique for domino circuit is proposed to reduce the process variations and power dissipation with optimized delay for wide fan-in OR logic. Two methods are used to reduce both process variation and power dissipation at the same time. In first part, the keeper circuit has been redesigned to reduce the process variation with enhanced noise margin. And in second part, evaluation network has been redesigned to reduce the subthreshold leakage current at optimized delay. Thus, the proposed domino can be used to design the low power VLSI circuits and deep submicron regime. The simulation results show that this work exhibits about 64% and 30% process variations reduction in power, and 38% and 21% process variations reduction in delay for reported conventional domino and a simple approach for delay reduction domino respectively. Noise margin is also improved by 1.41 and 1.16 times compared to above said schemes respectively. All simulation results are obtained with Cadence Virtuoso environment using SPECTRE simulator for 45 nm CMOS technology.

Journal ArticleDOI
TL;DR: Circuit implementations of blind phase search carrier phase recovery (CPR) for M-QAM coherent optical receivers are presented and some BPS algorithm modifications necessary to obtain efficient VLSI circuits are highlighted.
Abstract: We present circuit implementations of blind phase search (BPS) carrier phase recovery (CPR) for M-QAM coherent optical receivers and highlight some BPS algorithm modifications necessary to obtain efficient VLSI circuits. In addition, we show how three key design parameters (input word length, number of test phases, and type and size of averaging window) affect the resulting implementation. To study design tradeoffs, we develop BPS CPR circuit netlists for a 32-GBaud system, using a 22-nm CMOS process technology: our implementations reach energy efficiencies of around 1 pJ/bit for 16QAM up to 3 pJ/bit for 256QAM, at an SNR penalty of approximately 0.25 dB at a BER of 10−2. Furthermore, we present a circuit implementation of pilot-symbol-aided CPR, reaching 0.38 pJ/bit and 0.34 pJ/bit for 16QAM and 256QAM, respectively, at a slightly higher SNR penalty. The two CPR methods are also evaluated in terms of silicon area and scaling to higher-order modulation formats.

Journal ArticleDOI
Aditya Mandloi1, Santosh Pawar
TL;DR: The pipelined APT-VDF is modified by developing a new Variable Block Sized Ternary Adder (VBS-TA) and a modified TERNary multiplier for the fast realization of the filter structure and the simulation results show that the proposed APT -VDF overtakes the existing VDFs in terms of delay, power and area utilization.

Proceedings ArticleDOI
15 Jun 2020
TL;DR: Implementing the GDI technique in designing the ALU results in low power consumption and the number of transistors it requires is much less, which result in reduced chip-area and power consumption - two of the most important parameters in digital VLSI design.
Abstract: In this paper, the design of an 8-bit Arithmetic Logic Unit (ALU) using Gate Diffusion Input (GDI) technique is proposed. Implementing the GDI technique in designing the ALU results in low power consumption and the number of transistors it requires is much less. Which result in reduced chip-area and power consumption - two of the most important parameters in digital VLSI design. In this design, 3T XOR is used in the full adder. Moreover, a novel 1-to-8 demultiplexer circuit has been used in the design as well. A considerable number of research papers are studied and compared various logic families and then finally designed an 8-bit ALU which can perform 8 different operations. The design is validated using the schematic editor-DHCH 3.5 and the simulation have been carried out using Xilinx ISE 14.7.

Proceedings ArticleDOI
01 Jan 2020
TL;DR: In this article, a heterogeneous OPC framework is proposed to assist mask layout optimization, which has the potential to be an alternative to existing EDA solutions, and preliminary results show the efficiency and effectiveness of proposed frameworks.
Abstract: VLSI mask optimization is one of the most critical stages in manufacturability aware design, which is costly due to the complicated mask optimization and lithography simulation. Recent researches have shown prominent advantages of machine learning techniques dealing with complicated and big data problems, which bring potential of dedicated machine learning solution for DFM problems and facilitate the VLSI design cycle. In this paper, we focus on a heterogeneous OPC framework that assists mask layout optimization. Preliminary results show the efficiency and effectiveness of proposed frameworks that have the potential to be alternatives to existing EDA solutions.

Journal ArticleDOI
Y. M. Aneesh1, B. Bindu1
TL;DR: In this article, a physics-based bias-dependent model is developed to determine the SET pulse width of a double-gate (DG) CMOS inverter with the heavy ion strike on OFF state NMOS.
Abstract: The single-event transients in MOSFETs due to heavy ion strikes introduce soft errors in sub-50 $nm$ CMOS VLSI circuits. These transients are easily captured and propagated in high-frequency CMOS VLSI circuits. The capture rate mainly depends on the single-event transient (SET) pulse width and the clock frequency of the circuits. An estimation of the SET pulse width through a physics-based model that considers the device electrostatics is necessary to predict and mitigate these soft errors in VLSI circuits. In this article, a physics-based bias-dependent model is developed to determine the SET pulse width of a double-gate (DG) CMOS inverter with the heavy-ion strike on OFF state NMOS. The output voltage perturbations due to ion strike in the CMOS inverter and the SET pulse width model are derived from the bias-dependent SET current model previously reported. The variations in the output voltage of the inverter and the pulse width obtained from the developed model for different Linear Energy Transfer (LET), supply bias, strike positions, device dimensions, and load capacitances are validated with TCAD mixed-mode simulations.

Journal ArticleDOI
TL;DR: A hybrid analog/digital very large-scale integration (VLSI) implementation of a spiking neural network with programmable synaptic weights was designed and it is possible to interface the device to a workstation or a microcontroller and explore the effect of different types of spike-timing dependent plasticity learning algorithms for updating the synaptic weights values in the CAM module.
Abstract: A hybrid analog/digital very large-scale integration (VLSI) implementation of a spiking neural network with programmable synaptic weights was designed. The synaptic weight values are stored in an a...