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VHDL

About: VHDL is a research topic. Over the lifetime, 8737 publications have been published within this topic receiving 73719 citations. The topic is also known as: Very High Speed Integrated Circuit Hardware Description Language & VHSIC Hardware Description Language.


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Journal ArticleDOI
TL;DR: The VHDL code is written for four bit parallel CRC and FPGA implementation of the code was done and the overall efficiency of the parallel CRC is found to improve.
Abstract: This paper presents a different approach to solve the parallel CRC circuit. The previous works have been studied. Certain drawbacks were observed in the previous works. Some authors had used Linear feedback shift registers to do serial implementation. This approach resulted in a circuit that was inefficient in terms of time utilization. Though some authors had used the concept of parallel CRC but there was scope for improvement. We have worked on the related issues and have proposed an efficient mechanism. We have developed the VHDL code using VHDL structural modelling. The work was also compared with existing models of parallel implementation of four bit CRC circuit. The code is written for four bit parallel CRC and FPGA implementation of the code was done. Comparing with existing work, the proposed model is more efficient in terms of hardware utilization. As the hardware utilization has been been done in an efficient way, the overall efficiency of the parallel CRC is found to improve.
Journal ArticleDOI
TL;DR: In this paper, efficient hardware implementation of R/B converters have been reported for the moduli set of (2n-1,2n, 2n+1), and performance parameters have been compared as a function of propagation delay, power consumption and FPGA resource utilization.
Proceedings ArticleDOI
19 Apr 2010
TL;DR: The framework consists of a generic controller circuit defined in VHDL that can be configured by the user according to the needs of the functional units and the I/O channel and supports the design of both stateless and stateful functional units.
Abstract: FPGAs make it practical to speed up a program by defining hardware functional units that perform calculations faster than can be achieved in software. Specialised digital circuits avoid the overhead of executing sequences of instructions, and they make available the massive parallelism of the components. The FPGA operates as a coprocessor controlled by a conventional computer. An application that combines software with hardware in this way needs an interface between a communications port to the processor and the signals connected to the functional units. We present a framework that supports the design of such systems. The framework consists of a generic controller circuit defined in VHDL that can be configured by the user according to the needs of the functional units and the I/O channel. The controller contains a register file and a pipelined programmable register transfer machine, and it supports the design of both stateless and stateful functional units. Two examples are described: the implementation of a set of basic stateless arithmetic functional units, and the implementation of a stateful algorithm that exploits circuit parallelism.
Proceedings ArticleDOI
07 Apr 1991
TL;DR: The authors present a novel architecture and its design for a real-time parallel array processor for high-speed digital signal processing applications that enhances the data throughput more than twofold over that of any of the current conventional architecture processors that are used in similar applications.
Abstract: The authors present a novel architecture and its design for a real-time parallel array processor for high-speed digital signal processing applications. The processor generates sequential output data from a stream of input data and a set of predetermined coefficients. The processor has been designed and functionally simulated by the VHSIC Hardware Description Language. The processor includes a pipelined array of multiplier-accumulator circuits which provide parallel operation to the processor. The processor does not use parallel operation for data input rates lower than the data processing rate, but the degree of parallelism is increased up to 3 for data input rates higher than the data processing rate. This increase in the degree of parallelism enhances the data throughput more than twofold over that of any of the current conventional architecture processors that are used in similar applications. >

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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202368
2022185
2021141
2020182
2019221
2018218