Voltage-controlled filter

About: Voltage-controlled filter is a research topic. Over the lifetime, 5514 publications have been published within this topic receiving 70872 citations. The topic is also known as: VCF.

Power line harmonic reduction by hybrid parallel active/passive filter system with square wave inverter and DC bus control

Abstract: A hybrid parallel active/passive filter system (30) is provided which provides line power harmonic isolation and compensation for power systems connected to high power non-linear loads (38). The hybrid filter (30) includes a passive filter (50, 52) connected in series with an active filter inverter (54, 56). The active filter inverter (54, 56) is controlled to generate inverter voltages such that the filter terminal voltage tracks the supply voltage harmonics at a selected dominant harmonic frequency to regulate the supply current harmonics to zero. A synchronous reference frame (SRF) based controller is used to generate harmonic inverter voltage commands based on measured supply current values. A feed forward command signal generator may be used to improve the response of the control system. The active filter inverter (54, 56) is preferably implemented as a square-wave inverter. The active filter inverter DC bus is controlled to achieve power balancing and to provide real power to compensate for losses of the inverter.

Bandwidth and central frequency control on tunable bandpass filter by using MEMS cantilevers

Abstract: This paper deals with a tunable bandpass filter topology which controls independently and simultaneously both the central frequency and bandwidth. This tunable filter results from the association of MEMS cantilevers, used as variable capacitors, with an original passive topology. The latter is based on dual behavior resonators (DBRs), each of them is constituted of low- and high-frequency open-ended stubs. The associated filter electrical response is characterized by tunable frequency transmission zeros. A millimeter bandpass filter with central frequency and relative bandwidth tunability of about 10 and 75%, respectively, is presented.

Design and Implementation of a Hybrid Output EMI Filter for High-Frequency Common-Mode Voltage Compensation in PWM Inverters

Abstract: This paper presents a hybrid output electromagnetic interference (EMI) filter for common-mode voltage compensation in pulsewidth-modulation (PWM) inverters. Its structure is composed of a single-leg four-level active filter connected in series with a low-frequency blocking capacitor and a small passive LC filter that which enhances the suppression of the common-mode voltage in the high-frequency range. The series capacitor helps in avoiding the core saturation of the common-mode coupling transformer caused by the low-frequency components of the common-mode voltage. Detection of PWM voltages by high-speed optoisolators is done at the inverter's output to achieve better common-mode voltage detection and compensation characteristics. Analysis and design guidelines for the hybrid filter are also given to facilitate systematic design in the real implementation of the filter. Experimental results with a real drive system clearly illustrate a significant reduction of the common-mode voltage, the leakage current, the shaft voltage, and the bearing current.

Efficient demodulator for bandpass sampled AM signals

Abstract: A simple nonlinear (quadratic) filter is shown to demodulate bandpass sampled AM signals efficiently. The filter is based upon a discrete version of the recently introduced Teager-Kaiser energy operator, but also closely resembles a complex digital sampling demodulator. Such a filter can also be implemented in analogue circuitry.

A high-speed, programmable, CSD coefficient FIR filter

Abstract: A new high-speed, programmable FIR filter is presented, which is a multiplierless filter with CSD encoding coefficients. We propose a new programmable CSD encoding structure to make CSD coefficients programmable. Compared with the conventional FIR structure with Booth multipliers, this coding structure improves the speed of filter and decreases the area. We design a 10-bits, 18-taps video luminance filter with the presented filter structure. The completed filter core occupies 6.8 /spl times/ 6.8 mm of silicon area in 0.6 /spl mu/m 2P2M CMOS technology, and its maximum work frequency is 100 MHz.