Showing papers on "Voltage-controlled oscillator published in 1990"

A frequency synthesiser

Abstract: A frequency synthesiser comprising a phase locked loop having a reference oscillator (8) coupled to a first input of a comparator (6), a voltage controlled oscillator (VCO) (2) for providing an output signal, which output signal is fed back by way of a divider circuit (4) or dividing the output fequency by a factor N to a second input of said comparator, the output of the comparator being applied to a control input of the VCO, and including input means for applying a modulating signal in binary format via integrator means (26) for control of the divider circuit, and means having a predetermined transfer function (22) coupling said modulating signal to the control input of the VCO whereby to provide a modulation of the output signal in desired format.

A multiple modulator fractional divider

Abstract: Based on oversampling A/D conversion technology which allows the spectrum of error energy to be shaped so that fractional synthesis error energy is pushed away from the carrier, a CMOS integrated fractional-N divider is presented. A complete fractional-N phase locked loop (PLL) which was constructed utilizing only the CMOS divider, a dual modulus prescaler, a simple loop filter, and a voltage controlled oscillator is discussed. The resulting PLL is shown to exhibit no fractional spurs. >

A voltage reduction technique for digital systems

Abstract: A self-regulating on-chip voltage-reduction circuit that adjusts the internal supply voltage to the lowest value compatible with chip speed requirements is described. Besides enhancing reliability, this technique allows power savings. The technique is based on regulation of the supply voltage of an equivalent critical path, a small circuit with delay V/sub dd/ properties proportional to those of the actual critical path. The output of this equivalent critical path is compared with the output of a second identical equivalent critical path which is connected to the full supply voltage and serves as a reference. In a first-order approximation the ratio of the delay of a critical path to the period of a ring oscillator is a constant that depends only on the number of gates, the dimensions of the transistors, and the load capacitances. This means that a ring oscillator can be used as an equivalent critical path for all digital circuits. Moreover, when the supply voltage of a ring oscillator (VCO) is changed the frequency changes. The voltage regulator principle can be implemented with a phase-locked loop (PLL). By adjusting the VCO supply voltage, the PLL causes the VCO to oscillate at N*f/sub in/. If the dimensions of the VCO transistors and the division ratio N are such that the critical path functions correctly at the regulated voltage, it will always function correctly, as changing parameters temperature or frequency f/sub in/ affect the VCO in the same way as the circuitry. >

Method and apparatus for generating secure random numbers using chaos

Abstract: Information-theoretic notions are employed to establish the predictability of a random number generated from a circuit exhibiting chaos in order to obtain a number from a sequence of numbers with a known level of randomness and security. The method provides a measure of information loss whereby one may select the number of iterations before or between bit sampling in order to extract a secure pseudo-random number. A chaotic output is obtained by use of a sample and hold circuit coupled in a feedback loop to a variable frequency oscillator, such as a voltage controlled oscillator circuit, and operated with a positive Lyapunov exponent. A source signal generator, such as a periodic wave generator, provides a driving signal to the sample and hold circuit.

On the design of voltage-controlled sinusoidal oscillators using OTAs

Abstract: A unified systematic approach to the design of voltage-controlled oscillators using only operational transconductance amplifiers (OTAs) and capacitors is discussed. Two classical oscillator models, i.e. quadrature and bandpass-based, are employed to generate several oscillator structures. They are very appropriate for silicon monolithic implementations. The resulting oscillation frequencies are proportional to the transconductance of the OTA, and this makes the structures well-suited for building voltage controlled oscillators (VCOs). Amplitude stabilization circuits using both automatic gain control (AGC) mechanisms and limitation schemes are presented. The circuits are compatible with the transconductance amplifier capacitor oscillator (TACO). Experimental results from bipolar breadboard and CMOS IC prototypes showing the potential of OTA-based oscillators for high-frequency VCO operation are included. >

Multiple frequency bio-impedance measurement system

Abstract: The multiple frequency impedance measurement system of the present invention permits noninvasive examination of living tissue at any one of a plurality of frequencies. Precise frequency control is provided by a phase locked loop (PLL) circuit which is adjustable among at least a plurality of frequencies by locking the loop to the output signal generated by a voltage controlled oscillator (VCO) divided by a selectable divisor. By selecting the divisor of the output signal of the VCO, the frequency is changed and, due to the use of a PLL circuit, each selected frequency is stably maintained. Electrodes connecting the circuit to tissue to be monitored are driven by a high-Q filter and buffer amplifier which convert the square wave output from a voltage controlled clipper circuit to a sine wave signal. The clipper circuit receives the output signal from the VCO and is part of a feedback loop which maintains a constant examination current for the system. By monitoring the examination current via a precision resistor, a current reference signal is generated and used in the feedback loop to maintain the current at a substantially constant but selectable level. The reference signal is also used to drive a resistance synchronous detector and a reactance synchronous detector to derive resistance and reactance signals, respectively, which are representative of the resistance and reactance of the tissue at the selected measuring frequency. The resistance and reactance signals are displayed via a shared digital display which is switched between the two signals.

Voltage controlled oscillator with current control

Abstract: An apparatus (200) and method for adjusting the bias current of the oscillating device (320) in a VCO (202) in response to changes in the tuning voltage of the VCO to achieve reduced sideband noise.

Phase locked loop having low-frequency jitter compensation

Abstract: A phase locked loop circuit generates an output clock that is in phase with a reference clock and is frequency jitter compensated at lower frequencies by translating intrinsic jitter frequency from low frequency to a predetermined range of higher frequencies. The phase locked loop circuit utilizes dithering circuitry to control a switched capacitor network in order to reduce the magnitude of the frequency jitter at lower frequencies. A phase detector and a loop filter of the phase locked loop circuit are implemented using digital circuitry. An oscillator of the phase locked loop is an analog oscillator which is digitally controlled and includes the switched capacitor network. Quantization error in the output clock is minimized by switching an LSB weighted capacitor in the oscillator at a frequency established by the dithering circuitry.

Adaptive phase lock loop system

Abstract: A phase lock loop for a digital input signal has a phase detector, a loop filter, a digital voltage controlled oscillator (VCO), an initial phase difference calculator, a center frequency difference calculator and an input buffer memory. In an initial training mode prepared in the PLL operation, an optimum initial phase and an optimum center frequency of the VCO to complete a lock-in state is searched for the input signal stored in the buffer memory. By estimating the initial phase difference and the center frequency different between the input signal and the VCO output with repetitive kick-offs in calculators, optimum values mentioned above are obtained. In a normal operation mode as a second mode in which the PLL operates normally as a conventional PLL, a phase lock operation between the VCO output as the reference signal and the input signal in the buffer memory is carried out after the PLL is kicked off with the optimum initial phase and the optimum center frequency determined in the initial training mode.

Method for incorporating window strobe in a data synchronizer

Abstract: A method and structure for performing data synchronization by delaying the input data for substantially one-half of the VCO signal period and then comparing the phase of the delayed input data to the VCO signal. The phase difference is filtered and controls the frequency of the VCO signal to align the VCO signal with the delayed input data. The delayed input data is clocked into a flip-flop on the opposite phase of the VCO signal to produce an output signal. In a preferred embodiment the delay of the input data for phase comparison, and the delay of the input data for the output flip-flop can be independently selected.

Direct sequence spread spectrum (dsss) communications system with frequency modulation utilized to achieve spectral spreading

Abstract: Hardware complexity of transmitting and receiving equipment in a CDMA (Code Division Multple Access) cellular radio transmission system, embodying the principles of the invention, is reduced by the use of frequency modulation (FM) techniques to achieve spectral spreading in combination with signal modulation. The spectral spreading technique of a CDMA cellular radio telephone communications system is generalized by extending the range of values allotted to the spreading waveform code signal to include complex numbers of unity magnitude. This permits the addition of a baseband version of the information signal and spreadying waveforms instead of the conventional multiplication of the two signals in existing DSSS (Direct Sequence Spread Spectrum) communications sytems. The resultant summed signal is used to control a VCO (Voltage Controlled Oscillator) to produce a frequency modulated spread signal to be transmitted. This arrangement permits improved and more efficient implementations of the transmitting and receiving equipment.

Video dot clock generator

Abstract: A video dot clock generator includes a phase-locked loop (PLL) which includes a voltage controlled oscillator, a frequency divider, a phase comparator and a loop filter. The voltage controlled oscillator (VCO) is programmable to provide multiple frequency ranges for a given range of control voltages applied to the oscillator. The programming affects both the frequency range and the gain of the VCO. The phase comparator includes circuitry which simulates a predetermined minimum phase error which, when compensated for, substantially eliminates jitter in the dot clock signal. The frequency divider used in the PLL and a similar frequency divided used to generate the reference signals for the phase comparator are programmable via an internal memory which also holds programmable control signals for the VCO. The memory, in turn, may be programmed by the user to achieve desired frequency and loop again characteristics for a given application.

A method and arrangement for frequency synthesis

Abstract: The present invention relates to frequency synthesis with a controlled oscillator (20) included in a phase locked loop, where the frequency of the oscillator output signal is divided (22) periodically by different integers, such that the frequency is, on average, divided by a value which is equal to an integer N plus or minus a numeric fraction whose absolute value is smaller than one. The phase position of pulses formed in this way is compared with the phase position of pulses which derive from a reference signal (10, 12), therewith forming a phase error signal. For the purpose of suppressing periodic variations of an oscillator control signal as a result of phase jitter, there is added or subtracted to the phase error signal, in a known manner, a correction value (24, 26) which is dependent on the aforementioned numeric fraction. In order to eliminate the need to multiply the correction value by a factor which is proportional to the inverted value of the integer N, the phase error signal is instead amplified with a factor N (28) prior to adding or subtracting the correction value. The loop bandwidth is also held constant in this way.

Clock adapter using a phase locked loop configured as a frequency multiplier with a non-integer feedback divider

Abstract: A phase locked loop configured as a frequency multiplier capable of nonintegral feedback path division utilizes a multiphase voltage controlled oscillator (5) which generates a plurality of signals (10a-10f) having a substantially identical frequency but each offset equally from the other by a given phase angle. A commutator (3) selects signals of adjacent phases so as to give the time average output signal (9) a frequency higher or lower than the frequency 10a-10f. Frequency translation is accomplished by periodically selecting signals having a longer or shorter period as desired so that a commutator output signal (9) is delayed or advanced by an appropriate amount. In the preferred embodiment, the phase locked loop is capable of converting a 1.544 MHz signal to a 2.048 MHz signal or vice versa.

Digitally controlled timing recovery loop

Abstract: A digitally controlled timing recovery loop is comprised of a digitally controlled Phase Locked Loop (PLL) consisting of a phase detector, loop filter, and voltage controlled oscillator (VCO). The phase detector is a multi-point sampling phase comparator. The loop filter is comprised of a data independent smoothing filter and a command sequencer. The VCO is a digitally controlled ring oscillator with clock phase selection. The timing recovery loop tolerates a relatively large amount of incoming jitter and minimizes data dependent, ISI-induced, intrinsic jitter.

A 300-MHz CMOS voltage-controlled ring oscillator

Abstract: A voltage-controlled ring oscillator based on feedback derived from a weighted sum of two phases of an oscillation is described. A prototype fabricated in 1- mu m CMOS attains a maximum frequency of 320 MHz, with a controllable frequency range of 100 MHz. An almost sinusoidal waveform appears at the output across this range of frequencies. >

Vector network analyzer

Abstract: A vector network analyzer utilizes a single voltage controlled oscillator to produce a sweep frequency over time, which is supplied to a device under test. The return signal from the device under test is delayed and mixed with the original signal to produce an intermediate frequency signal that is digitized and the data manipulated by a computer to measure the reflection coefficient or transmission coefficient of the device under test.

Microwave apparatus and method for measuring fluid mixtures

Abstract: Apparatus for measuring the concentration of one material such as water in another material such as crude or refined oil including a coaxial microwave transmission line (14) formed by a conduit for receiving the material and a center conductor (22) which is sheathed with a dielectric covering (27) which is operable to prevent short circuiting of the transmission path. An oscillator circuit (30) is coupled to the transmission line and is driven by a free-running voltage controlled oscillator and a signal receiver monitors the change in frequency caused by impedance pulling of the oscillator due to the change in the dielectric constant of the mixture. Incident and reflected or transmitted power with respect to the measurement section is measured to determine whether an oil-in-water or water-in-oil emulsion is present to verify the concentration of one fluid in the other for a particular operating frequency.

Clock recovery phase lock loop having digitally range limited operating window

Abstract: A PLL architecture is disclosed which incorporates a coarse adjustment feedback loop and a fine adjustment feedback loop together providing a combined error signal to a single VCO. The coarse adjustment feedback loop includes two digital counters set to divide the VCO output frequency by two different numbers. The outputs of the counters are coupled to the inputs of respective phase-frequency detectors, and the pump-up output of one of the detectors and the pump-down output of the other detector are used as the coarse adjustment pump-up and pump-down signals, respectively, in the coarse adjustment feedback loop. The coarse adjustment feedback loop thereby establishes a frequency range limitation for the fine adjustment feedback loop.

Microwave oscillator with reduced phase noise

Abstract: An oscillator operational in the millimeter wave and microwave range, including frequencies greater than 60 GHz, is provided with reduced phase noise by enhancing Q of the resonant circuitry by reactively terminating fundamental frequency oscillation and increasing stored fundamental frequency energy in the resonant circuitry. A two frequency system is provided with constructive reflection of energy at fundamental frequency back to the resonant circuitry, and with isolation of fundamental frequency energy from the output load. Energy to the output load is obtained from the in-situ generated second harmonic of the active element. Phase noise is reduced by enhancing Q by more than an order of magnitude.

Frequency synthesizer with control of start-up battery saving operations

Abstract: A frequency synthesizer (10) governed by a battery saving signal (20) having sleep and awake cycles (60, 62) comprises a phase locked loop and a control circuit (70) for enhancing the restart operation of the phase locked loop at the commencement of each awake cycle of the battery saving signal. More specifically, the phase locked loop includes a phase detector (26, 28) for locking the frequencies generated by a reference oscillator (12) and a voltage controlled oscillator (36) by adjusting a signal (38) in a storage device (34) used for governing the voltage controlled oscillator. During the sleep and awake cycles of the battery saving signal, the oscillators and phase detector are inhibited and enabled, respectively, in their operations. The control circuit is operative to inhibit the adjustment of the governing signal until both of the oscillators are determined to be effectively enabled at the commencement of each awake cycle of the battery saving signal to ensure the stored governing signal commences at its desired setting.

Resonant scanner control system

Abstract: A resonant scanner control system controls a laser source using a pixel clock which uses a voltage controlled oscillator (VCO) and a phase detector to track continuously throughout the entire scan cycle the pixel-to-pixel and cycle-to-cycle operations of the scanner. The clock includes a VCO which changes frequency in a linear manner in response to changes in a frequency-control voltage applied to it. The VCO includes a negative feedback loop which consists of a frequency-to-voltage converter, which converts the VCO output to a related voltage, and a summing/integrating circuit, which compares this voltage with the frequency-control voltage which is produced in response to pixel related control signals and then integrates the difference. The integrated signal drives the VCO, which produces in response an output signal whose frequency varies linearly with variations in the pixel-related frequency-control signal. Once during each scan cycle the phase detector detects any phase error between a pixel-clock-driven synchronization signal and a position-related synchronization signal, which is produced by an optical detector. If the two synchronization signals do not coincide, the phase detector sends an appropriate analog error signal to a multiplying reference port of a multiplying digital/analog converter (DAC) which produces the pixel related frequency-control signal. The DAC then adjusts its frequency-control signal in accordance with the error signal.

Phase locked loop circuit with digital control

Abstract: A Phase Locked Loop (PLL) circuit includes a control signal generator, a digital phase detector, logic gates, a charge pump (charge/discharge circuit), a transmission gate, a loop filter, a lead-lag filter and a voltage controlled oscillator (VCO). Outputs of the digital phase detector are coupled through the logic gates to inputs of the charge pump. An output of the charge pump is coupled to the capacitor and to a first input/output of the transmission gate. A second input/output of the transmission gate is coupled to an input of the loop filter whose output is coupled to an input of the VCO whose output is coupled to a first input of the digital phase detector. A second input of the digital phase detector is coupled to a source of a reference frequency signal. The control signal generator generates non-overlapping complementary control signals with one of same connected to the logic gates and the other connected to the transmission gate. Accordingly, the electrical path from the digital phase detector to the charge pump through the logic gates is closed and the electrical path from the capacitor to the loop filter is open or vice versa. The loop filter includes an operational amplifier with AC feedback which is controlled by the same signal which controls the logic gates. The PLL circuit is typically formed on a single integrated circuit silicon chip using CMOS technology.

Charge pump circuit

Abstract: A charge pump circuit for charging a capacitor in response to a phase difference between first and second input signals comprises a constant current source for providing a first constant current; a constant current sink for absorbing a second constant current; a circuit for substantially equalizing the magnitudes of the first and second constant currents; and a switching circuit for providing the first constant current and the second constant current flowing in opposed directions to the capacitor through an output terminal of the charge pump circuit in response to the phase difference between the first and second input signals to produce a voltage level across the capacitor corresponding to the phase difference. In a phase locked loop system employing such a charge pump circuit, a phase comparator produces a phase difference signal for controlling the provision of the first and second constant currents by the switching circuit to the capacitor. The capacitor acts as a loop filter supplying the voltage thereacross as a control voltage to a voltage controlled oscillator of the phase locked loop system.

Frequency synthesizer allowing rapid frequency switching

Abstract: A frequency synthesizer is designed to modify voltage value data read out of a memory in accordance with the output voltage of a filter, and apply a d.c. voltage corresponding to the modified data to a second variable-capacitance diode at the control input of a VCO, thereby allowing the VCO frequency switching without imposing a significant fluctuation of the application voltage to a first variable-capacitance diode and accomplishing a short channel switching time and stable operation against temperature fluctuation. The device is further designed to supply a voltage setup value read out of the memory to the second variable-capacitance diode thereby to reduce the frequency matching time at channel switching, and to determine such another voltage setup value as to reduce the time of phase matching based on the trend of change in the filter output voltage and supply the value to the second variable-capacitance diode.

A new low-noise 100-MHz balanced relaxation oscillator

Abstract: A novel fully balanced architecture for high-frequency, low-noise relaxation oscillators is presented. Differential operation is achieved with the use of two grounded capacitors utilizing the circuit parasitics. Bypassing of the regenerative memory function in the oscillator benefits both high-speed and low-noise operation. A detailed analysis of phase noise in relaxation oscillators is performed. Results obtained from a test chip have verified the viability of the new oscillator and the developed phase-noise theory. The oscillator circuit has been realized in a medium-frequency (f/sub tau /=3 GHz) bipolar process. The tuning range extends to 150 MHz. At an oscillation frequency of 115 MHz, measured phase noise was -118 dBc/Hz at 1-MHz distance from the carrier. >

Inexpensive portable rf spectrum analyzer with calibration features

Abstract: An inexpensive portable RF (radio frequency) microcontroller-based (76) digital spectrum analyzer (50) is automatically calibrated for passband amplitude tilt/variations. Resulting software-obtained (78) calibration parameters are used during operation to reduce or eliminate passband amplitude errors. The spectrum analyzer (52) also includes a PLL frequency synthesizer (100) arrangement, but the PLL (100) controls a VCO only during calibration to derive calibration values for controlling a digital-to-analog converter (92). During normal operation, the VCO is driven in an open loop configuration under software control using such calibration values -- achieving nearly the accuracy of closed loop operation while avoiding the penalty of long PLL lock time. These amplitude and frequency calibration techniques and arrangements permit the spectrum analyzer to have relatively inexpensive components and circuit arrangements and nevertheless achieve high accuracy over a wide band.

Phase-locked loop with pulse-duration modulation fine frequency control

Abstract: A phase-locked loop includes an oscillator controlled by means of a switching network and a microprocessor which generates, in response to the output of a phase detector, two groups of output signals. A first group (Q1 . . . QN) is for adjusting the frequency of the oscillator in steps by selectively switching in frequency determining elements, and a second group (P1 . . . PM) for feeding a pulse duration modulator. The pulse duration modulator produces a control signal for a frequency determining minimum element of the switching network. The control signal has a duty cycle indicative of the frequency determination contribution by the minimum element.

High spectral purity X-band source

Abstract: An X-band source that is specifically designed for high order frequency multiplication and precision spectroscopy is presented. The wideband phase noise is controlled by frequency-locking a dielectric resonator oscillator source to a high-Q cavity with a DC loop. This avoids the need for modulation on the source signal that might interfere with high order multiplication. The phase noise close to the carrier can be controlled by phase-locking the 10.6 GHz signal to a harmonic of a low-noise quartz crystal controlled oscillator. Modulation sideband due to the power line and harmonics are suppressed far below the random noise by enclosing the entire source in a magnetic shield. The phase noise is lower than previously published levels of phase noise for a free-running, room temperature, X-band source. In principle the 10.6 GHz signal could be multiplied to approximately 250 THz before carrier collapse would occur. At 250 THz the free-running linewidth would be approximately 2.8 kHz. At a frequency of 30 THz a linewidth on the order of 10 Hz is expected if the phase noise near the carrier is controlled by a harmonic of a low-noise 5 MHz oscillator. >