Showing papers on "Voltage-controlled oscillator published in 1991"

A multiple modulator fractional divider

Abstract: Fractional-N frequency synthesis using a phase locked loop (PLL) is considered. Advances in oversampling A/D conversion technology are incorporated into fractional-N synthesis, allowing the spectrum of error energy to be shaped so that fractional synthesis error energy is pushed away from the carrier. Based on this new technology, a CMOS integrated fractional-N divider was successfully developed. A complete fractional-N PLL was constructed utilizing only a CMOS divider, a dual modulus prescaler, a simple loop filter, and a voltage controlled oscillator (VCO). The resulting PLL exhibits no fractional spurs. >

Embedded servo banded format for magnetic disks for use with a data processing system

Abstract: A data processing system records information on magnetic disks in a format in which sector headers, which include embedded servo information, are radially aligned and recorded at a single frequency and data are recorded at various band-related frequencies. The system records sector headers at a frequency which is optimal for the recording of address information in the shortest sector and records the data at frequencies which are optimal for the recording of information in the disk space allocated to the data portion of the various lengths of sectors. The system synchronizes to the headers, using conventional embedded servo synchronization methods, and produces header timing signals. It can then use the same header timing signals to locate and interpret the headers on different tracks, since the header frequency and the location of the headers are the same in every track. The system may record the data portions of the sectors at frequencies which are related to the header frequency by ratios of small integers. The system then uses, in synchronizing to the disk, a phase locked loop which includes a voltage controlled oscillator (VCO) that is driven to a reference frequency which is directly related to the header frequency. The system divides-down the frequency of the VCO output signal to produce the timing signals for the header. Also, it uses a version of the output signal of the VCO, which is divided-down by a band-related value, as a timing signal for the data.

Design of a 15-MHz CMOS continuous-time filter with on-chip tuning

Abstract: A fifth-order CMOS continuous-time Bessel filter with a tunable 6- to 15-MHz cutoff frequency is described. This fully balanced transconductance-capacitor (G/sub m/-C) leapfrog filter achieves a dynamic range of 55 dB while dissipating 96 mW in a 5-V 0.9- mu m CMOS process. The author reviews the disk drive application and filtering requirements, and explains why the G/sub m/-C continuous-time filtering approach was used. The on-chip master-slave tuning system uses a voltage-controlled oscillator (VCO). Experimental results are presented. >

Multi-loop control for quasi-resonant converters

Abstract: A multiloop control scheme for quasi-resonant converters (QRCs) is described. Like current-mode control for pulse width modulation (PWM) converters, this control offers excellent transient response and replaces the voltage-controlled oscillator (VCO) with a simple comparator. In this method, referred to as current-sense frequency modulation (CSFM), a signal proportional to the output-inductor current is compared with an error voltage signal to modulate the switching frequency. The control can be applied to either zero-voltage-switched (ZVS) or zero-current-switched (ZCS) QRCs. Computer simulation is method applied to a ZCS buck QRC. A circuit implementation is presented that allows multiloop control to be used on circuits switching up to 10 MHz. This circuit requires few components and produces clean control waveforms. Experimental results are presented for zero-current flyback and zero-voltage buck QRCs, operating at up to 7 MHz. Good small-signal characteristics have been obtained. >

High frequency CMOS VCO with gain constant and duty cycle compensation

Abstract: The present invention provides a high frequency CMOS voltage controlled oscillator circuit with gain constant and duty cycle compensation. The voltage controlled oscillator circuit includes a multi-stage ring oscillator that includes a plurality of series-connected inverter stages comprising N-channel and P-channel transistors. The ring oscillator responds to a control current signal for controlling the frequency of oscillation of the ring oscillator. A voltage-to-current converter converts a tuning voltage input signal to a corresponding output current signal that is independent of the channel strength of the N-channel and P-channel transistors. Process compensation circuitry responds to the tuning voltage input signal to provide a current dump output signal corresponding to the channel strength of the P-channel and N-channel transistors. Trip-point compensation circuit provides a net ring current signal as the current control signal to the ring oscillator. The net ring current signal represents the difference between the output current signal and the current dump output signal and responds to the balance between the output buffer trip point and a ring oscillator dummy stage.

High-speed voltage-controlled oscillator with quadrature outputs

Abstract: A voltage-controlled oscillator topology is described that combines a fully-differential four-stage ring oscillator with a balanced exclusive NOR gate frequency doubler, and provides both inphase and quadrature output signals at twice the ring oscillator frequency. These quadrature signals have a period of only four gate delays, which implies high frequency operation.

Ultra wideband radar transmitter employing synthesized short pulses

Abstract: A predetermined radar pulse train is formed in space by transmitting individual spectral components thereof. Thus, a train of extremely short pulses is obtained without switching a radio frequency signal on and off at a high rate. A crystal oscillator is coupled to a harmonic generator such as a comb generator. A power divider distributes the output of the harmonic generator to a multiplicity of final filter amplifiers. Each final filter amplifier has a phase-locked VCO circuit that provides frequency accuracy, spectral purity, low noise and frequency stability. Thus, each final filter amplifier provides one of the spectral components of the predetermined radar pulse train. The final filter amplifiers are coupled by duplexers to a broadband multiplexing feed such as a nested cup dipole feed that illuminates a reflector. On receive, the broadband multiplexing feed separates all the spectral components of the incoming pulse train. Each spectral component is coupled to its own narrow band receiver by the duplexers. One receiver is used to amplify and detect each spectral component. The signals from the receivers are coherently combined in a signal processor in which the signals add coherently and the noise signals do not. This provides a processing gain in signal to noise ratio corresponding to the total number of receivers. The output of the signal processor is applied to a radar display.

Digital temperature-compensated oscillator

Abstract: A digital temperature-compensated oscillator comprises a crystal oscillator, a first memory previously storing digital temperature compensation data obtained by previously measuring the relation between the ambient temperatures and the frequency deviations of the crystal oscillator, a second memory for storing frequency offset amounts of the oscillation frequency of the crystal oscillator, a temperature sensor for outputting analog detection data relating to the ambient temperature, an A/D converter for converting the analog detection data to digital detection data, a readout circuit for reading out temperature compensation data corresponding to the digital detection data and stored in the first memory according to the digital detection data and reading out the frequency offset amount stored in the second memory according to the digital detection data, an operation circuit for effecting the following calculation by use of the readout temperature compensation data and readout frequency offset amount to derive digital control voltage, V.sub.c =V.sub.co +(K.sub.00 +V.sub.co K.sub.10 +K.sub.01 T)×(ΔF+ΔF 2 ×K 10 /2) where K 00 , K 01 and K 10 are constants, V co is an initial value of the control voltage, T is an ambient temperature and ΔF is a frequency offset amount, a D/A converter for converting the digital control voltage into an analog control voltage, and a voltage-capacitance converter for receiving the analog control voltage and generating a control signal to be supplied to the crystal oscillator according to the received analog control voltage, wherein the frequency of the crystal oscillator is controlled according to the control signal.

Frequency synthesizer having microcomputer supplying analog and digital control signals to VCO

Abstract: A frequency synthesizer includes an oscillator which may be coarse-tuned by a first input receiving a digital signal for selecting one of a plurality of frequency ranges, and fine-tuned by a second input receiving an analog signal for selecting the desired frequency within the selected frequency range. The synthesizer further includes a computer storing the oscillator's characteristics in the form of a digital table of the input signals corresponding to a plurality of frequency values, each identified by digital data. The computer receives input data representing the desired oscillator frequency and generates from the stored digital table, a digital signal indicating the frequency range of the desired oscillator frequency, and an analog signal indicating the specific oscillator frequency desired, and applies both signals to the oscillator. A frequency measuring circuit measures the actual output frequency of the oscillator and outputs a signal corresponding thereto. This signal is fed back to the computer for controlling, in response thereto, the digital and analog signals generated by the computer.

Differential-logic ring oscillator with quadrature outputs

Abstract: A topology for a high speed voltage controlled oscillator (VCO) with quadrature outputs is produced utilizing four inverting differential circuits (12, 14, 16, 18). The fully differential four stage ring oscillator has outputs from alternate delay circuits combined in balanced exclusive OR gate frequency doublers (24, 26) to provide both in-phase and quadrature output signals at twice the ring oscillator frequency. The period of the quadrature delay signals is four gate delays and is easily realized in the Ghz frequency ranges. The in-phase and quadrature output signals are again combined in a balanced exclusive OR gate frequency doubler (36) to obtain a final output frequency quadruple the ring oscillator frequency.

Phase locked loop circuit responding to supplied signal frequency

Abstract: A phase locked loop circuit, which is arranged for receiving a first signal having a given frequency and producing a second signal which has the same frequency and is synchronous with the first signal, comprises control voltage generating means for generating a control voltage responding to a phase difference and a frequency difference between the first and second signals, a voltage controlled oscillator containing a ring oscillator having a multiplicity of the rows of inverters for producing a frequency output which is primarily determined by the control voltage, and a quantity-of-rows changing means for automatically changing the quantity of the inverters rows in the ring oscillator according to the control voltage.

Fractional-N synthesizer having modulation spur compensation

Abstract: A synthesizer circuit (10) with spur compensation utilizes fractional division in the synthesizer loop. The fractional divider (12) includes means for compensating the spurs when the fractional numerator N ¸ 0. The synthesizer (10) includes means for selecting a reference divisor R such that a non zero value of fractional numerator is produced and such that the generated spurs fall below the side band noise limits of the synthesizer's voltage controlled oscillator (15).

Pll frequency synthesizer capable of changing an output frequency at a high speed

Abstract: In a frequency synthesizer, a first pulse removing circuit (31) is connected between a reference signal generator (21) and a phase-frequency comparator (24). A second pulse removing circuit (32) is connected between a variable frequency divider (23) and the phase-frequency comparator. Responsive to first removing data indicative of a first pulse number, the first pulse removing circuit removes pulses from the reference signal that are equal in number to the first pulse number for a first predetermined cycle to produce a first pulse removed signal. Responsive to second removing data indicative of a second pulse number, the second pulse removing circuit removes pulses from the divided signal that are equal in number to the second pulse number for a second predetermined cycle to produce a second pulse removed signal. Responsive to a current command, a current controlling circuit may control current supplied from/to a charge pump circuit (25). A control circuit may be connected between the phase-frequency comparator and the charge pump circuit. A switch may be inserted between the loop filter and the voltage controlled oscillator. When the switch switches off a PLL, a D/A converter supplies a control voltage to the voltage controlled oscillator and a filter capacitor of the loop filter. The charge pump circuit may comprise a control circuit, a constant current circuit, an integrating circuit, and a sample and hold circuit.

Ink jet recorder

Abstract: PURPOSE:To make the printing density adjustable by mounting a means for variably controlling the oscillating frequency of an oscillator, a means for modulating the pulse width of a printing signal according to the change in oscillating frequency of the oscillator, and a printing means for changing the travel speed at the printing position CONSTITUTION:An oscillator mounted on a nozzle is driven by a VCO(voltage control oscillator) 29 The oscillating frequency of the VCO 29 is varied by a variable resistance 28 In an F/V(frequency-voltage) converter 31, a motor 23 is driven in accordance with the oscillating frequency of the VCO 29, a rotating drum 21 is rotated, and recording paper 22 is fed in accordance with an interval of ink drop separation A CPU 27 inputs the output of the VCO 29 and the output of an encoder 24 detecting the rotating state of a rotating drum 21 and outputs a printing signal after changing the pulse width thereof On this output, a high voltage driver 30 drives a charged electrode on a head part 20, and the head part 20 is driven in accordance with the output of the VCO 29 In this manner, printing density can be adjusted simply by adjusting the variable resistance 28 while observing an image to be printed

Phase-locked loop circuit

Abstract: A phase-locked loop circuit comprises first and second charge pumps which apply charge and discharge voltages to a control voltage generator. The control voltage generator applies a control voltage which is dependent on the charge and discharge voltages to a voltage controlled oscillator. The voltage controlled oscillator generates an oscillation frequency dependent on the control voltage. The oscillation frequency is compared with a reference frequency to detect a difference therebetween. The first charge pump supplies a charge or discharge voltage to the control voltage generator intermittently for a first period, and the second charge pump, in parallel with the first charge pump, supplies a charge or discharge voltage to the control voltage generator continually for a second period subsequently to the first period, so that a time by which the difference becomes zero is shortened by use of the second charge pump as compared to a case where the first charge pump is only used.

Adaptive lock time controller for a frequency synthesizer and method therefor

Abstract: An adaptive lock time controller for a phase locked loop having dividers for generating first and second loop timing signals, a phase detector, a voltage controlled oscillator, and a charging circuit for generating at least a first control signal for converging the output frequency to one or more predetermined frequency channels and a second control signal for maintaining the output frequency substantially constant, comprises a synchronization generator, a phase lock detector, and a control signal selector. The synchronization generator is responsive to the phase detector for synchronizing the phase lock detector. The phase lock detector detects phase locked and unlocked conditions by generating a count representative of the phase difference between the first and second loop timing signals. When the count generated exceeds a predetermined count, a phase locked condition exists, otherwise the loop is unlocked. The control signal selector selects the first control signal during the predetermined time interval when the phase unlocked condition is detected, and the second control signal when the phase locked condition is detected.

PLL clock synthesizer using current controlled ring oscillator

Abstract: A high frequency clock signal synthesizer circuit employs a single fixed reference clock signal to generate one or more variable frequency clock signals. A phase comparator and a variable count counter generate a control signal from the reference clock and circuit output and provide it to a voltage controlled oscillator. High frequency stability of the voltage controlled oscillator is provided by a ring oscillator with a control signal response which is linear even at high frequencies. The ring oscillator employs an odd number of inverting delay stages coupled in series in a ring configuration, each delay stage having an input, an output, an inverter coupled to the input and a controllable current source buffering the switching transistors of the inverter from the output. A bias circuit controls the current of the current source and thereby controls the delay of each delay stage and thus the frequency of the ring oscillator. The buffering of the switching transistors from the output nodes of the delay stages prevents transient effects due to parasitic capacitances and process variations from affecting the current to the output node and hence from affecting the delay of the delay stage and the frequency of the ring oscillator.

Phase locked loop lock detector including loss of lock and gain of lock detectors

Abstract: A phase lock detector circuit for detecting the lock state of a phase locked loop (PLL) such that it is known when a synthesized clock has achieved a stable phase relationship with its reference clock signal. The PLL includes an input for receiving the reference signal, a digital phase detector, a voltage controlled oscillator, and a frequency divider. The phase lock detector of the present invention includes a loss of lock detector (LOLD) connected to the frequency divider, the phase detector and the input. The LOLD detects the occurrence of a selected phase difference between the reference signal and an output of the frequency divider for a selected number of cycles. Also included is a gain of lock detector (GOLD) connected to the frequency divider and the input. The GOLD detects the occurrence of the reference signal within a selected phase difference of an output of the frequency divider for a second selected number of cycles. The outputs of the LOLD and the GOLD are connected to a latch for generating a composite signal responsive to signals generated by the LOLD and the GOLD such that the composite signal has a first state indicating when the PLL is in a locked condition and a second state indicating when the PLL is in an unlocked condition. The phase differences and the selected number of cycles of the LOLD and GOLD may be programmed, as desired.

Phase-locked loop frequency tracking device including a direct digital synthesizer

Abstract: Disclosed is a single phase-locked loop (50, 350) providing tuning over a very large bandwidth for use in wide band carrier tracking and clock recovery systems. In a first embodiment, a DC signal is formed representative of a phase difference between an input signal changing with time and a return signal. The DC signal is applied to a narrow band voltage controlled oscillator (68) which converts the DC signal back to an AC signal. The AC signal is level shifted to form a clocking pulse for an accumulator (80) of a direct digital synthesizer (72). A digital command word is also applied to the accumulator (80), such that the digital command word represents a coarse tuning of the input frequency. The clocking pulse from the narrow band VCO (68) supplies a fine tuning of the input frequency. In a second embodiment, the DC representative phase signal is applied to an analog-to-digital converter (364) which produces an N-bit word representative of the phase difference. The change in phase alters the digital output of the analog-to-digital converter (364) which in turn is applied to the accumulator (376) of a direct digital synthesizer (370). By this invention, very wide band tracking is capable with a single phase-locked loop, thus limiting the hardware and cost.

Fast-switching frequency synthesizer

Abstract: A fast-switching frequency synthesizer utilizes a time-varying presteering voltage injection at the voltage controlled oscillator ("VCO") with feedback to allow the VCO and synthesizer to rapidly change between two given frequencies.

Computer-aided analysis of free-running microwave oscillators

Abstract: The authors present a newly developed free-running steady-state oscillator analysis algorithm suited to large-signal oscillator analysis. Kurokawa's oscillation condition is coupled with the modified nodal admittance form of the circuit equations to avoid degenerate solutions. The algorithm was implemented by using both harmonic balance and frequency-domain spectral balance techniques. It was used in the simulation of monolithically integrated varactor-tuned MESFET oscillator. Good agreement between simulated power and oscillation frequency results was obtained. >

Variable frequency oscillator

Abstract: A variable frequency oscillator circuit adapted for stabilization of its free-running frequency comprises a first signal synthesizing circuit, first voltage-controlled oscillator, a phase-locked loop and reference signal generator, the phase-locked loop consisting of a second signal synthesizing circuit, second voltage-controlled oscillator, phase comparator and low-pass filter. The first and second signal synthesizing circuits have the same characteristics, and the first and second voltage-controlled oscillators have the same characteristics. The reference signal and output of the second voltage-controlled oscillator are input to the phase comparator. The comparator output is applied to the first and second signal synthesizing circuits. An external signal is applied to the first signal synthesizing circuit, and the output of the first voltage-controlled oscillator acts as the output of the variable frequency oscillator circuit. The principles are applied to reading data pulses from a floppy disk.

A 1.5 Gb/s link interface chipset for computer data transmission

Abstract: The authors designed a set of four ICs to provide encoding, multiplexing, clock extraction/demultiplexing, and decoding for gigabit-rate serial data transmission. These chips form a high bandwidth data link for point-to-point communication. A new line code is implemented that provides DC balance, efficient encoding, framing, and simple clock extraction. Embedded in the code is a fixed transition used by the phase/frequency locked loop (PLL) for simple clock extraction and frame synchronization. Unlike other links, this PLL requires no trimming for data retiming, either in production or later. An on-chip voltage-controlled oscillator (VCO) with a tuning range of 1.1-1.6 GHz is available for use with the PLL. With this chip set the authors demonstrated a transmission rate of 16 bits in parallel at 75 MHz or, with encoding overhead, a serial rate of 1.5 Gb/s. >

EMI-induced failures in crystal oscillators

Abstract: An electromagnetic interference (EMI) induced failure mode pertaining to crystal-based voltage-controlled oscillators (VCO) has been studied. The failure consists of a transition to a frequency of oscillation that differs from the crystal's fundamental resonant frequency, when the circuit is temporarily exposed to continuous or pulsed radio-frequency electromagnetic fields. The new state persists even after the EMI source is removed and leads to hang-up in digital systems. This mode transition has been observed experimentally. Its essential properties have been predicted theoretically and simulated numerically, using simplified oscillator models. The likelihood of observing such a failure in a noisy electromagnetic environment is assessed with respect to the radiated susceptibility levels given in MIL-STD-461B. >

Advanced phase locked loop circuit

Abstract: A PLL circuit comprises a voltage controlled oscillator responsive to a control signal to output an output signal having a variable oscillation frequency; a phase detector for making a phase comparison between the output signal from the voltage controlled oscillator and a reference signal, and for outputting an output error signal; an integrator for integrating the output error signal from the phase detector to extract a direct current variable component contained in the output error signal, the integrator having a first cutoff frequency; and a loop filter for feeding the direct current variable component from the integrator to the voltage controlled oscillator as the control signal to synchronize the output signal from the voltage controlled oscillator with the reference signal. An alternate current coupling circuit is provided for adding only an alternate current component contained in the output error signal from the phase detector to the control signal for feeding to the voltage controlled oscillator; and a compensating circuit is inserted in an alternate current signal path of the alternate current coupling circuit. The compensating circuit is inserted in an alternate current signal path of the alternate current coupling circuit. The compensating circuit has a second cutoff frequency exceeding the first cutoff frequency of the integrator, so that a wide band characteristic is obtained, and SSB phase noise suppression is improved.

Linearized three state phase detector

Abstract: A linearized three state phase detector (300) that exhibits a linear transfer function of phase to current or charge at and around the zero phase error region. The inputs to the D flip-flops (301 and 302) are tied to a logic high. The first flip-flop (301) is clocked with reference signal F r while the other flip-flop (302) is clocked with a variable frequency feedback signal F v . F v is typically from a voltage controlled oscillator in a phase locked loop. The outputs of the flip-flops are ANDed together with the result of this operation going through a delay element (304) before reseting one of the flip-flops (301). The other flip-flop (302) is reset by the output of the AND gate (304) without the delay element (304). Each flip-flop output enables a charge pump - one negative polarity (306) and one positive polarity (305). The present invention (300) will maintain a lock condition in a phase locked loop by extending the DOWN pulse enabling the negative polarity charge pump (306) to the same width as the UP pulse that enables the positive pump (305). This will create a net zero charge from the present invention (300).

Monolithic digital phaselock loop circuit having an expanded pull-in range

Abstract: A monolithic phaselock loop circuit (PLL) for controlling the phase and frequency of a VCO to compensate for process induced variations in the VCO natural frequency and to extend the pull-in range by ±50% of the frequency of a reference clock. The PLL is comprised of a VCO, a digital phase comparator, a digital frequency divider and a digital sequential phase error detector (SPED). The SPED circuit comprises two up-down counters, one to control the phase; the other, the frequency; a first one-shot circuit that drives the phase up-down counter to detect every level transition of the reference clock and a second one-shot circuit that drives the frequency up-down counter to provide a pulse for every falling edge of the reference clock; and a shift register responsive to the phase comparator to store the value of the phase comparator thereby providing indication of a frequency lock between the reference clock and the VCO.

A multi-loop controlled VCO

Abstract: Separate phase (or frequency/phase) detectors (11,13) are used in separate feedback loops of a phase-locked loop, one of the detectors having a dead zone (11) and the other detector having no dead zone (13). The dead zone of the one detector (11), rather than being regarded as undesirable as in the prior art, is used to gradually shift the effective loop bandwidth of the phase-locked loop from a wide bandwidth to a narrow bandwidth without requiring any deliberate control action or switching circuitry.

Switching regulator in which oscillation is maintained below a predetermined frequency

Abstract: A switching regulator, which applies output DC voltage to a load via an oscillator oscillatable between ON and OFF states, has an oscillation controller to control the oscillation of the oscillator based on the load so that a frequency of the oscillating of the oscillator is kept lower than a predetermined frequency irrespective of the load.