Showing papers on "Voltage-controlled oscillator published in 1992"

A 155-MHz clock recovery delay- and phase-locked loop

Abstract: The authors describe a completely monolithic delay-locked loop (DLL) which may be used either by itself as a deskewing element or in conjunction with an external voltage-controlled crystal oscillator (VCXO) for a delay- and phase-locked loop (D/PLL) that enables jitter-peaking-free clock recovery by removing the zero from the forward path. The voltage-controlled phase shifter (VCPS) shifts incoming data under loop control to align the data with the clock. The loop amplifier is an integrator so that the DLL is first order. The bandwidth of the loop determines the frequencies over which input jitter may be tracked out. The phase detector is a pattern-and duty-cycle insensitive implementation. The higher-order poles provide additional filtering of phase-detector output ripple to further improve jitter accommodation. >

A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s

Abstract: A phase and frequency detector IC is presented that operates up to an NRZ bit rate of 8 Gb/s. The IC comprises a phase detector (PD), a quadrature phase detector (QPD), and frequency detector (FD). In the PD and QPD the VCO signal and the quadrature VCO signal are sampled by the NRZ input signal. The two beat notes provided by this operation are subsequently processed in the FD. The superposition of the FD output and the PD output signals are then fed into a passive loop filter (lag/lead filter). The loop filter and the VCO are external components. The measured pull-in range is >+or-100 MHz at 8 Gb/s. The measured r.m.s. time jitter of the extracted clock is less than 1.9 ps for a pseudorandom bit sequence (PRBS) length of 2/sup 23/-1. A 0.9- mu m 12-GHz f/sub T/ silicon bipolar process was used to fabricate the chip with a total power consumption of 1.4 W. >

A 1.8-GHz monolithic LC voltage-controlled oscillator

Abstract: The authors describe a monolithic LC VCO (voltage-controlled oscillator) for use in the microwave frequency range. The circuit does not require any external components, but instead relies on characteristics inherent in the circuit configuration for frequency tuning. A simplified circuit schematic of the LC VCO is shown. A monolithic LC VCO achieves a measured tuning range of 200 MHz, extending from 1.68 GHz to 1.86 GHz. >

A 6-GHz integrated phase-locked loop using AlGaAs/GaAs heterojunction bipolar transistors

Abstract: A fully integrated 6-GHz phase-locked-loop (PLL) fabricated using AlGaAs/GaAs heterojunction bipolar transistors (HBTs) is described. The PLL is intended for use in multigigabit-per-second clock recovery circuits for fiber-optic communication systems. The PLL circuit consists of a frequency quadrupling ring voltage-controlled oscillator (VCO), a balanced phase detector, and a lag-lead loop filter. The closed-loop bandwidth is approximately 150 MHz. The tracking range was measured to be greater than 750 MHz at zero steady-state phase error. The nonaided acquisition range is approximately 300 MHz. This circuit is the first monolithic HBT PLL and is the fastest yet reported using a digital output VCO. The minimum emitter area was 3 mu m*10 mu m with f/sub t/=22 GHz and f/sub max/=30 GHz for a bias current of 2 mA. The speed of the PLL can be doubled by using 1- mu m*10- mu m emitters in next-generation circuits. The chip occupies a die area of 2-mm*3-mm and dissipates 800 mW with a supply voltage of -8 V. >

Integrated charge-pump phase-locked loop circuit

Abstract: A variable bandwidth phase-locked loop clock generator circuit is disclosed. The PLL circuit includes a phase comparator which presents pump-up and pump-down signals, indicating the polarity of the desired frequency change. The phase comparator also generates multiple level control outputs to control the rate of the frequency change. A current source includes a reference leg having a plurality of resistors which are shorted out according to the control outputs, from which a bias signal is generated. The level of the bias signal controls current sources in the output leg of the current source to control the rate of change of the voltage applied to the voltage controlled oscillator. In addition, the bias signal also controls the slew rate of an active low-pass filter according to the desired response characteristic; the output of the filter is applied to the voltage controlled oscillator for generating the output clock signal. This construction of the PLL circuit allows for the control signals to control the rate of change both for advancing and retarding the output clock frequency, and allows for on-chip implementation of the filter components in a manner compatible with MOS technology.

Temperature-compensated ring oscillator circuit formed on a semiconductor substrate

Abstract: An improved ring oscillator is disclosed which can be formed in a semiconductor substrate. The ring oscillator includes inverters cascaded in a ring-like manner, and a diffused resistor R1 having a positive temperature coefficient and a polysilicon resistor R2 having a negative temperature coefficient for determining bias currents supplied to the inverters. The oscillation frequency tends to decrease with a rise of ambient temperature based on a temperature characteristic of diffused resistor R1 and a temperature characteristic of the oscillator circuit itself; however, the change of oscillation frequency is compensated by a temperature characteristic of polysilicon resistor R2. Therefore, a reference clock signal generating circuit having an oscillation frequency which is not affected by change of the ambient temperature can be formed in the semiconductor substrate.

Widely tunable oscillator stabilization using analog fiber optic delay line

Abstract: A circuit for stabilizing an oscillator having an oscillator output signal includes a long optical fiber delay line which receives an optical version of the oscillator output signal and a phase detector sensing the oscillator output signal and the delayed optical output signal through the long optical fiber. The output of the phase detector is fed back to the oscillator's frequency control input to stabilize the frequency. The phase detector and the delay line are a delay line discriminator, and the length of the optical fiber is selected so as to optimize the discriminator's sensitivity against signal attenuation in the optical fiber, the optical fiber length typically being on the order of 10 kilometers. An adjustable phase shifter which maintains phase quadrature at the phase detector inputs at equilibrium is controlled by a tuning microprocessor responsive to an externally controlled change in the frequency at which the oscillator is to be stabilized, so as to follow changes in the selected oscillator frequency. As a result, an oscillator may be tuned in the circuit of the invention to any frequency in the general range of D.C. to optical frequencies.

PLL clock generator integrated with microprocessor

Abstract: A PLL based deskewed clock generator which may be fully integrated on a microprocessor is disclosed. The clock generator has a skew of less than 0.1 ns with peak to peak jitter of 0.3 ns using a 0.8 μm CMOS technology. The PLL comprises a phase frequency detector, charge pump, loop filter and voltage controlled oscillator from which the internal clock is generated. Since the PLL is on the same chip as the microprocessor, it is difficult to isolate the PLL from the noise generated by the microprocessor core logic and output buffers. Without an external filter, noise from the motherboard also influences the PLL. Power supply noise can cause a direct change in the frequency of the voltage controlled oscillator of the PLL. Circuits which overcome the adverse effects which would be created by such noises are also described.

Continuously tuneable frequency steerable frequency synthesizer having frequency lock for precision synthesis

Abstract: A frequency locked loop frequency synthesizer is comprised of a loop including a voltage controlled oscillator, a phase lock locked loop frequency detector, a divide by N counter and a low pass loop filter. A steering voltage is applied to the loop filter to produce a desired frequency or frequencies. The frequency lock loop frequency synthesizer drives the voltage controlled oscillator frequency to be N times the reference frequency. The frequency lock loop synthesizer inherently has 90 degrees less loop phase shift than a conventional phase lock loop. Additionally, the frequency lock loop frequency synthesizer provides a highly accurate, continuously tuneable, frequency synthesizer that includes a linear frequency detector in the frequency lock loop.

Radio with fast lock phase-locked loop

Abstract: A communication device (508) for use in a Time Division Multiplex (TDM) communication system (500) includes a transmitter, a receiver, and a frequency scanner for quickly scanning the radio frequency communication channels to determine an available channel. The communication device (508) also includes a phase locked loop (100) for providing a reference signal for the communication device (508) and locking to the available channel. This phase locked loop (100) includes a Voltage Control Oscillator (VCO) (104) having a control signal input (103). The phase locked loop (100) also includes a first filter (110) and a second filter (108). The first filter (110) has a wide frequency response. The second filter (108) includes a storage element (222) and has a narrow frequency response. The phase locked loop (100) also includes a switching circuit (106) which determines which one of the two filters (110, 108) gets coupled to the voltage control oscillator (104).

A high-frequency electronically tunable quadrature oscillator

Abstract: An architecture composed of mutually regenerative oscillators is introduced. It has been used to design a low-noise high-frequency voltage-controlled oscillator (VCO) capable of producing two output signals in quadrature with essentially identical properties. The phase relation between the quadrature outputs is frequency dependent and extremely stable. A novel way of coupling the regenerative oscillators is suggested in order to improve the frequency stability of the coupled oscillator system. Results obtained from a test chip have verified the viability of the oscillator concept. The oscillator circuit has been realized in a medium-frequency bipolar process. The tuning range extends to 500 MHz. At an oscillation frequency of 200 MHz, measured phase noise was -121 dBc/Hz at 1-MHz distance from the carrier. >

Information processing system

Abstract: PURPOSE:To decrease the timing loss for synchronization and to improve the performance of the system in the information processing system having plural semiconductor integrated circuits by providing a phase lock loop circuit for outputting a clock signal of a multiple frequency with respect to an inputted clock signal CONSTITUTION:In each semiconductor integrated circuit 7 - 10, in addition to a function block circuit of a CPU, etc, a phase lock loop circuit (PLL) 5 is integrated In such a state, a clock signal supplied to the circuit 5 through a clock line 11 is inputted to a phase comparator 16, compared with an output of a frequency dividing circuit 15, and its output signal is inputted to a voltage control oscillator (VCO) 18 through an LPF 17 Subsequently, a clock signal 131 outputted from the VCO 18 is inputted to the circuit 15, subjected to frequency division in a frequency division ratio set by control information from the CPU 1, and inputted to the comparator 16 That is, each circuit 5 has the frequency dividing circuit in the inside, and also, can control freely its frequency division ratio, therefore, the frequency of an outputted clock signal can be set to a multiple frequency of a clock signal generated by a clock generating circuit 6 Accordingly, a timing loss for synchronization is decreased, and the performance of the system can be improved

Adaptive phase locked loop

Abstract: A PLL system having a variable oscillator and apparatus for generating both phase and frequency error signals for controlling the variable oscillator, includes apparatus, responsive to the polarity of the frequency error signal, to selectively disconnect the frequency error signal from the variable oscillator when the PLL system approaches phase lock.

Controllable multi-phase ring oscillators with variable current sources and capacitances

Abstract: An electrically controlled oscillator circuit having multi-phase outputs with programmable frequency. The circuit includes a ring oscillator having a plurality of inverting stages. Each stage has an output which is connected to a switch that can be programmed to select one of a plurality of capacitors with different values to change the frequency range of the oscillator. Controlled current is fed to the stages to vary the frequency of the oscillator within a selected frequency range. Using capacitors to change the frequency range of the oscillator reduces variations of the oscillator output frequency.

Phase locked loop circuit

Abstract: PURPOSE:To obtain the phase locked loop circuit, for which pull-in is made easy even when mixing disturbance noise, by providing a means to suppress gain small at a phase comparator when a frequency component higher than a predictive frequency component is included in an external input. CONSTITUTION:When the mixture of disturbance noise is detected or estimated, the gain at a phase comparator 1 is suppressed small regardless of the function of a mode controller 4. Therefore, the output frequency of a voltage controlled oscillator does not exceed the pull-in limit because of the disturbance noise and when a frequency fi within the pull-in limit is inputted in place of the disturbance noise, pull-in is enabled. Thus, even when inputting the disturbance noise of the high frequency component to the phase comparator 1 which gain can be controlled to be increased/decreased, pull-in can be easily executed after the input.

A new PLL frequency synthesizer with high switching speed

Abstract: A phase-locked loop (PLL) frequency synthesizer with high switching speed is proposed. Mobile communication networks are evolving towards microcellulars operating in narrowband TDMA and microwave bands to meet the rapidly increasing demands for both voice and data services. Therefore, synthesizers with high switching speed are required for the realization. However, it will be difficult for conventional synthesizers to provide switching times of shorter than 1 ms. The PLL synthesizer proposed is composed entirely of digital signal processors except for a voltage-controlled oscillator (VCO). The VCO control signal is derived by the subtraction of the linear reference phase and the feedback phase; therefore, it does not need the band-limited loop filter which limits the ability of the loop to switch fast. The experimental results show that it can provide switching times as short as 0.1 ms, which is 10/sup 2/ approximately 10/sup 3/ times higher than conventional PLL synthesizers, and spurs of less than -60 dB. >

Current starved inverter voltage controlled oscillator

Abstract: A voltage controlled oscillator (VCO) operating as a variable length, variable delay, ring oscillator having a current starved inverter and an anti high-gain circuit for each stage. A VCO feedback signal is compared with a reference frequency obtained, for example, from a system crystal oscillator. A phase and frequency detector monitors these two input signals and issues "up" or "down" commands to a digital counter. This digital counter delivers select signals via a decoder and also drives a Digital to Analog Converter ("DAC"). The digital select signal from the counter chooses an operational stage from the multi-stage, tandem-connected VCO. A broadband operation for the VCO is achieved by overlapping the individual frequency ranges associated with each of the individual stages. The DAC moves the operation along each selected frequency range associated with a selected stage until a system lock between the VCO output and the crystal references is achieved.

Radio receiver for mobile reception with sampling rate oscillator frequency being an integer-number multiple of reference oscillation frequency

Abstract: Digital tuning of a locally generated frequency supplied to a frequency converting mixer, a mobile radio receiver is provided with great economy of components by utilizing the sampling rate oscillator for an analog-to-digital converter provided at the output of an analog intermediate frequency amplifier of the receiver as the source of the difference frequency for a phase locked loop (PLL) for control of the phase of a local oscillator for the mixer or mixers. All frequencies used to supply local oscillations to mixers, as well as the operating frequency of the phase locked loop are integer number multiples of the sampling rate pulse generator. Some division stages have fixed dividers and others have divisors selectable by a tuning processor and in some of the divisor connections it is useful to interpose a fixed or selectable-factor multiplier. A sampling rate of 42.75 MHz is recommended and an intermediate frequency amplifier frequency which is a rational number multiple of 57 kHZ, preferably 10.6875 MHz are similarly recommended.

Microwave oscillator with noise degeneration feedback circuit

Abstract: A microwave oscillator is shown to include an oscillator having an output and a control port and a feedback circuit disposed between the output and the control port of the oscillator. The feedback circuit includes a modulated laser, having an input and an output, the input responsive to a portion of a signal from the output of the oscillator and a photo detector having an input and an output, the input of the photo detector responsive to a signal from the output of the modulated laser delayed by a predetermined amount of time. The feedback circuit further includes a detector having a first and a second input and an output, the first input of the detector responsive to a signal from the output of the photo detector, the second input responsive to a portion of the signal from the output of the oscillator shifted in phase to be in phase quadrature with the signal at the first input of the detector and the output of the detector coupled to the control port of the oscillator. With such an arrangement, a microwave oscillator having improved FM noise performance than known microwave oscillators is provided.

Electro-acoustic hybrid integrated circuit and manufacturing method thereof

Abstract: An electro-acoustic hybrid integrated circuit such as a voltage controlled oscillator wherein a semiconductor substrate (1) having an active element is bonded directly to a surface acoustic wave resonator or a quartz oscillator as an electro-acoustic element by using silicon or silicon compound films formed on the semiconductor substrate and on the electro-acoustic element. This structure can be used for a high frequency circuit to be used for movable body communication or the like. The hybrid integrated circuit is small, light and has good productivity.

Dual phase-locked-loop having forced mid range fine control zero at handover

Abstract: Method and apparatus for controlling a PLL so that handover between fine and coarse loops take place at 2.5% of the nominal VCO frequency and where the coarse and fine loops error are combined in a summer circuit which employs a series circuit having a P-channel and N-channel FET with common drains and where the drains connected to the summer output node.

Method and apparatus for switching between gain curves of a voltage controlled oscillator

Abstract: A method and apparatus for switching between gain curves of a switched gain voltage controlled oscillator (VCO) 52, 52' or 52" In one form, the present invention uses a switched gain voltage controlled oscillator (VCO) 52, 52' or 52" which utilizes a ring oscillator A Gain Control signal is used to select between using a high gain curve and using a low gain curve The low gain curve is produced by selecting a high resistance path to either power or ground The high gain curve is produced by selecting a low resistance path to either power or ground

Frequency synthesizer having quick frequency pull in and phase lock-in

Abstract: A frequency synthesizer, including a phase-locked loop. The phase locked loop effects phase comparison between a comparison signal based on an output from a voltage-controlled oscillator and a reference signal based on an output from a reference oscillator. The resultant phase difference signal is submitted to a loop filter whose output serves as a control signal of the voltage-controlled oscillator. The frequency synthesizer includes a preset circuit for switching the output of the voltage-controlled oscillator by quickly charging or discharging a capacitor of the loop filter and a modifying circuit for modifying the time constant of the loop filter. The phase-locked loop is brought to phase lock at a high speed by decreasing the time constant of the loop filter when switching the output frequency.

Integrated mosfet resistance and oscillator frequency control and trim methods and apparatus

Abstract: In an integrated circuit system, a filter and an oscillator are referenced to a common reference circuitry through a suitable control loop to provide filter time constant and oscillator frequency references. The oscillator (Fig. 3) and the filter (Fig. 4) are implemented in a manner where the monolithic pattern elements setting the fundamental control parameters (time-period and time-constant respectively) are of the same type. Monolithic capacitors are used as one of the common passive elements between the oscillator and the filter to set the time-period and time-constants, respectively, adjustable through adjustment of control currents (Iosc, Ix). The monolithic implementation of the Control Block (Fig. 3, Fig. 4 and Fig. 7) is such that by tuning the oscillator frequency to the appropriate value through setting of the respective control current (Iosc), the filter time-constants also are appropriately set to satisfy the Nyquist criteria for a sampling rate referenced to the oscillator frequency.

FMCW radar system with linear frequency modulation

Abstract: It has been proposed in accordance with the invention to determine the linearity of the modulated oscillator frequency of an FMCW radar by means of the Hilbert transformation and to supply a control voltage, corresponding to the deviation, to the controllable oscillator via a digital/analog converter. A control and computing unit is used to determine the linearity of the modulated oscillator frequency.

Double conversion digital tuning system using separate digital numbers for controlling the local oscillators

Abstract: A double conversion tuning system for a high definition television receiver includes a microprocessor supplying first and second digital numbers to first and second local oscillators. The first local oscillator is controlled by a wide band phase locked loop that includes a programmable divider that receives the first digital number from the microprocessor and a prescaler that couples the first local oscillator signal to the programmable divider. The output of the programmable divider supplies one input of a phase detector, the other input of which is supplied with the divided down output of a crystal reference source. The output of the phase detector controls the first local oscillator frequency. The tuning of the first local oscillator is coarse and the first IF signal frequency may deviate within a predetermined range from a desired value. The second digital number from the microprocessor controls, via a D/A and varactor, the resonant frequency of a tunable dielectric resonator in the second local oscillator to adjust the second local oscillator frequency to compensate for the deviation in first IF signal frequency so that the second IF signal frequency remains constant.

Digital voltage controlled oscillator having a ring oscillator with selectable output taps

Abstract: A digital VCO is disclosed which comprises a ring oscillator formed of a plurality of inverters connected in series, each inverter being capable of controlling its delay amount, a frequency controlling circuit for controlling the oscillation frequency of the ring oscillator to coincide with a reference frequency, a selector switch for selecting specified output taps from output taps, each thereof being provided for each of the plurality of inverters, to take out the outputs therefrom, and switching control means for controlling the output taps from which the outputs are taken out to be cyclically switched through the selector switch.

VCO driven flyback converter for implantable cardoverter/defibrillator

Abstract: A battery powered cardioverter or defibrillator employing output capacitors for delivery of cardioversion or defibrillation pulses. The capacitors are charged by means of a step-up transformer, coupled and uncoupled from the battery by means of a voltage controlled oscillator which varies its off and on times as a function of the voltage on the battery and the voltage stored on the output capacitor to allow for rapid charging of the capacitor even under conditions of battery depletion. The voltage controlled oscillator is constructed to provide a highly accurate timing signal with a low current drain.

NRZ clock and data recovery system employing phase lock loop

Abstract: An improved NRZ clock and data recovery system lends itself to integration, includes a NRZ phase detector, an NRZ frequency detector and a lock detector, and provides automatic centering of the clock edge within the bit interval in a manner that is independent of analog delays and process and temperature variations NRZ data is applied to one side of an exclusive-OR gate (6) and a twice delayed (2, 4) version of the NRZ data is applied to the other side The output of the XOR gate (6), a "blivet" signal, is applied to a NRZ phase detector (10) comprising two AND gates (12,14), one of which (12) has as its other input a recovered clock signal output of a VCO (20) and the other of which has as its other input an inverted (16) version of the recovered clock signal The "up" and "down" outputs of the AND gates (10,12) indicate which direction a frequency control signal (26) should change the VCO (20) frequency A data holding flip-flop (28) whose input is a once delayed (2) version of the NRZ data is clocked with the recovered clock signal The NRZ frequency detector (50) monitors the state of the recovered clock signal on opposite edges (52,53) of the blivet to detect too-high (56), too low (55) and good (54) conditions The results of the detection can be ignored if a lock signal indicates that the phase lock loop is locked The lock detector (30) consists of a saturating up/down counter (42) that is incremented (38) by one when good blivets (32) occur and is decremented (40) by four when not-good blivets (36) occur

Voltage controlled oscillator suitable for complete implementation within a semiconductor integrated circuit

Abstract: An embodiment of the present invention is a voltage controlled oscillator (VCO) comprised of a differential pair of transistors that have respective positive feedback paths with phase-lead networks cross-coupled. Each positive feedback path on each side has two different phase-lead branches. The two phase-lead branches have the same phase differences on each side of the differential pair, in order to maintain a symmetry that improves common-mode noise rejection on a voltage control differential input. Current-steering is used to control the mixture of currents that arrive at the bases of the differential transistor pair from the respective two different phase-lead branches, and thereby changing the frequency of the VCO.