Showing papers on "Voltage-controlled oscillator published in 1993"

Fast settling phase locked loop

Abstract: A phase locked loop including a switch between a phase detector output and a VCO input to open the PLL during a frequency change is provided. While the PLL is open, an analog error correction signal is generated by sampling any residual error coming from the phase detector, and generating the analog error correction signal to counter the residual error. Once analog error correction signal is available, the switch is closed and the error correction signal is added to the phase detector output and the PLL is allowed to settle to an optimized frequency.

Calibration systems and methods for setting PLL gain characteristics and center frequency

Abstract: Calibration systems and techniques for phase-locked loops (PLLs) provide precise setting of the center frequency and/or uniform voltage controlled oscillator (VCO) gain characteristics. Center frequency is calibrated by imposing a selected center frequency at the output of the PLL and driving the control voltage V c across the PLL's filter to a predefined, steady state voltage indicative of PLL circuit calibration. The approach can be employed to calibrate any imposed VCO frequency output. VCO gain calibration is accomplished by employing the center frequency calibration technique only with a low frequency point imposed on the VCO output. A high frequency point on the transfer function is calibrated by applying a known voltage across the filter and driving the VCO output to a corresponding calibration frequency. Once a low frequency point and a high frequency point are calibrated, the slope of the VCO transfer function is defined. Various integrated PLL/calibration system embodiments are presented.

CMOS micromechanical resonator oscillator

Abstract: A completely monolithic high-Q oscillator, fabricated via a combined CMOS plus surface micromachining technology, is described, for which the oscillation frequency is controlled by a polysilicon micromechanical resonator to achieve stability and phase noise performance comparable to those of quartz crystal oscillators. It is shown that the closed-loop, steady-state oscillation amplitude of this oscillator can be controlled through the DC-bias voltage applied to the capacitively driven and sensed /spl mu/resonator. Measurements indicate a phase noise density level of -168 dBm/Hz at 5 kHz offset frequency for an oscillator carrier power of -14.5 dBm. >

Phase locked loop having plural selectable voltage controlled oscillators

Abstract: The invention discloses a PLL formed by a phase detector, a filter, three VCO's (VCO1, VCO2, and VCO3), a multiplexer, and a frequency divider. The VCO1, VCO2, and VCO3 have different mean frequencies, each oscillating at a frequency controlled according to the voltage value of a phase control signal from the filter. The multiplexer selects one of the VCO's which operate in parallel. If a pulse of a digital phase difference signal UP indicating that an internal signal is delayed in phase with respect to a reference signal is output twice in succession, or if a pulse of a digital phase difference signal DOWN indicating that an internal signal is advanced in phase with respect to a reference signal is output twice in succession, a counter makes the multiplexer change its current VCO selection via a shift register. Accordingly, high-speed PLL pulling is achievable even if a PLL frequency variable-range is expanded.

Voltage controlled oscillator operating with digital controlled loads in a phase lock loop

Abstract: A phase lock loop (16) operates independent of temperature and process variation by digitally loading a VCO (22) until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors (162-166, 174-180, 182-188) to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit (32) sets the loop node voltage to V DD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector (34) monitors the output frequency of the VCO and passes control signals to a load control circuit to (36) activate digital loads (38) and slow down the VCO to the desired operating frequency.

Video signal data and composite synchronization extraction circuit for on-screen display

Abstract: A composite synchronization extraction circuit is particularly suited for receiving composite video signals containing closed captioning data in raster scan line 21 by means of a signal CMOS integrated circuit device. A dual mode voltage clamp is realized in CMOS technology. The clamp includes temperature compensated current sources in the form of complementary current mirrors through which a clamped composite synchronization node of is charged and discharged, the output of which controls a transistor for charging the composite synchronization node. Detected pulse amplitude is set by slicing the incoming pulse at the back porch level and then doubling the amplitude with an amplifier and comparing that level with the back porch level as derived from a sample-and-hold device. The slice voltage level is maintained without an off-chip capacitor by an analog-digital-analog conversion process. Frequency and phase synchronization is accomplished by a combination of frequency lock loop and phase lock loop working in concert to generate a control voltage for a voltage controlled oscillator in a flywheel mode. The voltage controlled oscillator is not subject to noise in the incoming signal and provides a clean source of timing information for the circuit. The effects of impulse noise in the detection of the vertical retrace pulse are eliminated by the use of digital counting circuits to count the requisite number of horizontal synchronization pulses which occur between valid retrace pulses and to block pulses which appear at other times.

PLL design for a 500 MB/s interface

Abstract: When operating pins at high data rates, the key problem is to control timing skews (both on- and off-chip) so data on the pins can be read in a short time. The problem of external skews is solved by a clocking scheme where clock and data signals travel the same distance between the sender and receiver so that there is little skew on the 600-mV/sub pp/ external signals. There are two clocks: one for incoming data (RxClk) and one for outgoing data (TxClk). A PLL (phase-locked loop) generates the properly skewed internal clocks to operate the bus. The PLL consists of one main loop and two fine loops (one each for the receive and transmit clocks). The main loop is a VCO (voltage-controlled oscillator) based second-order loop using a 6-stage, small-swing, differential ring oscillator VCO. It is locked to the incoming RxClk after it is amplified to full CMOS levels. VCO and input clock frequency are halved to allow the phase/frequency detector more time to settle. The fine loop delays the internal clock (relative to the input RxClk) by an amount that causes the sampler to produce high and low outputs with precisely equal frequency, thereby compensating for sampler setup time. >

Voltage controlled oscillator (VCO) with symmetrical output and logic gate for use in same

Abstract: A voltage controlled oscillator (VCO) (23) includes a periodic signal generator (30) such as a comparator (42)followed by a latch (43), and a logic gate such as a NAND gate (31) connected to the output of the latch (43) to adjust for asymmetries in the output signals from the latch (43). In one embodiment, the NAND gate (31) includes two pullup transistors (80, 81) receiving first and second output signals from the latch and connected between a first power supply voltage terminal and an output node (86). Two switching branches (82, 83 and 84, 85) each including two transistors are connected between the output node (86) and a second power supply voltage terminal. The order of the input signals received by the two transistors is reversed between the two switching branches (82, 83 and 84, 85) to compensate for any duty cycle asymmetries. A frequency divider (32) divides the output of the NAND gate (31) to complete the duty cycle adjustment.

Filtering device for use in a phase locked loop controller

Abstract: A phase lock loop (PLL) frequency synthesizer is used in a radiotelephone to provide a reference frequency to a transmitter or a receiver. This particular PLL frequency synthesizer has a wide bandwidth control loop having a high current charge pump (417) and a narrow bandwidth control loop having a low current charge pump (411). A deadzone circuit (413) is used at an output of a phase detector (405) to control the application of an error signal to the high current charge pump (417). Additionally, the PLL frequency synthesizer utilizes a loop filter (419). The loop filter (419) receives two correction signals (409', 415') and provides a single control signal for the VCO (voltage controlled oscillator) (423). The loop filter contains two time constants formed from resistive and capacitive elements. The two time constants control the bandwidth of the two control loops.

Integrated phase locked loop local oscillator

Abstract: An embodiment of the present invention is a single-chip GPS receiver front-end comprising a radio frequency amplifier, a voltage-controlled oscillator operating at a first local oscillator frequency, a divide by seven and one-half counter for deriving a second local oscillator frequency from the first and a first and second mixer. The local oscillator frequency is mid-way between two carrier frequencies of interest that may be received by the radio frequency amplifier and the first mixer produces a first intermediate frequency. The second local oscillator frequency is then beat with the first intermediate frequency in the second mixer to produce a second intermediate frequency. A dual-conversion super heterodyne configuration is therefore employed in which the first and second local oscillator frequencies are derived from a single oscillator and the first local oscillator frequency is seven and one-half times the second local oscillator frequency.

New current-conveyor-based single-resistance-controlled/voltage-controlled oscillator employing grounded capacitors

Abstract: A new current conveyor (CC) based minimum-component oscillator structure has been proposed which provides the following advantageous features over the previously known minimum-component designs: (i) noninteracting control of frequency of oscillation through a single grounded resistor, (ii) easy convertibility into a voltage-controlled oscillator (iii) use of two grounded capacitors as preferred for IC implementation, (iv) availability of a buffered output, and (v) very good frequency stability.

A W-band single-chip transceiver for FMCW radar

Abstract: A monolithic microwave integrated circuit (MMIC) chip containing a W-band voltage controlled oscillator (VCO). transmit amplifiers, a receiver low noise amplifier and a mixer is discussed. It is used as the front-end of a homodyne FMCW radar for target range and range rate sensing applications. The 6.9-mm*3.6-mm monolithic chip was fabricated using 0.1- mu m pseudomorphic InGaAs-AlGaAs-GaAs HEMT process technology. The transmitter output power is more than 10 dBm for frequencies in the range 90-94 GHz, and maximum tuning bandwidth is 500 MHz for the VO. The receiver channel has 6-dB conversion gain when the output transmitting power is 10 dBm. A compete radar system has been tested based on the single-chip MMIC front-end. The calculated range and range rate are in good agreement with the measurement data. >

Lock recovery circuit for a phase locked loop

Abstract: A circuit (10) for providing recovery of a phase locked loop circuit when lock has been lost has been provided. The circuit includes a lock indicator circuit (24) for detecting when the phase locked loop circuit has lost lock on an input reference signal. When such loss has occurred, an override circuit (28) is rendered operative to decrease the voltage appearing at the input of a VCO within the phase locked loop thereby slowing down the frequency of the VCO and allowing the phase locked loop circuit to recover lock. Further, a logic circuit (30) detects when the voltage appearing at the input of the VCO has fallen below a predetermined threshold voltage and renders the override circuit non-operative.

Variable frequency ultrasonic generator with constant power output

Abstract: A generator for driving an ultrasonic transducer for use in ultrasonic cleaning The generator is based on a voltage controlled oscillator (26) which drives an output circuit which includes the ultrasonic transducer (22) The output circuit has a resonant frequency, and a resonance follower (30) produces a control voltage which tunes the voltage controlled oscillator to the resonant frequency Operating in conjunction with the automatic tuning elements is a constant power control which allows the user to set a desired power level, and monitors the actual output power by means of an output wattmeter circuit (32) to cause the actual output power to match the level selected by the user The constant output power circuit is effective even during resonance tracking of the system, or during frequency modulation of the ultrasonic output energy

Low phase noise oscillator frequency control apparatus and method

Abstract: A low phase noise third order phase lock loop which can track and eliminate microphonic disturbances and phase hits. The PLL utilizes a third order loop filter which incorporates two integrators. These two integrators, when coupled with the integration which occurs at the voltage control input of the voltage controlled oscillator within the PLL yield an open loop transfer function with a --18 dB/octave rolloff over a band of frequencies which at least encompasses the spectral content of the microphonic or phase hit phase noise disturbance to be eliminated. The open loop gain of the phase lock loop must be set high enough such that the phase lock loop does not oscillate and such that the loop converges and locks. The integrators are implemented with operational amplifiers with RC feedback networks. The values of the components in the RC feedback networks set the frequencies of two zeroes in the transfer function. The frequencies of these zeroes are set by proper selection of the R and C values to cause a change in slope of the open loop gain frequency response curve at the frequency of the zeroes from the -18 dB/octave rollof to a -6 dB/octave rolloff at the frequency of the zeroes. This causes the phase angle of the open loop PLL transfer function to be more positive than -180 degrees at the frequency at which the open loop gain magnitude frequency response curve falls to unity gain thereby achieving conditional stability. The open loop gain of the PLL is set such that the -18 dB/octave rolloff of the frequency response does not result in a gain of unity until a frequency is reached which is above the highest expected frequency deviation of the carrier caused by microphonic disturbances or phase hits. In the preferred embodiment, the gain is set high enough that the -18 dB/octave rolloff of the open loop gain frequency response extends over at least two decades and extends up to 10 kHz which encompasses substantially all the spectral content of the microphonic disturbance caused by package resonance which sources the phase noise to be eliminated.

Digital damping method and apparatus for phase-locked loops

Abstract: A damping circuit is described which includes a phase-and-frequency detector, a charge pump, a voltage-current oscillator and a capacitor. The phase-and-frequency detector generates UP and DOWN signals representative of a difference in phase between a pair of digital input signals. The charge pump varies an amount of charge carried within the capacitor in accordance with the UP and DOWN signals. The voltage controlled oscillator generates an output signal having a frequency controlled by both a voltage provided by the capacitor and by the UP and DOWN signals directly received from the phase-and-frequency detector. No analog damping resistor is required. Rather, the digital damping circuit is a digital circuit which generates adequate phase and frequency damping without a damping resistor. In this manner damping is achieved which is substantially unaffected by process parameters and operating and ambient parameters. Method embodiments of the invention are also described.

Clock recovery apparatus with means for sensing an out of lock condition

Abstract: An out of lock condition is sensed on a data transition by transition basis in clock recovery apparatus. When an out of lock condition is sensed, a range sweeping signal is generated and summed with the correction signal to sweep the frequency of the clock signal over the frequency range of the VCO. When an out of lock condition is absent, i.e., when the VCO is phase locked, simulated data transitions are generated in the frequency/phase detector. An out of lock condition is sensed by a D flip-flop. Data is coupled to the clock input of the flip-flop, the clock signal is delayed by a fraction of its nominal period and coupled to the D input of the flip-flop. The state of the Q output of the flip-flop indicates an out of lock condition.

Method and apparatus for providing the lock of a phase-locked loop system to a frequency sweep

Abstract: Synchronization of the output of an internally-driven VCO to an exterior clock signal is obtained by using the exterior clock signal to re-start the VCO at every exterior clock pulse, until the pre-set VCO frequency is reached. At that point, the re-starting of the VCO ceases, and the VCO locks onto the internal signal it is designed to track. One application of this circuit is for enabling a smooth transition between open-loop, ramp-up of a polyphase DC motor, enclosed-loop operation of the motor to closed loop operation. Implementation of the circuit described phase-synchronizes the output of a phase-switching PLL loop, which is tracking the back emf of the motor, to the external clock used for motor ramp-up, so that there is no "jolt" in the motor at the transition from open-loop to closed-loop operation of the motor.

Frequency synthesizing phase lock loop with unvarying loop parameters

Abstract: A PLL frequency synthesizer utilizes circuitry for altering pump current magnitude based upon division factors in the PLL. In one embodiment, pump current magnitude is responsive to the feedback division factor path, providing a constant gain over a wide frequency range, thereby providing a constant natural frequency and damping. In another embodiment, pump current magnitude is controlled as a function of both feedback and feedforward division factors, thereby maintaining a constant natural frequency with respect to the output frequency. In another embodiment, the output frequency is proportional to the VCO control signal raised to a power, with charge pump current controlled as a function of the feedforward division factor thus providing a natural frequency and damping factor which is constant with respect to output frequency. In another embodiment, gain control is provided as a function of at least one division factor in a PLL loop which does not utilize a charge pump. In one embodiment, a gain control circuit provides a gain control signal to at least one of a phase comparator and the variable frequency oscillator. In another embodiment, a gain control circuit provides a gain control signal to at least one adjustable gain stage.

Circuit and method of controlling a VCO with capacitive loads

Abstract: A phase lock loop operates independent of temperature and process variation by digitally loading a VCO until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit sets the loop node voltage to V DD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector monitors the output frequency of the VCO and passes control signals to a load control circuit to activate digital loads and slow down the VCO to the desired operating frequency.

Frequency modifier for a transmitter

Abstract: A transmitter has an oscillator (101, 201, 303, 401, 501) that operates at frequency k multiplied by f c , thus the oscillator (101, 201, 303, 401, 501) outputs a signal at an output frequency, kf c . Coupled to the oscillator (101, 201, 303, 401, 501) is a frequency modifier (103, 205, 307, 405, 505), for modifying the oscillator output frequency by factor 1/k, thereby producing a signal at frequency f c at the frequency modifier output. Coupled to the frequency modifier output is a modulator (105, 215, 301, 407-417, 507-517) for producing a modulated output signal substantially centered at frequency f c .

VCO and buffer having noise filter on power supply line

Abstract: A voltage-controlled oscillation circuit includes a power supply terminal for supplying power to an oscillation stage, a buffer stage, and an output matching stage. Connected between the power supply terminal and ground is a high frequency bypass capacitor for bypassing electrical noise superimposed on the power supply to the side of ground, a voltage feedback resistor is connected in series in a power supply line connected to the power supply terminal, the high frequency bypass capacitor and the voltage feedback resistor constitute a low-pass filter, and the capacitance value of the high frequency bypass capacitor and the resistance value of the voltage feedback resistor are determined so that the cut off frequency of the low-pass filter is at most the frequency f0 of noise.

FSK modulating apparatus

Abstract: An FSK modulating apparatus includes a first phase locked loop arrangement having a first voltage controlled oscillator for generating a space frequency signal of a modulation signal and a second phase locked loop arrangement having a second voltage controlled oscillator for generating a mark frequency signal of the modulation signal. The apparatus also includes a third voltage controlled oscillator used to produce an FSK modulated output signal. After input data changes frequency to a space frequency or a mark frequency, a control voltage for the phase locked loop arrangement that is associated with the resulting frequency is routed through a low pass filter having a flat group delay characteristic to the third voltage controlled oscillator. After a set period of time has elapsed, the third voltage controlled oscillator replaces the voltage controlled oscillator of the particular phase locked loop arrangement associated with the current state of the modulator signal.

Digital voltage controlled oscillator

Abstract: A digital phase lock loop is provided, comprising a digital voltage controlled oscillator, a phase detector, and an up/down counter The digital voltage controlled oscillator is responsive to a first set of control signals received from the up/down counter to provide an output signal The phase detector receives and compares the frequency of the output signal with the frequency of a reference signal and, based on the comparison, outputs to the up/down counter a second control signal which determines the status of the first set of control signals The digital voltage controlled oscillator comprises (i) an array of delay elements and (ii) a decoder for receiving the first set of the control signals from the up/down counter and for selectively activating one or more of the delay elements in response thereto The decoder provides a separate output line for each of the delay elements which is to be selectively activated The logic required to implement the decoder requires only a single AND gate and a single OR gate for each of the delay elements in the array

Time acquisition system with dual-loop for independent frequency phase lock

Abstract: A time acquisition system is disclosed with dual independent frequency and phase lock loops, each containing a dedicated voltage controlled oscillator (VCO). The frequency lock loop (FLL) outputs a frequency bias signal, used for coarse frequency lock-up, only when the difference frequency between the input signal and the FLL VCO is outside a predetermined frequency band -ΔωL to ΔωL. Significantly, the frequency bias signal is equal to zero when the difference frequency between the input signal and the FLL VCO is inside the frequency band -ΔωL to ΔωL. The phase lock loop (PLL) provides a phase bias signal, used for fine tuning lock-up, when the difference frequency between the input signal and the PLL VCO is inside the predetermined frequency band -ΔωL to ΔωL. Therefore, there is no interaction between loops during the final phase tuning lock-up.

Quasi-optical VCOs

Abstract: Quasi-optical grid voltage controlled oscillators (VCOs) are presented. These VCOs are the first demonstration of a quasi-optical system consisting of several periodic arrays loaded with solid-state devices. A quasi-optical VCO consists of an array of oscillators, a variable capacitance array, and a mirror. The mirror provides feedback for locked power-combining of a large number of MESFET oscillators that load a two-dimensional metal grid on a dielectric substrate. The frequency can be electrically tuned either with gate bias or with another array loaded with varactor diodes. When the varactor bias voltage is changed, the capacitance of the diodes changes, which in turn modulates the frequency of the output power-combined wave. Two types of arrays are presented, one consisting of short dipoles, and the other of bow-tie elements. As expected, the bow-tie VCO has better performance than the dipole VCO, due to its broadband impedance. A 10% tuning bandwidth with less than 2 dB power change was measured in the case of a bow-tie VCO. >

Method and apparatus for performing frequency acquisition in all digital phase lock loop

Abstract: A method and apparatus for performing frequency acquisition. Frequency acquisition is accomplished by utilizing binary-search techniques with a controller (13), variable digital oscillator (16), frequency detector (11) an incrementor (19) and decrementor (21) and control registers (22). The frequency detector (11) generates an output indicating the relative speed of the variable oscillator (16) with reference to a externally provided signal. Depending on the output of the frequency detector (11 ), the arithmetic logic circuitry (19, 21) will increase or decrease the value in a control register (22), resulting in a corresponding increase or decrease in speed of the variable oscillator (16). The magnitude of changes to the control register (22) is gradually reduced as the steps of frequency detection and arithmetic updates are repeated until the variable oscillator (16) has reached the proper frequency.

Frequency synthesizer with comb spectrum mixer and fractional comb frequency offset

Abstract: A frequency synthesizer has the configuration of a phase locked loop (PLL) having a voltage controlled oscillator (VCO) generating an output signal, a phase detector for outputting a control signal to the VCO, and circuitry coupled to an output port the VCO for offsetting the frequency of a sample of the output signal. The synthesizer includes a sampling mixer operative with a source of reference signal and interconnecting the offset circuitry with the phase detector. The sampling mixer mixes the offset sample with the reference signal to output a comb frequency spectrum of signals differing in frequency from each other by multiples of the reference frequency. A filter selects a signal outputted by the sampling mixer at one of the comb frequencies for application to the phase detector. The phase detector is operative with a source of input signal having an input signal frequency for phase locking with the signal selected by the filter. The PLL includes a stabilizing loop filter circuit preceding the VCO and having means for adjusting a value of the control signal to tune the frequency of the output signal. In the offset circuitry, inphase and quadrature portions of the output sample are mixed with either the reference frequency or a fraction thereof, as selected by a switch, and are summed to provide the offset frequency sample to the sampling mixer.

Phase locked loop frequency modulator using fractional division

Abstract: A frequency modulation circuit includes a phase-locked loop having a reference frequency input and a controlled frequency output. The phase-locked loop has a phase detector, a filter and a voltage-controlled oscillator and, in a feedback path between the output and the phase detector, a frequency divider. Also included is a converter converting an input signal to a digital modulation signal M, and an adder inverting the most significant bit of the digital modulation signal and adding it to a digital word representing a selected frequency. The frequency divider divides a fractional number (N.F)±M, where N is an integer, F is a fraction and M is the digital value of modulation data. This configuration is advantageous because data can be taken directly from the analog-to-digital output to the adder with no data translation, the modulation signal M could also be provided from a processor data bus, the peak deviation is selectable, and no carrier offset results from injecting the modulation signal into the phase-locked loop.

Squid control apparatus with non-cryogenic flux-locked loop disposed in close proximity to the squid

Abstract: SQUID control apparatus for controlling multiple SQUID probes includes a plurality of head units each corresponding to a respective SQUID probe, each of the head units including a non-cryogenic modulated flux-locked loop feedback circuit operating at a respective modulation frequency. The apparatus also includes a base unit coupled to all of the head units, the base unit providing control signals to control the multiple head units. Means are also provided, such as through the use of a daisy chain topology, for synchronizing the modulation frequency of all of the modulated flux-locked loop feedback circuits. The head units may also contain a phase shifter coupled to phase shift the modulation frequency oscillator signal for provision to the local oscillator input of a demodulator, and the phase shifter may include a shifting filter for filtering the oscillator signal to reduce all frequency components except a fundamental frequency component, and for phase shifting the fundamental frequency component by a desired amount, and shaping means for shaping the filtered and shifted signal into a square wave.