Showing papers on "Voltage-controlled oscillator published in 1997"

A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors

Abstract: A completely integrated 1.8-GHz low-phase-noise voltage-controlled oscillator (VCO) has been realized in a standard silicon digital CMOS process. The design relies heavily on the integrated spiral inductors which have been realized with only two metal layers and without etching. The effects of high-frequency magnetic fields and losses in the heavily doped substrate have been simulated and modeled with finite-element analysis. The achieved phase noise is as low as -116 dBc/Hz at an offset frequency of 600 kHz, at a power consumption of only 6 mW. The VCO is tuned with standard available junction capacitances, resulting in a 250-MHz tuning range.

A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications

Abstract: A monolithic 1.9-GHz, 198-mW, 0.6-/spl mu/m CMOS receiver which meets the specifications of the Digital Enhanced Cordless Telecommunications (DECT) standard is described. All of the RF, IF, and baseband receiver components, with the exception of the frequency synthesizers, have been integrated into a single chip solution. A description is given of a wide-band IF with double conversion architecture which eliminates the need for the discrete-component noise and IF filters in addition to facilitating the eventual integration of the frequency synthesizer blocks with on-chip VCO's. The prototype device utilizes a 3.3-V supply and includes a low noise amplifier, an image-rejection mixer, and two quadrature baseband signal paths each of which includes a second-order Sallen and Key anti-alias filter, an eighth-order switched-capacitor filter network followed by a 10-b pipelined analog-to-digital converter (ADC). The experimental device has a measured receiver reference sensitivity of -90 dBm, an input referred IP3 of -7 dBm, a P/sub -1 dB/ of -24 dBm, and an image-rejection ratio of -55 dBc across the DECT bands.

Jitter in ring oscillators

Abstract: Jitter in ring oscillators is theoretically described, and predictions are experimentally verified. A design procedure is developed in the context of time domain measures of oscillator jitter in a phase-locked loop (PLL). A major contribution is the identification of a design figure of merit /spl kappa/, which is independent of the number of stages in the ring. This figure of merit is used to relate fundamental circuit-level noise sources (such as thermal and shot noise) to system-level jitter performance. The procedure is applied to a ring oscillator composed of bipolar differential pair delay stages. The theoretical predictions are tested on 155 and 622 MHz clock-recovery PLL's which have been fabricated in a dielectrically isolated, complementary bipolar process. The measured closed-loop jitter is within 10% of the design procedure prediction.

Digital compensation for wideband modulation of a phase locked loop frequency synthesizer

Abstract: A digital compensation filtering technique is provided that enables indirect phase locked loop modulation with a digital modulation data stream having a bandwidth that exceeds, perhaps by an order of magnitude, the bandwidth characteristic of the phase locked loop. A modulation data receiver is provided for receiving from a modulation source digital input modulation data having a bandwidth that exceeds the cutoff frequency characteristic of the phase locked loop frequency response. A digital processor is coupled to the modulation data receiver for digitally processing the input modulation data to amplify modulation data at frequencies higher than the phase locked loop cutoff frequency. This digital processor is connected to the phase locked loop frequency divider to modulate the divider based on the digitally-processed input modulation data, whereby a voltage controlled oscillator of the phase locked loop is controlled to produce a modulated output carrier signal having a modulation bandwidth that exceeds the phase locked loop cutoff frequency. The digital processing of the modulation data can be implemented by adapting a digital FIR Gaussian transmit filter such that its filter characteristic reflects the intended modulation data amplification as well as enables Gaussian Frequency Shift Keyed modulation. With this implementation, no additional componentry beyond the PLL system is needed to implement the digital modulation data processing provided by the invention.

Phase noise in coupled oscillators: theory and experiment

Abstract: Phase noise in mutually synchronized oscillator systems is analyzed for arbitrary coupling and injection-locking topologies, neglecting amplitude noise, and amplitude modulation (AM) to phase modulation (PM) conversion. When the coupling phase is chosen properly (depending on the oscillator model), the near-carrier phase noise is reduced to 1/N that of a single oscillator, provided the coupling network is reciprocal. This is proved In general, and illustrated with specific cases of globally coupled and nearest-neighbor coupled oscillator chains. A slight noise degradation is found for unilaterally coupled (nonreciprocal) chains. The 1/N reduction for reciprocal coupling applies over nearly the entire range of free-running frequency distributions required for beam-scanning, and is verified experimentally using a linear chain of coupled GaAs MESFET voltage-controlled oscillators (VCOs) operating at X-band. The effect of a nonoptimum coupling phase on the phase noise of the system is also studied. As the coupling phase deviates from the optimum value, the phase noise increases significantly near the locking range edge for noise offset frequency near the carrier.

Phase locked loop (PLL) with linear parallel sampling phase detector

Abstract: A parallel sampling phase detector with linear output response is disclosed. The parallel sampling phase detector for use in data recovery. The device includes a voltage controlled oscillator (VCO) that generates ten separate phase signals using a five stage ring oscillator. Five linear phase detectors are employed in the device, each operating during one of five "window" intervals. The "window" intervals are non-overlapping, and are generated using preselected ones of the VCO output phases. The linear phase detectors each generate, respectively, a variable pulsewidth pump up signal wherein the pulsewidth of the pump up signal is proportional to a phase difference between the input data signal applied to the phase detector, and the output phase signals of the VCO. Each phase detector also generates a pump down signal that has a fixed pulsewidth. A loop filter determines the difference between the pump up and pump down signals and develops a control signal to vary the output frequency and phase of the VCO in accordance therewith. Each phase detector also operates as a deserializer, capturing, during the interval when the respective "window" signal is active, the data signal from the input data stream. The plurality of sampled data signals are captured by a data register, which then outputs an n-bit (5-bit) parallel format data word. The linear phase detector includes means for generating the pump down signal in response to the generation of the pump up signal.

Clock signal from an adjustable oscillator for an integrated circuit

Abstract: An integrated circuit is described which has circuitry to detect environmental conditions such as temperature and supply voltage and adjust the operation of the circuit accordingly. A flash memory system is described which includes a temperature detector and a supply voltage detector. The memory monitors temperature and voltage and adjusts an oscillator circuit to maintain an ideal operating frequency. The oscillator includes adjustable delay stages which can be selectively fed back to adjust operating frequency. To save power, unused delay stages of the oscillator can be disabled. Oscillator calibration circuitry, a temperature detector, and a voltage detector are described.

Frequency synthesizer with temperature compensation and frequency multiplication and method of providing the same

Abstract: A frequency synthesizer (200) with temperature compensation and frequency multiplication. The synthesizer (200) having a temperature uncompensated frequency oscillator (202) coupled to a phase locked loop (206) including at least one temperature compensating and frequency multiplication element (208). The element (208) preferably being a multi-modulus divider. The element (208) is programmed by a control circuit (210) to vary as a function of temperature and to vary as a function of a fractional frequency multiplication factor. The element (208) also may provide adjustment of the nominal frequency of the frequency oscillator (202). The frequency oscillator (202) and preferably all the elements of the synthesizer (200) are temperature-compensated by the element (208) to produce a multiplied and temperature-compensated frequency output.

A fully integrated spiral-LC CMOS VCO set with prescaler for GSM and DCS-1800 systems

Abstract: A set of two VCOs is developed in a 0.4 /spl mu/m CMOS process, using a fully integrated spiral inductor with symmetrical octagonal shape in the resonance LC-tank. One VCO operates at a 900 MHz center frequency, and the other at 1.8 GHz, both achieving the required phase noise spec and tuning range for the GSM and DCS-1800 system. The phase noise equals -108 dBc/Hz at 100 kHz offset for the 900 MHz version and -113 dBc/Hz at 200 kHz for the 1.8 GHz version. The power consumption is 9 and 11 mW. An eight-modulus prescaler operates together with both VCOs.

A balanced 1.5 GHz voltage controlled oscillator with an integrated LC resonator

Abstract: A monolithic voltage-controlled oscillator (VCO) is presented for low-power digital radio handsets. This circuit is fabricated in a production 0.8/spl mu/m 11GHz f/sub T/ BiCMOS process. The VCO is based on the common-collector Colpitts circuit in a balanced configuration to provide differential output for direct compatibility with prescaler and double-balanced mixer inputs. The circuit utilizes an integrated LC resonator comprised of coplanar inductors, polysilicon capacitors, and on-chip varactors. The fully-integrated inductors have an unloaded Q of approximately 5 at 2GHz.

Subharmonic quadrature sampling receiver and design

Abstract: A receiver for down-converting a modulated carrier into its in-phase (I) and quadrature (Q) components for further processing is proposed. This is accomplished using a sampling method in which the signal is sampled directly using a sampling circuit which is driven by a single sampling clock frequency substantially lower than the carrier frequency while allowing the I and Q components to be precisely obtained. Each of the signal samples comprises sub-samples taken successively which represent the in-phase, quadrature, negative in-phase and negative quadrature components of the signal. The negative components permit flexible application of the invention in several modes, including differential mode for the removal of common-mode noise. The invention is useful because it provides an integrated circuit means for precisely obtaining I and Q components of a very high frequency modulated carrier. This greatly eases the difficulty of implementing receiver architectures such as direct down-conversion or low-IF receivers, which permit on-chip integration of traditionally difficult-to-integrate components such as IF filters and VCO circuits while eliminating the need for image-rejection filters.

A 2.7 V GSM RF transceiver IC

Abstract: A 2.7-V RF transceiver IC is intended for small, low-cost global system for mobile communications (GSM) handsets. This chip includes a quadrature modulator (QMOD) and an offset phase locked loop (OPLL) in the transmit path and a dual IF receiver that consists of a low noise amplifier (LNA) with an active-bias circuit, two Gilbert-cell mixers, a programmable gain linear amplifier (PGA), and a quadrature demodulator (QDEM). The IC also contains frequency dividers with a very high frequency voltage controlled oscillator (VHF-VCO) to simplify the receiver design. The system evaluation results are the phase error of 2.7/spl deg/ r.m.s. and the noise transmitted in the GSM receiving band of -163 dBc/Hz for transmitters and the reference sensitivity of -105 dBm for receivers. Power-control functions are provided for independent transmit and receive operation. The IC is implemented by using bipolar technology with f/sub T/=15 GHz, r'/sub bb/=150 /spl Omega/, and 0.6-/spl mu/m features.

GMSK modulator formed of PLL to which continuous phase modulated signal is applied

Abstract: A Gaussian Minimum Shift Keying modulator that provides direct modulation of a carrier signal, produced by a single microwave high power voltage controlled oscillator. A continuous phase frequency shift keyed modulated signal with a modulation index of 0.5 is produced at the desired output frequency using a full 360 degree linear continuous phase modulator, controlled by a linear baseband signal that is the integral of the binary baseband information signal. This modulated signal is used as the reference signal for a phase locked high power voltage controlled oscillator. The phase locked loop provides frequency tracking and Gaussian spectral shaping to the modulated output signal.

Single chip RF tag oscillator circuit synchronized by base station modulation frequency

Abstract: A Radio Frequency (RF) transponder (tag), method, and system, whereby the tag has a low current tag oscillator, the oscillation frequency of the tag oscillator set by RF signal from a base station.

Clock recovery circuit

Abstract: A clock recovery circuit that can be used for recovering a clock signal from a data stream having a high data rate. The clock recovery circuit has a phase interpolator and non-linear digital to analog converters. These circuits are used to interpolate between the phases produced by a voltage controlled oscillator. A determination to advance or hinder a currently selected phase can be made using an up/down detector, a divider, and control logic. The divider can divide not only the up and down pulses produced by the up/down detector, but also the clock frequency. By dividing the clock frequency, the control logic can be designed using CMOS logic circuits.

Random number generator

Abstract: A random number generator using, for example, a voltage controlled oscillator (VCO) which receives a noise input and at least one differential oscillator. The differential oscillator(s) provided oscillator signals to a differential sense amplifier which is sampled under control of the VCO.

Oscillator circuit with first and second frequency control elements

Abstract: A controllable-frequency oscillator has a first portion for generating a signal having a controllable frequency. The controllable-frequency oscillator has a second portion for controlling the frequency of the signal generated by the first portion in response to a first control signal. The controllable-frequency oscillator has a third portion for controlling the frequency of the signal generated by the first portion in response to a second control signal separate from the first control signal.

Frequency converter for outputting a stable frequency by feedback via a phase locked loop

Abstract: A frequency converter capable of providing a highly stable frequency by frequency feedback using a phase locked loop circuit. The frequency converter includes a local oscillator; a frequency converter for mixing an output of the local oscillator and a feedback frequency therefrom to generate a mixed frequency; a first filter for filtering the mixed frequency; a phase comparator for generating a voltage signal corresponding to a phase difference in between an input frequency to the frequency convertor and the output frequency of the first filter; a second filter for converting the voltage signal of the phase comparator to a constant polarity voltage and eliminating any noise component of the converted voltage signal; and a voltage controlled oscillator receiving the output of the second filter as a control voltage so as to provide a stable output frequency by generating the feedback frequency responsive to the control voltage.

Silicon bipolar VCO family for 1.1 to 2.2 GHz with fully-integrated tank and tuning circuits

Abstract: This work introduces fully-integrated VCOs implemented in the mature ISOSAT silicon bipolar RFIC process. The ISOSAT silicon bipolar process has transistors with 15GHz f/sub T/ and 30GHz f/sub max/, along with MIS capacitors of Q > 50 and spiral inductors with Q up to 10 for the values and frequency range of interest. Recently, a voltage-variable capacitor (or varactor) was characterized within the process. This device has up to 3:1 capacitance range from 0 to 3V reverse bias and also has Q of 3060 in the 1.1-2.2GHz frequency range desired for these VCOs.

A micromachine-based RF low-noise voltage-controlled oscillator

Abstract: A voltage-controlled oscillator (VCO) employs an aluminum micromachined variable capacitor for frequency tuning. Unlike conventional varactor diodes, the capacitor is fabricated on a silicon substrate and thus amenable to monolithic integration with a standard IC process. Experimental capacitors achieve a 16% tuning range with a nominal capacitance value of 2 pF and a quality factor above 60 at 1 GHz. A prototype VCO exhibits -107 dBc/Hz phase-noise at 100 kHz offset frequency from the carrier. The center frequency of 714 MHz and 14 MHz tuning range are limited by the test setup.

Clock/data recovery PLL using half-frequency clock

Abstract: A CMOS clock and data recovery PLL is described for serial nonreturn-to-zero (NRZ) data transmission. The voltage controlled oscillator (VCO) works at half the data rate, which means for a 1-Gb/s data rate, the VCO runs at 500 MHz. A specially designed phase comparator uses a delay-locked loop (DLL) to generate the required sampling clocks to compare clock and data. The VCO can typically be tuned from 350 MHz to 890 MHz, and the phase-locked loop (PLL) locks between 720 Mb/s and 1.3 Gb/s. Data recovery is error free up to 1.2 Gb/s with a 9-b pseudorandom data sequence. The core consumes 85 mW (3.3 V) at 1 Gb/s.

CMOS VCO's for PLL frequency synthesis in GHz digital mobile radio communications

Abstract: CMOS inductorless voltage controlled oscillator (VCO) design is discussed with the emphasis on low-noise, low-power, gigahertz-range circuits suitable for portable wireless equipment. The paper considers three VCO structures-one simple ring oscillator and two differential circuits. The design methodology followed optimization for high-speed and low-power consumption. The proposed linearized MOSFET model allows the accurate prediction of the operating frequency while the phase noise evaluation technique makes it possible to determine, through simulation, the relative phase-noise performance of different oscillator architectures. The measurement results of three VCO's implemented in 1.2-/spl mu/m CMOS technology confirm with the simulation predictions. The prototype VCO's exhibits 926-MHz operation with -83 dBc/Hz phase noise (@ 100 kHz carrier offset) and 5 mW (5 V) power consumption.

Method and system for calibrating a crystal oscillator

Abstract: A method and system are provided for calibrating a batch of devices each containing a circuit which is responsive to a control signal for producing a desired output which varies in accordance with a first predetermined function of a specific ambient condition, the control signal having a magnitude which varies as a second predetermined function of the specific ambient condition, the second function being based on data stored as a look-up table in a memory of the device and which must be individually calibrated for each device. In a preferred embodiment, the device is a digital temperature controlled crystal oscillator which produces a desired output frequency and includes a voltage controlled oscillator (VCO) responsive to a control signal having a magnitude which varies as a predetermined function of ambient temperature in order to compensate for temperature variations in the oscillator output frequency. For such an application, the invention requires the connection of an accurate frequency source to each oscillator in the batch so as to enable the output frequency of the oscillator to be equalized thereto or to a multiple thereof. In calibration mode, the digital equivalent of the resulting analog control voltage is stored; whilst in compensation mode it is extracted from the memory, converted to an equivalent analog voltage and applied to the VCO. The invention is also applicable to compensate for aging of crystal oscillators in the field without requiring reconfiguring the complete look-up table.

Ideal phase-locked-loop (PLL) operation of a 10 GHz erbium-doped fibre laser using regenerative modelocking as an optical voltage controlled oscillator

Abstract: Ideal phase-locked-loop (PLL) operation of a 10 GHz erbium doped fibre laser has been achieved for the first time by using a voltage controlled regenerative modelocking technique. The repetition rate of the regeneratively modelocked fibre laser in a free running condition can be continuously varied by changing the voltage supplied to the PZT to change the fibre cavity length. PLL operation is achieved by feeding back a phase sensitive error signal to the PZT. This signal is obtained by mixing a laser clock signal with a synthesizer signal. The external signal tracking range is 40 kHz.

Dual band transceiver

Abstract: A dual band transceiver for operating in a first lower frequency band such as the band allocated to cellular systems, and in a second higher frequency band such as the band allocated to personal communication services (PCS) systems (as shown in Figs. 2-4). In a representative embodiment, the dual band transceiver (108 and 118) comprises a main voltage controlled oscillator (VCO) (134) for generating a local oscillator (LO) signal; an offset VCO (136) for generating an offset frequency (OF) signal; a first mixer (132) for combining the LO signal with the OF signal to produce a first transmit signal; a modulator (130) for modulating the first transmit signal with a data signal to produce a first data modulated transmit signal; and a second mixer (154) for combining the first data modulated transmit signal with the LO signal to produce a second data modulated signal. The main VCO (134) and the offset VCO (136) can be programmed such that the first data modulated transmit signal is in the first band and the second data modulated transmit signal is in the second band.

A wide band tuning system for fully integrated satellite receivers

Abstract: The building blocks for a low power tuning system that reduces the phase noise of integrated VCO's are described. The multi-modulus prescaler, the phase frequency detector and the wide band charge pump were integrated in a standard bipolar technology with 9 GHz npn-transistors and 200 MHz pnp-transistors. The maximum input frequency of the multi-modulus prescaler is 3 GHz, the maximum reference frequency of the phase frequency detector is 380 MHz and the -3 dB bandwidth of the charge pump is 41 MHz at a reference frequency of 300 MHz. The achieved performance enables use of noisy integrated VCO's for reception of satellite digital signals.

Interference-free broadband television tuner

Abstract: An interference free local oscillator circuit is disclosed A first local oscillator signal is generated in a first phase locked loop A second local oscillator signal is generated in a second phase locked loop Third and fourth phase locked loops provide inputs to the second phase locked loop to control the second local oscillator frequency The operating frequencies of the first and second local oscillator signals are selected so that spurious signals generated in the phase locked loops do not interfere with a received RF signal in a conversion circuit

GHz transceiver phase lock loop having autofrequency lock correction

Abstract: A transceiver circuit used in connection with a fiber channel serial interface is designed and constructed with transmitter and receiver phase lock loop sections, each acquiring velocity lock with respect to a 106.25 MHz reference clock signal. The transmitter phase lock loop section is maintained in velocity lock during serialization of a 10-bit encoded transmission character. The receiver phase lock loop section is operative in a phase-only mode during de-serialization and byte synchronization of a 1.0625 GHz serial data stream. VCO control voltages of both the transmitter and receiver phase lock loop sections are monitored and evaluated by a comparison circuit such that if the receiver phase lock loop section looses lock, its VCO control voltage will exceed a pre-determined lock range value, triggering an output of the comparison circuit. The output trigger of the comparison circuit automatically commands the receiver phase lock loop section to reacquire velocity lock and maintains the receiver phase lock loop section in velocity lock mode until such time as the receiver VCO control voltage returns to about its nominal value. Frequency lock correction is applied to the receiver phase lock loop section automatically and is a function solely of the receiver phase lock loop frequency deviation from its nominal value.

A 0.9-2.2 GHz monolithic quadrature mixer oscillator for direct-conversion satellite receivers

Abstract: External tank circuits including varicaps are often employed in satellite receiver ICs. These circuits require external components and an expensive 30 V tuning voltage supply. This fully-integrated quadrature current-controlled oscillator (QCCO), quadrature mixer, and V/I converter with band switch circuit uses a standard BiCMOS process, (f/sub /spl sim//5GHz) the tuning range of 80% covers the satellite band with a VCO gain of 150MHz/V/spl plusmn/35%. The band switch circuit divides the frequency range of 0.9-2.2 GHz into four bands, each with a tuning voltage range from 0 V up to 3.5 V.

Fiber optic micro-doppler ladar system and operating method therefor

Abstract: A micro-doppler ladar system for identifying and analyzing a target of interest includes a transmitter and coherent receiver pair, each of which includes a fiber optic power amplifier, and a controller. Preferably, the transmitter includes a master oscillator for generating a primary laser beam, a voltage controlled oscillator (VCO) for generating a VCO signal having a predetermined, repetitive frequency pattern, a frequency shifting circuit for varying the frequency of the primary laser beam responsive to the VCO signal to thereby produce a frequency-varying primary laser signal, and the optical fiber amplifier, which amplifies the frequency-varying primary laser signal to thereby produce a transmit laser beam. In addition, the coherent receiver, which responds to backscattered light produced by the interaction of the transmit laser beam with the target of interest, includes an optical fiber pre-amplifier for amplifying the backscattered light to thereby produce an amplified return laser beam, and a phase locked loop receiving the primary laser beam and the amplified return laser beam for generating an electrical signal indicative of range, velocity and a characteristic signature of the target of interest. The transmitter and coherent receiver can be operated in a target acquisition mode of operation for determining range and velocity, and a signature acquisition mode of operation for determining a characteristic signature of the target of interest responsive to the electrical signal. A method for operating the micro-doppler ladar system is also described.