Showing papers on "Voltage-controlled oscillator published in 1999"

An integrated CMOS micromechanical resonator high-Q oscillator

Abstract: A completely monolithic high-Q oscillator, fabricated via a combined CMOS plus surface micromachining technology, is described, for which the oscillation frequency is controlled by a polysilicon micromechanical resonator with the intent of achieving high stability. The operation and performance of micromechanical resonators are modeled, with emphasis on circuit and noise modeling of multiport resonators. A series resonant oscillator design is discussed that utilizes a unique, gain-controllable transresistance sustaining amplifier. We show that in the absence of an automatic level control loop, the closed-loop, steady-state oscillation amplitude of this oscillator depends strongly upon the dc-bias voltage applied to the capacitively driven and sensed /spl mu/resonator. Although the high-Q of the micromechanical resonator does contribute to improved oscillator stability, its limited power-handling ability outweighs the Q benefits and prevents this oscillator from achieving the high short-term stability normally expected of high-Q oscillators.

A low-noise, 900-MHz VCO in 0.6-/spl mu/m CMOS

Abstract: This paper describes a low-noise, 900-MHz, voltage-controlled oscillator (VCO) fabricated in a 0.6-/spl mu/m CMOS technology. The VCO consists of four-stage fully differential delay cells performing full switching. It utilizes dual-delay path techniques to achieve high oscillation frequency and obtain a wide tuning range. The VCO operates at 750 MHz to 1.2 GHz, and the tuning range is as large as 50%. The measured results of the phase noise are -101 dBc/Hz at 100-kHz offset and -117 dBc/Hz at 600-kHz offset from the carrier frequency. This value is comparable to that of LC-based integrated oscillators. The oscillator consumes 10 mA from a 3.0-V power supply. A prototype frequency synthesizer with the VCO is also implemented in the same technology, and the measured phase noise of the synthesizer is -113 dSc/Hz at 100-kHz offset.

Integrated GHz Voltage Controlled Oscillators

Abstract: The voltage controlled oscillator (VCO) is a critical sub-block in communications transceivers. The role of the VCO in a transceiver and the VCO requirements are first reviewed. The necessity of GHz VCOs and the driving factors towards the monolithic integration of the VCO are examined. VCO design techniques are outlined and design trade-offs are explored. The performance of VCOs in different implementation styles is compared to evaluate when and if VCO integration is desirable.

A low-noise, low-power VCO with automatic amplitude control for wireless applications

Abstract: Voltage controlled oscillators (VCOs) used in portable wireless communications applications, such as cellular telephony, are required to achieve low phase-noise levels while consuming minimal power. This paper presents the design challenges of a VCO with automatic amplitude control, which operates in the 300 MHz to 1.2 GHz frequency range using different external resonators. The VCO phase noise level is -106 dBc/Hz at 100-KHz offset from an 800-MHz carrier, and it consumes 1.6 mA from a 2.7-V power supply. An extensive phase-noise analysis is employed for this VCO design in order to identify the most important noise sources in the circuit and to find the optimum tradeoff between noise performance and power consumption.

A 108-GHz InP-HBT monolithic push-push VCO with low phase noise and wide tuning bandwidth

Abstract: This paper reports on what is believed to be the highest frequency bipolar voltage-controlled oscillator (VCO) monolithic microwave integrated circuit (MMIC) so far reported. The W-band VCO is based on a push-push oscillator topology, which employs InP HBT technology with peak f/sub T/'s and f/sub max/'s of 75 and 200 GHz, respectively. The W-band VCO produces a maximum oscillating frequency of 108 GHz and delivers an output power of +0.92 dBm into 50 /spl Omega/. The VCO also obtains a tuning bandwidth of 2.73 GHz or 2.6% using a monolithic varactor. A phase noise of -88 dBc/Hz and -109 dBc/Hz is achieved at 1- and 10-MHz offsets, respectively, and is believed to be the lowest phase noise reported for a monolithic W-band VCO. The push-push VCO design approach demonstrated in this work enables higher VCO frequency operation, lower noise performance, and smaller size, which is attractive for millimeter-wave frequency source applications.

Direct digital synthesis of precise, stable angle modulated RF signal

Abstract: An RF modulator that allows precise, stable phase shifts to be obtained. The modulator uses a PLL structure including an auxiliary feedforward path including an adaptive gain amplifier (411) used to inject a modulation signal into the PLL at a point past a loop filter (403). A phase demodulator (419) recovers from the output of the PLL phase information which is compared in a comparator (417) to the phase information of the modulation signal. A resulting error signal is used to control the gain of the adaptive gain amplifier (411). The modulator compensates for variability of the VCO (405) and other components of the PLL.

The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as a multibit quantizer

Abstract: This brief proposes a new- architecture for the oversampling delta-sigma analog-to-digital converter (ADC) utilizing a voltage controlled oscillator (VCO). The VCO, associated with a pulse counter, works as a high-speed quantizer. This VCO quantizer also has the function of first-order noise shaping because the phase of the output pulse is an integrated quantity of the input voltage. If the maximum VCO frequency (fvm) is designed in the range of (2/sup bq/-2)fos

A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz

Abstract: A fully integrated, phase-locked loop (PLL) clock generator/phase aligner for the POWER3 microprocessor has been designed using a 2.5-V, 0.40-/spl mu/m digital CMOS6S process. The PLL design supports multiple integer and noninteger frequency multiplication factors for both the processor clock and an L2 cache clock. The fully differential delay-interpolating voltage-controlled oscillator (VCO) is tunable over a frequency range determined by programmable frequency limit settings, enhancing yield and application flexibility. PLL lock range for the maximum VCO frequency range settings is 340-612 MHz. The charge-pump current is programmable for additional control of the PLL loop dynamics. A differential on-chip loop filter with common-mode correction improves noise rejection. Cycle-cycle jitter measurements with the microprocessor actively executing instructions were 10.0 ps rms, 80 ps peak to peak (P-P) measured from the clock tree. Cycle-cycle jitter measured for the processor in a reset state with the clock tree active was 8.4 ps rms, 62 ps P-P. PLL area is 1040/spl times/640 /spl mu/m/sup 2/. Power dissipation is <100 mW.

A 6.5 GHz monolithic CMOS voltage-controlled oscillator

Abstract: Phase noise and frequency tuning range are key performance parameters of high-frequency voltage-controlled oscillators (VCOs). To achieve low phase noise, LC sinusoidal oscillators with high quality factor (Q) are preferred to other topologies, such as inverter-based ring oscillators. The frequency tuning of LC oscillators can be readily achieved with varactor diodes either on-chip or external. The frequency tuning range is often limited by low supply voltage and maximum variable capacitance available to varactors at high frequencies when on-chip inductors are used. Other frequency tuning approaches include varying current in the resonator to alter effective capacitance, or varying relative weighting between two different LC resonators. While the former approach varies loop gain in addition to the phase, the latter requires careful choice of the resonators and their Qs for stable oscillations. This VCO architecture incorporates two coupled fixed-frequency LC oscillators to generate a variable-frequency output by varying the coupling between two oscillators.

Configurable single and dual vcos for dual- and tri-band wireless communication systems

Abstract: A wireless communication with a receiver subsystem capable of supporting communications operating on two or three distinct frequency bands while incorporating only one or two oscillating devices, respectively. For example, such a subsystem could be integrated in a wireless communication hand-held device configured to operate within three frequency ranges in order to support Cellular, PCS, and GPS services. The receiver subsystem includes a receiver subsystem front end configured to receive first, second, and third receive signals operating under three different frequency bands. The three receive signals are subjected to front-stage filtering, low-noise amplifier, and bandpass filtering in order to remove any unwanted radio frequency components. The first signal is subsequently down-converted into an IF signal by mixing it with a first reference signal generated by a first voltage controlled oscillator (VCO). The first VCO operates with a frequency band that is broader than necessary and generates the first reference signal with a predetermined frequency such that the mixing operation produces a specific common IF frequency. The second signal and third signals are similarly down-converted to a second common IF signal by mixing it with a second reference signal generated by a second voltage controlled oscillator (VCO). The present invention also includes a VCO feedback control loop, including a phased-lock-loop, for maintaining the accuracy and stability of the frequency signals produced by the first and second VCOs.

Method and apparatus for compensating a spread spectrum clock generator

Abstract: An improved spread spectrum clock generator circuit is provided which automatically compensates for variations in passive component values and system gain and charge pump current in a Phase Locked Loop circuit. The pulse widths of the UP and DOWN outputs of the Phase Frequency Detector are monitored at particular intervals to determine the deviation error of these UP and DOWN signals, as compared to typical or nominal pulse-width durations. After an error is determined in the actual values of the pulse-width durations, the Phase Locked Loop (PLL) system is adjusted depending upon the magnitude and direction of the error signal. Changes in the PLL gain parameters, especially the VCO gain and charge pump current, have a significant effect on the PFD outputs, such that the width of the UP and DOWN signals vary as the frequency changes along the spread spectrum profile. At one portion of the spread spectrum profile, the “peak” (i.e., maximum) pulse width of these UP and DOWN signals will be a function of the spread spectrum's modulation profile and the PLL parameters. In addition to sampling for maximum pulse widths at the profile locations exhibiting peaks and valleys, the actual error profile may also exhibit a similarly large deviation from the target error profile at times just before the occurrence of the maximum peak and minimum peak (or “valley”). While determining precisely where within the profile these other substantial deviations occur is more difficult than monitoring the same signals at their maximum peaks, there are certain advantages to using the alternative locations along the error profile, which are described below.

Analysis of oscillators with external feedback loop for improved locking range and noise reduction

Abstract: A simple scheme for enhancing the locking/capture range and phase-noise performance of FET-based voltage-controlled oscillators (VCO's) is presented using a low-pass feedback loop from the oscillator output to the varactor tuning port. The nonlinearity of the FET provides for mixer or phase detector behavior (a self-oscillating mixer). The resulting feedback oscillator advantageously combines the principles of a conventional injection-locked oscillator (ILO) and phase-locked loop (PLL), which we refer to as an injection-locked phase-locked loop (ILPLL). The analysis suggests that the ILPLL can be designed for superior near-carrier phase-noise performance compared with conventional ILO or PLL circuits. A 10-GHz prototype was fabricated, which demonstrated a locking range more than double that of the isolated VCO injection-locking range over the same range of injected signal power.

Wideband modulated fractional-N frequency synthesizer

Abstract: A direct modulation multi-accumulator fractional-N frequency synthesizer 1 for generating a carrier signal 150 modulated by a modulation signal 170, 121 is disclosed. The frequency synthesizer includes a Voltage Controlled Oscillator, VCO 50, having a tuning port for controlling the frequency of the signal 110 output by the VCO, a variable divider 20 and a multi-accumulator sequence generator 21 for controlling the variable divider, a reference signal generator 50, a phase detector 30 and a low pass filter 40. These elements are arranged to form a Phase Locked Loop arrangement, the directly modulated output signal of which is taken from the output of the VCO, wherein in-band modulation is performed by varying the variable divider and out-of-band modulation is performed by directly applying the modulating signal to the VCO tuning port.

Precision frequency and phase synthesis

Abstract: An electronic system, such as a video decoder ( 80 ), includes a clock generator circuit ( 22, 22′ ) based upon a phase-locked loop (PLL) ( 25 ). The PLL ( 25 ) includes a voltage controlled oscillator (VCO) ( 30 ) that produces a plurality of evenly-spaced output phases, each of a locked frequency relative to a reference clock (CREF). A frequency synthesis circuit ( 27 ) receives a frequency selection value on control lines (FREQ) that include an integer and a fraction portion. The integer and fraction portion of the frequency selection value are added to the current contents of a register ( 40 ) that stores the previous integer value used to select the corresponding phase from VCO ( 30 ) for application to the clock input of a toggle flip-flop ( 36 ) from which the output clock (COUT) is generated. Use of the fraction portion permits a time-averaged clock frequency to be produced with more precision than the multiple phases output by the VCO ( 30 ). Alternative embodiments include multiple frequency synthesis circuits ( 27 ) based upon the same PLL ( 25 ), and the generation of a phase-shifted secondary output from a phase synthesis circuit ( 29 ) that is slaved to the frequency synthesis circuit ( 27 ). Additional performance is obtained by providing separate paths ( 52 a , 52 b ) for producing the leading and trailing edges of the output clock (COUT).

A 2.6 GHz/5.2 GHz CMOS voltage-controlled oscillator

Abstract: New wireless local area network (WLAN) standards have recently emerged in the 5 GHz band. For example, high performance radio LAN (HIPERLAN) is a European standard operating at 5.2 GHz with Gaussian minimum shift keying (GMSK) modulation and a 23 MHz channel bandwidth. The voltage-controlled oscillator reported here is to be used in a HIPERLAN transceiver. Here, the receiver employs two downconversion steps, each with a 2.6 GHz local oscillator (LO) frequency, translating the RF spectrum to dc. The second downconversion thus requires the quadrature phases of the LO. The transmitter performs modulation by first placing the VCO in a synthesizer loop and subsequently opening the loop and applying the Gaussian-shaped baseband data to the VCO to perform GMSK modulation.

Low-voltage, low-jitter voltage controlled oscillator

Abstract: A low-voltage, low-jitter voltage controlled oscillator according to the invention includes a plurality of delay units electrically connected in series to form a closed loop circuit. Each delay unit has a symmetric differential structure constituted by a plurality of MOS FETs. Furthermore, only two transistors are stacked between the power source and ground. Thus, the low-voltage, low-jitter voltage controlled oscillator can operate at low voltage, and can not be affected by the variation of the power source voltage.

The design of an all-digital phase-locked loop with small DCO hardware and fast phase lock

Abstract: The cores of the all-digital phase-locked loop (ADPLL) are the switch-tuning digital control oscillator (DCO) and the architecture, In this brief, we propose a DCO with reduced hardware cost, and architecture with characteristics of fast frequency locking, full digitization, easy design and implementation, and good stability. It is suitable to be used as the clock generator for high-performance microprocessors. The prototype of a 3.3-V ADPLL chip has been designed by TSMC's 0.6 /spl mu/m SPDM CMOS process. The simulation shows that this ADPLL can operate in the range between 60 and 400 MHz, and at four times the reference clock frequency. The phase-lock process takes 47 clock cycles, and the phase error is less than 0.1 ns.

Internal oscillator circuit including a ring oscillator controlled by a voltage regulator circuit

Abstract: An oscillator circuit residing internally to a semiconductor device for generating a clock signal for use by digital circuits. The oscillator circuit includes a voltage regulator circuit responsive to frequency selection signals for selecting a predetermined frequency and a supply voltage. The voltage regulator circuit is operative to generate a voltage reference signal having a voltage level being adjusted to compensate for variations due to temperature, process and supply voltage variations. The oscillator circuit further includes a ring oscillator circuit responsive to the voltage reference signal for generating a clock out signal having a particular frequency based upon the voltage level of the voltage reference signal. Wherein the frequency of the clock out signal remains substantially constant despite temperature, process and supply voltage variations in the semiconductor circuit.

Voltage controlled oscillator utilizing threshold voltage control of silicon on insulator MOSFETS

Abstract: A voltage controlled ring oscillator (VCRO) that can operate at low voltage and provide a variable periodic output. A plurality of transistors form a ring oscillator and a selected transistor in the ring oscillator has a body which can float with respect to ground potential. The selected transistor has a threshold voltage which is controllable by a voltage applied to the transistor body. A control input is coupled to the transistor body such that the body of the transistor can be charged by the control input. Charging the body alters the threshold voltage of the transistor and thereby controls the oscillation frequency of the oscillator.

Very wide range tunable CMOS/bipolar current mirrors with voltage clamped input

Abstract: In low power current mode signal processing circuits it is often necessary to use current mirrors to replicate and amplify/attenuate current signals and clamp the voltage of nodes with high parasitic capacitances so that the smallest currents do not introduce unacceptable delays. The use of tunable active-input current mirrors would meet both requirements. In conventional active-input current mirrors, stability compensation is required. Furthermore, once stabilized, the input current cannot be made arbitrarily small. In this paper we introduce two new active-input current mirrors that clamp their input node to a given voltage. One of them does not require compensation, while the other may under some circumstances. However, for both, the input current may take any value. The mirrors can operate with their transistors biased in strong inversion, weak inversion, or even as CMOS compatible lateral bipolar devices. If it is biased in weak inversion or as lateral bipolars, the current mirror gain can be tuned over a very wide range. According to the experimental measurements provided in this paper, the input current may spawn beyond nine decades and the current mirror gain can be tuned over 11 decades. As an application example, a sinusoidal g/sub m/-C-based VCO has been fabricated, whose oscillation frequency could be tuned for over seven decades, between 73 mHz and 1 MHz.

VCO jitter simulation and its comparison with measurement

Abstract: We have simulated the phase noise of a voltage controlled oscillator (VCO) using an RF circuit simulator, SpectreRF/sup TM/. This simulator uses a variation of the periodic noise analysis first proposed by Okumura, et al (1993). It computes the power spectral density of the noise as a function of frequency. By assuming that only white noise sources are present in the oscillator, it is possible to derive a simple relationship between the level of the phase noise and the jitter. This excludes flicker noise from consideration, however, since flicker noise is a low-frequency phenomenon, excluding it only affects the accuracy of the long-term jitter. We compared the jitter with measurement and found the error to be less than 2 dB. An AHDL model for the VCO that efficiently exhibits jitter in the time domain is included. The model was written in Verilog-A. This model can be used to determine the affect of VCO jitter on a larger system, such as a phase-locked loop (PLL).

Method and apparatus for fully integrating a voltage controlled oscillator on an integrated circuit

Abstract: A method and apparatus for fully integrating a Voltage Controlled Oscillator (VCO) on an integrated circuit. The VCO is implemented using a differential-mode circuit design. The differential-mode implementation of the VCO preferably comprises a differential mode LC-resonator circuit, a digital capacitor, a differential pair amplifier, and a current source. The LC-resonator circuit includes at least one tuning varactor and two high Q inductors. The tuning varactor preferably has a wide tuning capacitance range. The tuning varactor is only used to 'fine-tune' the center output frequency fo of the VCO. The center output frequency fo is coarsely tuned by the digital capacitor. The VCO high Q inductors comprise high gain, high self-resonance, and low loss IC inductors. The IC VCO is fabricated on a high resistivity substrate material using a trench isolated guard ring. The guard ring isolates the fully integrated VCO, and each of its component parts, from RF signals that may be introduced into the IC substrate by other devices. By virtue of the improved performance characteristics provided by the digital capacitor, the analog tuning varactor, the high Q inductor, and the trench isolated guard ring techniques, the inventive VCO is fully integrated despite process variations in IC fabrication.

Computer based fast phase difference measuring unit and PLL using same

Abstract: A system for measuring a phase difference between two input signals, including a computer performing computations in the complex domain and operating on two complex signals indicative of the two input signals respectively to compute the phase difference. Alternately, the system for measuring the phase difference includes a computer operating on two input buses indicative of the two input signals respectively to generate a signal indicative of the phase difference, and wherein: A. each input bus includes at least two digital bits; B. the two input buses are indicative of the phase of each of the two input signals; C. the two input buses each has a different range of possible values and wherein the computer further includes a device for normalizing at least one of the buses so as to bring the two buses to the same range. A phase-lock loop includes the system for measuring the phase difference, a VCO and digital devices.

A novel two-beam scanning active leaky-wave antenna

Abstract: A novel two-beam scanning active leaky-wave antenna (LWA) has been developed. This LWA with a two-terminal feeding microstrip line structure is integrated with a varactor-tuned X-band high-electron mobility transistor (HEMT) voltage-controlled oscillator (VCO). The signal of the VCO is injected via a T-divider into the radiating element. To excite the first higher order mode, the designed antenna is fed asymmetrically at both ends of the microstrip line. Compared with single-terminal feeding leaky-wave antennas, this configuration offers the advantages of dual-direction and suppression of the reflected wave caused by the open end of the radiating element. The scanning angle is steered over a range of 24-46/spl deg/ for the right beam and 128-150/spl deg/ for the left beam. The effective isotropic radiated power (EIRP) is calculated to be 17.5 and 16.67 dBm at 10.4 GHz, respectively. The measured return loss S/sub 11/ is less than -10 dB in the range of 9-11.5 GHz. The transmission coefficient S/sub 21/ indicates that the power radiates into the space.

A process and temperature compensated ring oscillator

Abstract: An on-chip oscillator with small frequency variation in a digital 0.6 /spl mu/m CMOS technology is described. The oscillator utilizes a bias technique to compensate for the influences on the oscillation frequency caused by both temperature and process variations. No external components are needed in the oscillator. Simulation results show that the frequency of the proposed oscillator has a peak variation of /spl plusmn/6.8% for all process corners and a temperature range of 120/spl deg/C. The oscillator is measured to operate at a center frequency of 680 kHz and have a peak variation of /spl plusmn/4.7% over 29 sample chips in two different lots and a temperature range of 35/spl deg/C to 115/spl deg/C. As a comparison, a conventional inverter chain oscillator is made on the same chip. The frequency variation of the conventional inverter chain is /spl plusmn/14.6%.

A 9.8 GHz back-gate tuned VCO in 0.35 /spl mu/m CMOS

Abstract: A fully-integrated voltage controlled oscillator (VCO) has been one of the focal points of CMOS RF design activities in recent years. As potential applications extend to higher frequencies, CMOS VCO designs have pushed from ultra-high frequency (UHF) into super-high frequency (SHF). The requirement for fully-integrated VCOs to operate with low voltage, low power and low phase noise usually leads to the use of relatively large transistors in a process where the quality factor (Q) of the resonant tank is low. As the operating frequency further increases, the designs become more difficult due to the large parasitic capacitance and poor high-frequency performance of the transistors. This circuit demonstrates a technique which makes a transistor parasitic capacitance tunable through the use of its back-gate thereby reducing or eliminating the need for a varactor. In other words, the functionalities of transconductance (gm) and variable capacitance (/spl Delta/C) are realized in the MOS transistors at the same time by utilizing (where it is possible) all the four terminals of the transistors.

Device for rf control

Abstract: A method and a system are disclosed for providing automatic frequency tuning for an RF electrode accelerating system in a cyclotron device (3) for production of PET isotopes. A controlled frequency oscillator (5) generates an RF signal of a predetermined frequency for the acceleration of an ion beam in the cyclotron, and a matched power transmission line (2) connects to and feeds the RF electrode system (10). A load phase sensor (8) connected between the RF signal generator and the matched power transmission line (2) feeds a detected load phase to a feedback amplifier (9), which produces an error signal connected to the controlled frequency oscillator (5) for a fine tuning of the frequency of the controlled frequency oscillator, whereby the frequency of the RF power signal is continuously optimised for a maximum transfer of high voltage driving to the RF electrode accelerating system of the cyclotron.

A 2-1600 MHz 1.2-2.5 V CMOS clock-recovery PLL with feedback phase-selection and averaging phase-interpolation for jitter reduction

Abstract: The clock-recovery PLL requires >50% VCO tuning range to accommodate CMOS process variations. In a macro-cell PLL used in applications at different frequencies, the tuning range must be even larger. This requires special techniques for initial locking, since no phase detector for NRZ data operates reliability with a large initial frequency offset. A modification of the circuit results in a PLL that first generates a number of clock phases and than selects one of these phases as the recovered clock. In most communication systems, the data rate is specified to within a few hundred ppm, so an appropriate choice of f/sub ref/ and N makes the generated clocks have a frequency close to the data rate, avoiding initialization/start-up procedures.

Third-order self-biased phase-locked loop for low jitter applications

Abstract: A self-biased phase-locked loop circuit includes a phase detector, first and second charge pumps, first and second loop filters, and a voltage-controlled oscillator (VCO). The phase detector is configured to measure a phase offset between two input signals, and to generate pulses corresponding to the phase offset. The first and second charge pumps are configured to provide charge corresponding to the pulses. The first and second loop filters are coupled to outputs of the first and second charge pumps, respectively. The filters operate to provide a control signal responsive to the charge. The VCO is configured to adjust its output frequency in response to the control signal. The second loop filter capacitor considerably improves the output clock jitter.

A 1.24-GHz monolithic CMOS VCO with phase noise of -137 dBc/Hz at a 3-MHz offset

Abstract: For the first time, a 1.24-GHz CMOS voltage-controlled oscillator (VCO) with an integrated resonator which satisfies the Global System for Mobile communications (GSM) phase noise requirement at a 3-MHz offset is presented. The measured phase noise is -88, -125, and -137 dBc/Hz at 10-kHz, 600-kHz, and 3-MHz offsets, respectively. The VCO is implemented in a low-cost 0.8-/spl mu/m foundry CMOS process exclusively using pMOS transistors which have greater than one order of magnitude lower 1/f noise than that of nMOS transistors. The tuning range is /spl sim/130 MHz for the control voltages between 0.5 and 3.0 V. The VCO core runs on 22 mA from a 3-V power supply.